AT25P1024_06 ATMEL

Document overview

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  • PDF pages: 17

Technical content

Features

  • Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1)  2.1 MHz Clock Rate  128-byte Page Mode Only for Write Operations  Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V)  Block Write Protection – Protect 1/4, 1/2, or Entire Array  Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection  Self-Timed Write Cycle (5 ms Typical)  High Reliability – Endurance: 100,000 Write Cycles – Data Retention: >40 Years  20-lead JEDEC SOIC and 8-lead Leadless Array Package

Description

The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT25P1024 is available in space saving 20-lead JEDEC SOIC and 8-lead LAP packages. The AT25P1024 is enabled through the Chip Select pin (CS ) and accessed via a 3- wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Table 1. Pin Configurations

2 AT25P1024

Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. used to suspend any serial communication without resetting the serial sequence. Figure 1. Block Diagram

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL and VIH max are reference only and are not tested. Table 2. Pin Capacitance(1) Table 3. DC Characteristics

4 AT25P1024

Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics

1.0 MHz

1082I–SEEPR–7/06 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the serial cloc k pin (SCK) is always an input, the AT25P1024 always operates as a slave. TRANSMITTER/RECEIVER: The AT25P1024 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25P1024, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25P1024 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25P1024. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial comm unication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the inter nal write cycle has already been initiated, WP going low will have no effect on any write operation to the stat us register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25P1024 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

6 AT25P1024

Figure 2. SPI Serial Interface

1082I–SEEPR–7/06 Functional The AT25P1024 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25P1024 utilizes an 8-bit instruction regi ster. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is indepen- dent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The Ready /Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 5. Instruction Set for the AT25P1024 Table 6. Status Register Format

8 AT25P1024

levels and corresponding status register control bits are shown in Table 8. the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. Table 7. Read Status Register Bit Definition Bits 4-6 are “0”s when device is not in an internal write cycle. Bits 0-7 are “1”s during an internal write cycle. Table 8. Block Write Protect Bits Table 9. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

will be ignored except the RDSR instruction. during the SCK low time immediately after clocking in the D0 (LSB) data bit. the write programming cycle. ically returned to the write disable state at the completion of a write cycle. ing edge is required to re-initiate the serial communication.

1 Low 1 Protected Writable Protected

Table 10. Address Key Table 9. WPEN Operation (Continued)

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Figure 3. Synchronous Data Timing Figure 4. WREN Timing Figure 5. WRDI Timing

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Figure 9. WRITE Timing Figure 10. HOLD Timing

1082I–SEEPR–7/06 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. 2. “U” designates Green Package & RoHS Compliant. Ordering Information(1) Ordering Code Package Operation Range AT25P1024C1-10CI-2.7 AT25P1024W1-10SI-2.7 8C1 20S2 Industrial (-40°C to 85°C) AT25P1024C1-10CU-2.7(2) AT25P1024W1-10SU-2.7(2) 8C1 20S2 Lead-Free\\Halogen-Free Industrial Temperature (-40°C to 85°C) Package Type 8C1 8-pad, 0.300" Wide, Leadless Array Package (LAP) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options -2.7 Low-voltage (2.7V to 5.5V)

14 AT25P1024

1082I–SEEPR–7/06 Packaging Information 8C1 – LAP 1150 E.Cheyenne Mtn Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) B8CN1 11/8/04 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.36 0.41 0.46 1 D 7.90 8.00 8.10 E 4.90 5.00 5.10 e 1.27 BSC e1 0.60 REF L 0.62 .0.67 0.72 1 L1 0.92 0.97 1.02 1 Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm Pin1 Corner Marked Pin1 Indentifier 0.10 mm TYP Top View L b e Side View A Bottom View E D

1082I–SEEPR–7/06 20S2 – JEDEC SOIC

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 1/9/02 20S2 A COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. A 0.0926 0.1043 A1 0.0040 0.0118 b 0.0130 0.0200 4 C 0.0091 0.0125 D 0.4961 0.5118 1 E 0.2914 0.2992 2 H 0.3940 0.4190 L 0.0160 0.050 3 e 0.050 BSC L End View Side View Top View HE b N e A D C

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1082I–SEEPR–7/06

Revision History

Doc. Rev. Comments 1082I Added Note ‘Not Recommended for new design; please refer to AT25FS010 datasheet’ to first page.

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