AT25P1024 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 13

Technical content

Features

  • Serial Peripheral Interface (SPI) Compatible
  • Supports SPI Modes 0 (0,0) and 3 (1,1)
  • 2.1 MHz Clock Rate
  • 128-Byte Page Mode Only for Write Operations
  • Low Voltage and Standard Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V)
  • Block Write Protection – Protect 1/4, 1/2, or Entire Array
  • Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
  • Self-Timed Write Cycle (5 ms Typical)
  • High Reliability – Endurance: 100,000 Write Cycles – Data Retention: >40 Years – ESD Protection: >3000V
  • 20-Pin JEDEC SOIC and 8-Pin Leadless Array Package

Description

The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT25P1024 is available in space saving 20-pin JEDEC SOIC and 8-pin leadless array (LAP) packages. Rev. 1082C–08/98 SPI Serial EEPROMs 1M (131,072 x 8) AT25P1024 Preliminary Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect (continued) 20-Lead SOIC CS SO NC NC NC NC NC NC WP GND VCC HOLD NC NC NC NC NC NC SCK SI 8-Pin LAP Bottom View VCC HOLD SCK SI CS SO WP GND

The AT25P1024 is enabled through the Chip Select pin (CS ) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self- timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write pro- tection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to pro- tect against inadvertent write attempts to the status regis- ter. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram Absolute Maximum Ratings* Voltage on Any Pin 131,072 x 8

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL and VIH max are reference only and are not tested. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions Max Units Conditions C OUT Output Capacitance (SO) 8 pF V OUT = 0V C IN Input Capacitance (CS, SCK, SI, WP, HOLD)6 p F V IN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 3.6 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current V CC = 5.0V at 1 MHz, SO = Open Read 2.0 5.0 mA ICC2 Supply Current V CC = 5.0V at 2 MHz, SO = Open Write 4.0 7.0 mA ISB1 Standby Current V CC = 1.8V , CS = VCC 0.1 3.0 µA ISB2 Standby Current V CC = 2.7V , CS = VCC 0.2 3.0 µA ISB3 Standby Current V CC = 5.0V , CS = VCC 2.0 7.0 µA IIL Input Leakage V IN = 0V to VCC -3.0 3.0 µA IOL Output Leakage V IN = 0V to VCC , TAC = 0°C to 70°C- 3 . 0 3 . 0 µA VIL (1) Input Low Voltage -0.6 V CC x 0.3 V VIH (1) Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage 4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V VOH1 Output High Voltage I OH = -1.6 mA V CC - 0.8 V VOL2 Output Low Voltage 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V VOH2 Output High Voltage I OH = -100 µAV CC - 0.2 V

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, C L = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2.1 1.0 0.5 MHz tRI Input Rise Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 µs tFI Input Fall Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 µs tWH SCK High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 400 800 ns tWL SCK Low Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 400 800 ns tCS CS High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 500 1000 ns tCSS CS Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 250 1000 ns tCSH CS Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 150 250 1000 ns tSU Data In Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 ns tH Data In Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 ns tHD Hold Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 400 ns tCD Hold Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 300 400 ns tV Output Valid 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 400 800 ns tHO Output Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 ns

Note: 1. This parameter is characterized and is not 100% tested. tLZ Hold to Output Low Z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 200 300 ns t HZ Hold to Output High Z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 200 300 ns t DIS Output Disable Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 250 1000 ns t WC Write Cycle Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 ms Endurance (1) 5.0V , 25°C, Page Mode 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100K Write Cycles AC Characteristics (Continued) Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, C L = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units

Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25P1024 always operates as a slave. TRANSMITTER/RECEIVER: The AT25P1024 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25P1024, and the serial out- put pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25P1024 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25P1024. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status regis- ter. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25P1024 in a system with the WP pin tied to ground and still be able to write to the status regis- ter. All WP pin functions are enabled when the WPEN bit is set to “1”. SPI Serial Interface MASTER: MICROCONTROLLER SLAVE: AT25P1024 DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS

type series of microcontrollers. Register instruction provides access to the status register. tion. The AT25P1024 is divided into four array segments. control bits are shown in Table 4. block-protected sections in the memory array are disabled. Table 1. Instruction Set for the AT25P1024 Table 2. Status Register Format Table 3. Read Status Register Bit Definition Bits 4-6 are 0s when device is not in an internal write cycle. Bits 0-7 are 1s during an internal write cycle. Table 4. Block Write Protect Bits

entire memory to be read in one continuous READ cycle. AT25P1024, two separate instructions must be executed. mands will be ignored except the RDSR instruction. edge is required to re-initiate the serial communication. Table 5. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

Table 6. Address Key

Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing WREN Timing WRDI Timing SO VOH VOL HI-Z HI-Z tV VALID INSI VIH VIL tHtSU tDIS SCK V IH VIL tWH tCSH CS V IH VIL tCSS tCS tWL tHO

0123456789 1 0 1 1 1 2 1 3 1 4 SI INSTRUCTION SO 76543210 DATA OUT MSB HIGH IMPEDANCE CS SI SCK HIGH IMPEDANCE INSTRUCTION 3-BYTE ADDRESS 01234 8 9 10 11 28 23 22 21 3... 21 321 29 30 31 32 33 34 35 36 37 38 SO

1st BYTE DATA-IN 128th BYTE DATA-IN INSTRUCTION HIGH IMPEDANCE 0123456789 1 0 1 1 2 8 2 3 2 2 2 1 3 10 6543210 72 29 30 31 32 33 34 1051 1052 1054 1053 1055 SO SCK HOLD tCD tHD tHZ tLZ tCD tHD CS

Ordering Information

tWC (max) (ms) ICC (max) (µµµµA) ISB (max) (µµµµA) fMAX (kHz) Ordering Code Package Operation Range 5 7000 7.0 2100 A T25P1024C1-10CC A T25P1024W1-10SC 8C1 20S Commercial (0°C to 70°C) 7000 7.0 2100 A T25P1024C1-10CI A T25P1024W1-10SI 8C1 20S Industrial (-40°C to 85°C) 10 2000 3.0 1400 A T25P1024C1-10CC-2.7 A T25P1024W1-10SC-2.7 8C1 20S Commercial (0°C to 70°C) 2000 3.0 1000 A T25P1024C1-10CI-2.7 A T25P1024W1-10SI-2.7 8C1 20S Industrial (-40°C to 85°C) 10 1000 3.0 500 A T25P1024C1-10CC-1.8 A T25P1024W1-10SC-1.8 8C1 20S Commercial (0°C to 70°C) 1000 3.0 500 A T25P1024C1-10CI-1.8 A T25P1024W1-10SI-1.8 8C1 20S Industrial (-40°C to 85°C) Package Type 8C1 8-Lead, 0.300" Wide, Leadless Array Package (LAP) 20S 20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 3.6V)

5.15 (0.203) 4.85 (0.191) 8.15 (0.321) 7.85 (0.309) 0.42 (0.017) 0.34 (0.013) 1.30 (0.051) 1.00 (0.039) 1.27 (0.050) TYP 0.41 (0.016) TYP 0.64 (0.025) TYP TOP VIEW SIDE VIEW BOTTOM VIEW 0.299 (7.60) 0.291 (7.39) 0.020 (0.508) 0.013 (0.330) 0.420 (10.7) 0.393 (9.98) PIN 1 .050 (1.27) BSC 0.513 (13.0) 0.497 (12.6) 0.012 (0.305) 0.003 (0.076) 0.105 (2.67) 0.092 (2.34)

8 REF

0.035 (0.889) 0.015 (0.381) 0.013 (0.330) 0.009 (0.229) 8C1 , 8-Lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) 20S, 20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters)