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Technical content
Features
Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Datasheet describes Mode 0 operation Low-voltage operation VCC = 1.7V to 5.5V High frequency operation 20MHz clock rate capable from 4.5V to 5.5V VCC 10MHz clock rate capable from 2.5V to 5.5V VCC 5MHz clock rate capable from 1.7V to 5.5V VCC 256-byte Page Mode and Byte Write operation supported Block Write protection Protect ¼, ½, or entire array Write Protect (WP) pin and Write Disable instructions for both hardware and software data protection Self-timed write cycle (5ms max) High-reliability Endurance: 1,000,000 write cycles Data retention: 100 years Green package options (Pb/Halide-free/RoHS compliant) 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, and 8-ball WLCSP Die sales options: wafer form, waffle pack and bumped die
Description
The Atmel® AT25M01 provides 1,048,576 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 131,072 words of eight bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25M01 is enabled through the Chip Select pin ( CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write. Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Atmel AT25M01 SPI Serial EEPROM 1-Mbit (131,072 x 8) DATASHEET
- Pin List and Configurations
Figure 1. Pin Configurations
- Absolute Maximum Ratings*
3Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 3. Block Diagram VCC GND SI SCK SO Status Register Memory Array 131,072 x 8 Address Decoder Data Register Output Buffer Mode Decode Logic Clock Generator HOLD CS WP
4Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 4. Electrical Specifications Table 4-1. Pin Capacitance (1) Note: 1. This parameter is characterized and is not 100% tested. Table 4-2. DC Characteristics Note: 1. V IL min and VIH max are reference only and are not tested. Applicable over recommended operating range from TA = 25°C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted). Symbol Test Conditions Max Units Conditions COUT Output Capacitance (SO) 8 pF VOUT = 0V CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = 1.7V to 5.5V, (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.7 5.5 V VCC2 Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V at 20MHz, SO = Open, Read 7.0 10.0 mA ICC2 Supply Current VCC = 5.0V at 10MHz, SO = Open, Read, Write 5.0 7.0 mA ICC3 Supply Current VCC = 5.0V at 1MHz, SO = Open, Read, Write 2.2 3.5 mA ISB1 Standby Current VCC = 1.7V, CS = VCC 0.2 3.0 μA ISB2 Standby Current VCC = 2.5V, CS = VCC 0.4 3.0 μA ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 μA IIL Input Leakage VIN = 0V to VCC –3.0 3.0 μA IOL Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C –3.0 3.0 μA VIL (1) Input Low-voltage –1.0 VCC x 0.3 V VIH (1) Input High-voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low-voltage 3.6 VCC 5.5V IOL = 3.0mA 0.4 V VOH1 Output High-voltage IOH = 1.6mA VCC –0.8 V VOL2 Output Low-voltage 1.7V VCC 3.6V IOL = 0.15mA 0.2 V VOH2 Output High-voltage IOH = 100μA VCC –0.2 V
5Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 Table 4-3. AC Characteristics Applicable over recommended operating range from TAI = –40°C to + 85°C, VCC = As Specified, CL = 1TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V MHz tRI Input Rise Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V μs tFI Input Fall Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V μs tWH SCK High Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns tWL SCK Low Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns tCS CS High Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 100 200 ns tCSS CS Setup Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 100 200 ns tCSH CS Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 100 200 ns tSU Data In Setup Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns tH Data In Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns tHD Hold Setup Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns tCD Hold Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns tV Output Valid 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns tHO Output Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ns
6Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 Notes: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. tLZ Hold to Output Low Z 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 ns tHZ Hold to Output High Z 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 ns tDIS Output Disable Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 ns tWC Write Cycle Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V ms Endurance(1) 25°C, Page Mode, 5.0V 1,000,000 Write Cycles Table 4-3. AC Characteristics (Continued) Applicable over recommended operating range from TAI = –40°C to + 85°C, VCC = As Specified, CL = 1TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units
7Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 5. Serial Interface Description Master: The device that generates the serial clock. Slave: Because the Serial Clock pin (SCK) is always an input, the AT25M01 always operates as a slave. Transmitter/Receiver: The AT25M01 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains the opcode that defines the operations to be performed. Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25M01, and the Serial Output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. Chip Select: The AT25M01 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the Serial Output pin (SO) will remain in a high impedance state. Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25M01. When the device is selected and a serial sequence is underway, Hold can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low, and WPEN bit is one, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25M01 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to one.
8Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 Figure 5-1. SPI Serial Interface Master: Microcontroller Slave: AT25M01 Data Out (MOSI) Data In (MISO) Serial Clock (SPI CK) SS0 SS1 SS2 SS3 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS
9Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 6. Functional Description The AT25M01 is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 6800 type series of microcontrollers. The AT25M01 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 6-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 6-1. Instruction Set for Atmel AT25M01 Write Enable (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. Read Status Register (RDSR): The Read Status Register instruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6-2. Status Register Format Table 6-3. Read Status Register Bit Detection Instruction Name Instruction Format Operation WREN 0000 x110 Set Write Enable Latch WRDI 0000 x100 Reset Write Enable Latch RDSR 0000 x101 Read Status Register WRSR 0000 x001 Write Status Register READ 0000 x011 Read Data from Memory Array WRITE 0000 x010 Write Data to Memory Array Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is ready. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not write enabled. Bit 1 = 1 indicates the device is write enabled. Bit 2 (BP0) See Table 6-4 on page 10. Bit 3 (BP1) See Table 6-4 on page 10. Bits 4 6 are zeros when device is not in an internal write cycle. Bit 7 (WPEN) See Table 6-5 on page 10. Bits 0 7 are ones during an internal write cycle.
10Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25M01 is divided into four array segments. Top quarter (¼), top half (½), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read-only. The block write protection levels and corresponding status register control bits are shown in Table 6-4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, t WC, RDSR). Table 6-4. Block Write Protect Bits The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware Write Protection is enabled when the WP pin is low and the WPEN bit is one. Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is zero. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block protected (see Table 6-5). Note: When the WPEN bit is hardware write protected, it cannot be changed back to zero, as long as the WP pin is held low. Table 6-5. WPEN Operation Read Sequence (READ): Reading the AT25M01 via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read opcode is transmitted via the SI line followed by the a 3-byte address to be read (see Table 6-6 on page 11). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. Level Status Register Bits Array Addresses Protected BP1 BP0 AT25M01 0 0 0 None 1(¼) 0 1 18000h – 1FFFFh 2(½) 1 0 10000h – 1FFFFh 3(All) 1 1 00000h – 1FFFFh WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 x 0 Protected Protected Protected 0 x 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected X High 1 Protected Writable Writable
11Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 Write Sequence (Write): In order to program the AT25M01, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then, a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write opcode is transmitted via the SI line followed by the byte address and the data (D7 – D0) to be programmed (see Table 6-6). Programming will start after the CS pin is brought high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register instruction is enabled during the Write programming cycle. The AT25M01 is capable of a 256-byte Page Write operation. After each byte of data is received, the eight low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 256 bytes of data are transmitted, the address counter will roll-over and the previously written data will be overwritten. The AT25M01 is automatically returned to the write disable state at the completion of a Write cycle. Note: If the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6-6. Address Key Note: The A23 through A17 address bits of the most significant address byte are don’t care values as these bits fall outside the addressable 1-Mbit range. Address AT25M01 A(n) A23 A0
15Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 8. Part Marking DRAWING NO. REV. TITLE 25M01SM A 3/19/13 25M01SM, AT25M01 Standard Package Marking Information Package Mark Contact: DL-CSO-Assy_eng@atmel.com AAAAAAAA##% @ATMLHYWW 8-lead SOIC 8-ball WLCSP Note 2: Package drawings are not to scale Note 1: designates pin 1 Catalog Number Truncation AT25M01 Truncation Code ##: 5G Date Codes Voltages Y = Year WW = Work Week of Assembly % = Minimum Voltage 2: 2012 6: 2016 02: Week 2 M: 1.7V min 3: 2013 7: 2017 04: Week 4 5: 2015 9: 2019 52: Week 52 Country of Assembly Lot Number Grade/Lead Finish Material @ = Country of Assembly AAA...A = Atmel Wafer Lot Number U: Industrial/LeadFree Ball H: Industrial/NiPdAu Atmel Truncation ATML: Atmel AAAAAAAA##% @ ATMLUYWW AT25M01: Package Marking Information
16Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 9. Ordering Code Detail 10. AT25M01 Ordering Information Additional package types that are not listed below may be available for order. Please contact Atmel for availability details. Note: 1. Consistent with the general semiconductor market trend, Atmel will supply devices with either gold or copper bond wires to increase manufacturing flexibility and ensure a long-term continuity of supply. There is no difference in product quality, reliability, or performance between the two variations. 2. B = Bulk delivery in tubes: JEDEC SOIC = 100 units per tube EIAJ SOIC = 95 units per tube 3. T = Tape and reel delivery: JEDEC SOIC = 4k per reel EIAJ SOIC = 2k per reel WLCSP = 5k per reel 4. Contact Atmel for availability. Atmel Designator Product Family 25 = Standard SPI Serial EEPROM Device Density Shipping Carrier Option Package Device Grade or Wafer/Die Thickness Package Option M = Megabit Family 01 = 1 Megabit B = Bulk (tubes) T = Tape and reel Operating Voltage M = 1.7V to 5.5V H = Green, NiPdAu Lead Finish Industrial Temperature Range (-40ºC to 85ºC) U = Green, Matte Tin Lead Finish Industrial Temperature Range (-40ºC to 85ºC) 11 = 11mil Wafer Thickness AT25M01-SSHM-B SS = JEDEC SOIC S = EIAJ SOIC U = WLCSP WWU = Whole Wafer, Unsawn Atmel Ordering Code(1) Lead Finish Package Voltage Operation Range AT25M01-SSHM-B(2) NiPdAu (Lead-free/Halogen-free) 8S1 1.7V to 5.5V Industrial Temperature (40C to 85C) AT25M01-SSHM-T(3) AT25M01-SHM-B(2) 8S2 AT25M01-SHM-T(3) AT25M01-UUM-T(3)(4) SnAgCu (Lead-free/Halogen-free) 8U-7 AT25M01-WWU11M(4) — Wafer Sale Package Type 8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8S2 8-lead, 0.208" wide, Plastic Small Package Outline (EIAJ SOIC) 8U-7 8-ball, Wafer Level Chip Scale Package (WLCSP)
17Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 11. Packaging Information 11.1 8S1 — 8-lead JEDEC SOIC DRAWING NO. REV. TITLE GPC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ØØ 0° – 8° Ø E N TOP VIEW C END VIEW A b L e D SIDE VIEW Package Drawing Contact: packagedrawings@atmel.com 8S1 G 6/22/11 Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) SWB
18Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 11.2 8S2 — 8-lead EIAJ SOIC TITLE DRAWING NO. GPC REV. Package Drawing Contact: packagedrawings@atmel.com 8S2 STN F 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) 4/15/08 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 2 E 7.70 8.26 L 0.51 0.85 q 0° 8° e 1.27 BSC 3 qq 1 1 N N E E TOP VIEW TOP VIEW C C E1 E1 END VIEW END VIEW A A b b L L A1 A1 e e D D SIDE VIEW SIDE VIEW
19Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 11.3 8U-7 — 8-ball WLCSP DRAWING NO. REV. TITLE GPC 8U-7 B 03/19/13 8U-7, 8-ball (5x3 Array) Wafer Level Chip-Scale Package (WLCSP) GXG COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN TYP MAX NOTE A 0.540 A1 0.185 0.210 0.235 A2 0.305 0.330 0.355 E Contact Atmel for details e 0.867 e2 0.500 d 1.000 d2 0.500 D Contact Atmel for details b 0.220 0.250 0.280 Package Drawing Contact: packagedrawings@atmel.com TOP VIEW SIDE VIEW BALL SIDE PIN ASSIGNMENT MATRIX 1 2 3 4 5 A B C HOLD n/a WP V CC n/a SI D E e d Øb Pin 1 Pin 1 A 15 3 C B A C B A n/a SCK n/a n/a SO n/a CS n/a GND 15 324 Note: Dimensions are not to scale
20Atmel AT25M01 [DATASHEET] Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 12. Revision History Doc. Rev. Date Comments 8823B 03/2013 Add part marking. Update datasheet status from advance to complete. Update footers and Atmel fax number. 8823A 12/2012 Initial document release.
Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2013 Atmel Corporation. All rights reserved. / Rev.: Atmel-8824B-SEEPROM-AT25M01-Datasheet-032013 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITION S OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCT S INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness o f the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commi tment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.