AT25HP256 ATMEL

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 15

Technical content

Features

  • Serial Peripheral Interface (SPI) Compatible
  • Supports SPI Modes 0 (0,0) and 3 (1,1)
  • 10 MHz Clock Rate
  • 128-Byte Page Mode Only for Write Operations
  • Low-Voltage and Standard-Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V)
  • Block Write Protection – Protect 1/4, 1/2, or Entire Array
  • Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
  • High Reliability – Endurance: 100K Write Cycles – Data Retention: > 40 Years – ESD Protection: > 3000V
  • 8-Pin PDIP , 8-Pin EIAJ SOIC, and 8-Pin Leadless Array Package

Description

The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable pro- grammable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits each. The device is optimized for use in many industrial and commercial applications where high-speed, low-power, and low-voltage operation are essential. The AT25HP256/512 is available in a space saving 8-pin PDIP (AT25HP256/512), 8-pin EIAJ SOIC (AT25HP256), and 8-pin Leadless Array (AT25HP256/512) packages. In Rev. 1113B–07/98 SPI Serial EEPROMs 256K (32,768 x 8) 512K (65,536 x 8) AT25HP256 AT25HP512 Preliminary Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input (continued) 8-Pin SOIC CS SCK SO WP HOLD GND VCC1 5 SI 8-Pin PDIP CS SCK SO WP HOLD GND VCC1 5 SI 8-Pin Leadless Array Bottom View VCC HOLD SCK SI CS SO WP GND

addition, the entire family is available in 5.0V (4.5V to sions. The AT25HP256/512 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self- timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write pro- tection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to pro- tect against inadvertent write attempts to the status regis- ter. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram Absolute Maximum Ratings* Voltage on Any Pin 32,768/65,536 x 8

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL and VIH max are reference only and are not tested. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions Max Units Conditions C OUT Output Capacitance (SO) 8 pF V OUT = 0V C IN Input Capacitance (CS, SCK, SI, WP, HOLD)6 p F V IN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 3.6 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current V CC = 5.0V at 5 MHz, SO = Open Read 6.0 10.0 mA ICC2 Supply Current V CC = 5.0V at 5 MHz, SO = Open Write 4.0 7.0 mA ISB1 Standby Current V CC = 1.8V , CS = VCC 0.1 2.0 µA ISB2 Standby Current V CC = 2.7V , CS = VCC 0.2 2.0 µA ISB3 Standby Current V CC = 5.0V , CS = VCC 2.0 5.0 µA IIL Input Leakage V IN = 0V to VCC -3.0 3.0 µA IOL Output Leakage V IN = 0V to VCC , TAC = 0°C to 70°C- 3 . 0 3 . 0 µA VIL (1) Input Low Voltage -0.6 V CC x 0.3 V VIH (1) Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage 4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V VOH1 Output High Voltage I OH = -1.6 mA V CC - 0.8 V VOL2 Output Low Voltage 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V VOH2 Output High Voltage I OH = -100 µAV CC - 0.2 V

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, C L = 1 TTL Gate and 30 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD MHz tRI Input Rise Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD µs tFI Input Fall Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD µs tWH SCK High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ns tWL SCK Low Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ns tCS CS High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 TBD ns tCSS CS Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 TBD ns tCSH CS Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 TBD ns tSU Data In Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ns tH Data In Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ns tHD Hold Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ns tCD Hold Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ns tV Output Valid 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ns tHO Output Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 ns

Note: 1. This parameter is characterized and is not 100% tested. tLZ Hold to Output Low Z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 200 TBD ns t HZ Hold to Output High Z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 200 TBD ns t DIS Output Disable Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 TBD ns t WC Write Cycle Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 TBD ms Endurance (1) 5.0V , 25°C, Page Mode 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100K Write Cycles AC Characteristics (Continued) Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, C L = 1 TTL Gate and 30 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units

Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25HP256/512 always operates as a slave. TRANSMITTER/RECEIVER: The AT25HP256/512 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25HP256/512, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25HP256/512 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25HP256/512. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status regis- ter. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25HP256/512 in a system with the WP pin tied to ground and still be able to write to the status reg- ister. All WP pin functions are enabled when the WPEN bit is set to “1”. SPI Serial Interface AT25HP256/512

6800 type series of microcontrollers. The AT25HP256/512 utilizes an 8-bit instruction register. Register instruction provides access to the status register. ister control bits are shown in Table 4. block-protected sections in the memory array are disabled. Table 1. Instruction Set for the AT25HP256/512 Table 2. Status Register Format Table 3. Read Status Register Bit Definition Bits 4-6 are 0s when device is not in an internal write cycle. Bits 0-7 are 1s during an internal write cycle. Table 4. Block Write Protect Bits

followed by the byte address to be read (Refer to Table 6). Upon completion, any data on the SI line will be ignored. mands will be ignored except the RDSR instruction. one; the high order bits of the address will remain constant. edge is required to re-initiate the serial communication. bytes of data is received (byte write is not supported). Table 5. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

Table 6. Address Key

Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing WREN Timing WRDI Timing SO VOH VOL HI-Z HI-Z SI VIH VIL SKC VIH VIL CS VIH VIL VALID IN tCSS tSU tH tWH tWL tV tCS tCSH tDIStHO SCK CS SI SO CS SCK SI SO HI-Z WRDI OP-CODE

0123456789 1 0 1 1 1 2 1 3 1 4 SI INSTRUCTION SO 76543210 DAT A OUT MSB HIGH IMPED ANCE

WRITE Timing (AT25HP256) SCK SI SO CS 0123456789 1 0 1 1 2 0 2 1 2 2 2 3 2 4 2 5 2 6 INSTRUCTION HIGH IMPEDANCE BYTE ADDRESS 15 14 13 3 2 10 7 65 4 32 1 0 1ST BYTE DATA IN 27 28 29 30 31 ...

PAGE WRITE Timing (AT25HP512) HOLD Timing 1043 1044 1045 1046 1047 SCK SI SO CS 0123456789 1 0 1 1 2 0 2 1 2 2 2 3 2 4 2 5 2 6 INSTRUCTION HIGH IMPEDANCE BYTE ADDRESS 15 14 13 3 2 10 7 65 4 32 1 0 128th BYTE DATA IN 1st BYTE DATA IN SO SCK HO LD CS tCD tHD tHZ tHD tCD tLZ

tWC (max) (ms) ICC (max) (µµµµA) ISB (max) (µµµµA) fMAX (kHz) Ordering Code Package Operation Range 8000 7.0 10000 A T25HP256-10CC A T25HP256C1-10CC A T25HP256-10PC A T25HP256W-10SC 8C1 8P3 8S2 Commercial (0°C to 70°C) 8000 7.0 10000 A T25HP256-10CI A T25HP256C1-10CI A T25HP256-10PI A T25HP256W-10SI 8C1 8P3 8S2 Industrial (-40°C to 85°C) 4000 3.0 5000 A T25HP256-10CC-2.7 A T25HP256C1-10CC-2.7 A T25HP256-10PC-2.7 A T25HP256W-10SC-2.7 8C1 8P3 8S2 Commercial (0°C to 70°C) 4000 3.0 5000 A T25HP256-10CI-2.7 A T25HP256C1-10CI-2.7 A T25HP256-10PI-2.7 A T25HP256W-10SI-2.7 8C1 8P3 8S2 Industrial (-40°C to 85°C) TBD TBD TBD TBD A T25HP256-10CC-1.8 A T25HP256C1-10CC-1.8 A T25HP256-10PC-1.8 A T25HP256W-10SC-1.8 8C1 8P3 8S2 Commercial (0°C to 70°C) TBD TBD TBD A T25HP256-10CI-1.8 A T25HP256C1-10CI-1.8 A T25HP256-10PI-1.8 A T25HP256W-10SI-1.8 8C1 8P3 8S2 Industrial (-40°C to 85°C) Package Type 8C 8-Lead, 0.230" Wide, Leadless Array Package (LAP) 8C1 8-Lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S2 8-Lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 3.6V)

tWC (max) (ms) ICC (max) (µµµµA) ISB (max) (µµµµA) fMAX (kHz) Ordering Code Package Operation Range 8000 7.0 10000 A T25HP512C1-10CC A T25HP512-10PC 8C1 8P3 Commercial (0°C to 70°C) 8000 7.0 10000 A T25HP512C1-10CI A T25HP512-10PI 8C1 8P3 Industrial (-40°C to 85°C) 4000 3.0 5000 A T25HP512C1-10CC-2.7 A T25HP512-10PC-2.7 8C1 8P3 Commercial (0°C to 70°C) 4000 3.0 5000 A T25HP512C1-10CI-2.7 A T25HP512-10PI-2.7 8C1 8P3 Industrial (-40°C to 85°C) TBD TBD TBD TBD A T25HP512C1-10CC-1.8 A T25HP512-10PC-1.8 8C1 8P3 Commercial (0°C to 70°C) TBD TBD TBD A T25HP512C1-10CI-1.8 A T25HP512-10PI-1.8 8C1 8P3 Industrial (-40°C to 85°C) Package Type 8C1 8-Lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 3.6V)

5.15 (0.203) 4.85 (0.191) 6.15 (0.242) 5.85 (0.230) 0.42 (0.017) 0.34 (0.013) 1.30 (0.051) 1.00 (0.039) 1.27 (0.050) TYP 0.41 (0.016) TYP 0.64 (0.025) TYP TOP VIEW SIDE VIEW BOTTOM VIEW 5.15 (0.203) 4.85 (0.191) 8.15 (0.321) 7.85 (0.309) 0.42 (0.017) 0.34 (0.013) 1.30 (0.051) 1.00 (0.039) 1.27 (0.050) TYP 0.41 (0.016) TYP 0.64 (0.025) TYP TOP VIEW SIDE VIEW BOTTOM VIEW .400 (10.16) .355 (9.02) PIN .280 (7.11) .240 (6.10) .037 (.940) .210 (5.33) MAX SEATING PLANE .100 (2.54) BSC .015 (.380) MIN .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62)

15 REF

.430 (10.9) MAX .012 (.305) .008 (.203) .020 (.508) .012 (.305) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62)PIN 1 .050 (1.27) BSC .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 8 REF .010 (.254) .007 (.178) .035 (.889) .020 (.508) 8C, 8-Lead, 0.230" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) 8C1 , 8-Lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) 8P3, 8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC ST ANDARD MS-001 BA 8S2, 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters)