AT25F512_04 ATMEL

Document overview

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Technical content

Features

  • Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1)  20 MHz Clock Rate  Byte Mode and 256-byte Page Mode for Program Operations  Sector Architecture: – Two Sectors with 32K Bytes Each (512K) – Four Sectors with 32K Bytes Each (1M) – 128 Pages per Sector  Product Identification Mode  Low-voltage Operation – 2.7 (V CC = 2.7V to 3.6V)  Sector Write Protection  Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection  Self-timed Program Cycle (60 µs/Byte Typical)  Self-timed Sector Erase Cycle (1 second/Sector Typical)  Single Cycle Reprogramming (Erase and Program) for Status Register  High Reliability – Endurance: 10,000 Write Cycles Typical  Lead-free Devices Available  8-lead JEDEC SOIC and 8-lead SAP Packages

Description

The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash memory organized as 65,536/131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-volt- age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead JEDEC SOIC and 8-lead SAP packages. The AT25F512/1024 is enabled through the Chip Select pin (CS ) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Rev. 1440P–SEEPR–6/04 SPI Serial Memory 512K (65,536 x 8) 1M (131,072 x 8) AT25F512 AT25F1024 Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input 8-lead SOIC CS SO WP GND VCC HOLD SCK SI 8-lead SAP Bottom View VCC HOLD SCK SI CS SO WP GND

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1440P–SEEPR–6/04 Block Diagram Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin 65,536 x 8 or 131,072 x 8

1440P–SEEPR–6/04 Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL and VIH max are reference only and are not tested. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +3.6V (unless otherwise noted). Symbol Test Conditions Max Units Conditions COUT Output Capacitance (SO) 8 pF V OUT = 0V CIN Input Capacitance (CS, SCK, SI, WP, HOLD)6 p F V IN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +3.6V, TAC = 0°C to +70°C, VCC = +2.7V to +3.6V (unless otherwise noted). Symbol Parameter Test Co ndition Min Typ Max Units VCC Supply Voltage 2.7 3.6 V ICC1 Supply Current V CC = 3.6V at 20 MHz, SO = Open Read 10.0 15.0 mA ICC2 Supply Current V CC = 3.6V at 20 MHz, SO = Open Write 15.0 30.0 mA ISB Standby Current V CC = 2.7V, CS = VCC 2.0 10.0 µA IIL Input Leakage V IN = 0V to VCC -3.0 3.0 µA IOL Output Leakage V IN = 0V to VCC, TAC = 0°C to 70°C -3.0 3.0 µA VIL (1) Input Low Voltage -0.6 V CC x 0.3 V VIH (1) Input High Voltage V CC x 0.7 V CC + 0.5 V VOL Output Low Voltage 2.7V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V VOH Output High Voltage I OH = -100 µA V CC - 0.2 V

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1440P–SEEPR–6/04 Notes: 1. The programming time for n bytes will be equal to n x t BPC. 2. This parameter is characterized at 3.0V, 25 °C and is not 100% tested. 3. One write cycle consists of erasing a sector , followed by programming the same sector. AC Characteristics Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +2.7V to +3.6V CL = 1 TTL Gate and 30 pF (unless otherwise noted). Symbol Parameter Min Typ Max Units fSCK SCK Clock Frequency 0 20 MHz tRI Input Rise Time 20 ns tFI Input Fall Time 20 ns tWH SCK High Time 20 ns tWL SCK Low Time 20 ns tCS CS High Time 25 ns tCSS CS Setup Time 25 ns tCSH CS Hold Time 25 ns tSU Data In Setup Time 5 ns tH Data In Hold Time 5 ns tHD Hold Setup Time 15 ns tCD Hold Time 15 ns tV Output Valid 20 ns tHO Output Hold Time 0 ns tLZ Hold to Output Low Z 200 ns tHZ Hold to Output High Z 200 ns tDIS Output Disable Time 100 ns tEC Erase Cycle Time per Sector 1.1 s tBPC Byte Program Cycle Time(1) 60 100 µs tSR Status Register Write Cycle Time 60 ms Endurance(2) 10K Write Cycles (3)

1440P–SEEPR–6/04 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25F512/1024 always operates as a slave. TRANSMITTER/RECEIVER: The AT25F512/1024 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received , no data will be shifted into the AT25F512/1024, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25F512/1024 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F512/1024. When the device is sele cted and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The 25F512/1024 has a write lockout feature that can be activated by asserting the write protect pin (WP). When the lockout feature is activated, locked-out sectors will be READ only. The write protect pin will allow normal read/write operations when held high. When the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal status register write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25F512/1024 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

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1440P–SEEPR–6/04 SPI Serial Interface MASTER: MICROCONTROLLER SLAVE: AT25F512/1024 DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS

1440P–SEEPR–6/04 Functional The AT25F512/1024 is designed to interface directly with the synchronous serial periph- eral interface (SPI) of the 6800 type series of microcontrollers. The AT25F512/1024 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification. The following commands, PROGRAM, SECTOR ERASE, CHIP ERASE, and WRSR are write instructions for AT25F512/1024. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the sta- tus of the WP pin. READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta- tus register. The READY/BUSY and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction. Table 1. Instruction Set for the AT25F512/1024 Table 2. Status Register Format

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manufacturer code (1FH = ATMEL), followed by the device code. register control bits are shown in Table 4. Table 3. Read Status Register Bit Definition the device is WRITE ENABLED. Bits 4-6 are 0s when device is not in an internal write cycle. Bits 0-7 are 1s during an internal write cycle. Table 4. Block Write Protect Bits

write the status register, the device must first be write enabled via the WREN instruction. automatically return to write disable state at the completion of the WRSR cycle. long as the WP pin is held low. nated when the highest address (00FFFF) is reached. programming cycle, all commands will be ignored except the RDSR instruction. Table 5. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

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ended. Only the RDSR instruction is enabled during the program cycle. pletion of the PROGRAM cycle. required to re-initiate the serial communication. ERASE may incur busy cycles. WREN instruction. Then the SECTOR ERASE instruction can be executed. able state at the completion of the SECTOR ERASE cycle. Table 6. Address Key Table 7. Sector Addresses

1440P–SEEPR–6/04 Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing WREN Timing WRDI Timing SO VOH VOL HI-Z HI-Z tV VALID INSI VIH VIL tHtSU tDIS SCK VIH VIL tWH tCSH CS VIH VIL tCSS tCS tWL tHO

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1440P–SEEPR–6/04 RDSR Timing WRSR Timing READ Timing CS SCK 0123456789 1 0 1 1 1 2 1 3 1 4 SI INSTRUCTION SO 76543210 DATA OUT MSB HIGH IMPEDANCE CS SI SCK HIGH IMPEDANCE INSTRUCTION 3-BYTE ADDRESS 01234 8 9 10 11 28 23 22 21 3 ... 21 321 29 30 31 32 33 34 35 36 37 38 SO

1440P–SEEPR–6/04 PROGRAM Timing HOLD Timing SECTOR ERASE Timing CS SCK SI SO 3-BYTE ADDRESS 1st BYTE DATA-IN 256th BYTE DATA-IN INSTRUCTION HIGH IMPEDANCE 0123456789 1 0 1 1 2 8 23 22 21 3 1 0 6 5 4 3 2 1 0 72 29 30 31 32 33 34 2075 2076 2078 2077 2079 SO SCK HOLD tCD tHD tHZ tLZ tCD tHD CS X X = Don’t Care bit

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1440P–SEEPR–6/04 CHIP ERASE Timing RDID Timing X X = Don’t Care bit 12 13 14 15 16 17 2318 19 X MANUFACTURER CODE (ATMEL) DEVICE CODE

1440P–SEEPR–6/04

Ordering Information

Ordering Code Package Operation Range AT25F512N-10SI-2.7 8S1 Industrial (-40°C to 85°C) AT25F1024N-10SI-2.7 8S1 Industrial (-40°C to 85°C) AT25F512N-10SU-2.7 AT25F512Y4-10YU-2.7 8S1 8Y4 Lead-free/Halogen Free/Industrial Temperatures (-40°C to 85°C) AT25F1024N-10SU-2.7 AT25F1024Y4-10YU-2.7 8S1 8Y4 Lead-free/Halogen Free/Industrial Temperatures (-40°C to 85°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) Options -2.7 Low-voltage (2.7V to 3.6V)

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1440P–SEEPR–6/04 Package Drawing 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

1440P–SEEPR–6/04 8Y4 – SAP 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80817 TITLE DRAWING NO. R REV. 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package (SAP) Y4 A8Y4 5/24/04 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 0.90 A1 0.00 – 0.05 D 5. 80 6.00 6.20 E 4.70 4.90 5.10 D1 2. 85 3.00 3.15 E1 2. 85 3.00 3.15 b 0. 35 0.40 0.45 e 1.27 TYP e1 3.81 REF L 0.50 0.60 0.70 A E A1 b PIN 1 INDEX AREA D A PIN 1 ID L e

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