Download PDFAT25F512A_06 ATMEL
Document overview
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- PDF pages: 19
Technical content
Features
- Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet Describes 0 Operation
- 33 MHz Clock Rate
- Byte Mode and 128-byte Page Mode for Program Operations
- Sector Architecture: – Two Sectors with 32K Bytes Each – 256 Pages per Sector
- Product Identification Mode
- Low-voltage Operation
- Sector Write Protection
- Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection
- Self-timed Program Cycle (75 µs/byte typical)
- Self-timed Sector Erase Cycle (1 second/sector typical)
- Single Cycle Reprogramming (Erase and Program) for Status Register
- High Reliability – Endurance: 10,000 Write Cycles Typical – Data Retention: 20 Years
- 8-lead JEDEC SOIC and 8-lead SAP Packages
Description
The AT25F512A provides 524,288 bits of serial reprogrammable Flash memory orga- nized as 65,536 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F512A is available in a space-saving 8-lead JEDEC SOIC and 8-lead SAP packages. The AT25F512A is enabled through the Chip Select pin (CS ) and accessed via a three-wire interface consisting of Serial Da ta Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. Block write protection for the entire memory array is enabled by programming the sta- tus register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data prot ection is provided via the Write Protect (WP) pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configuration
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Figure 1. Block Diagram
Note: 1. This parameter is characterized and is not 100% tested.
- V IL and VIH max are reference only and are not tested.
Table 2. Pin Capacitance(1) Table 3. DC Characteristics(1)
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Notes: 1. The programming time for n bytes will be equal to n x t BPC.
- This parameter is ensured by characterization at 3.0V, 25 °C only.
- One write cycle consists of erasing a sector, followed by programming the same sector.
Table 4. AC Characteristics (Preliminary - Subject to Change)
3345F–FLASH–11/06 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the SCK pin is always an input, the AT25F512A always operates as a slave. TRANSMITTER/RECEIVER: The AT25F512A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25F512A, and the serial output pin (SO) wi ll remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25F512A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F512A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial comm unication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The AT25F512A has a write lockout feature that can be activated by asserting the WP pin. When the lockout feature is ac tivated, locked-out sectors will be read only. The write protect pin will allow normal read/write operations when held high. When the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal status register write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow th e user to install the AT25F512A in a system with the WP pin tied to ground and still be able to write to the sta- tus register. All WP pin functions are enabled when the WPEN bit is set to “1”.
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Figure 2. SPI Serial Interface
3345F–FLASH–11/06 Functional The AT25F512A is designed to interface dire ctly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25F512A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification. The commands Program, Sector Erase, Chip Erase, and WRSR are write instructions for AT25F512A. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the sta- tus of the WP pin. READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta- tus register. The Ready/Busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction. Table 5. Instruction Set for the AT25F512A Table 6. Status Register Format
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manufacturer code (1FH = ATMEL), followed by the device code, 65H. sponding status register control bits are shown in Table 8. return to write disable state at the completion of the WRSR cycle. long as the WP pin is held low. Table 7. Read Status Register Bit Definition the device is write enabled. Bits 3–6 are “0”s when device is not in an internal write cycle. Bits 0–7 are “1”s during an internal write cycle. Table 8. Block Write Protect Bits
cycle, all commands will be ignored except the RDSR instruction. has ended. Only the RDSR instruction is enabled during the program cycle. required to re-initiate the serial communication. Table 9. WPEN Operation
0 X 0 Protected Protected Protected
0 X 1 Protected Writeable Writeable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writeable Protected
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instruction. Then the SECTOR ERASE instruction can be executed. tion of the sector erase cycle. automatically return to the WRDI state at the completion of the chip erase cycle. Table 10. Address Key Table 11. Sector Addresses
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Figure 6. RDSR Timing Figure 7. WRSR Timing Figure 8. READ Timing
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Figure 12. CHIP ERASE Timing Figure 13. RDID Timing
3345F–FLASH–11/06
Ordering Information
Ordering Code Package Operation Range AT25F512AN-10SH-2.7 AT25F512AY4-10YH-2.7 8S1 8Y4 Lead-free/Halogen-free/NiPdAu Lead Finish Industrial Temperature (−40 to 85°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) Options −2.7 Low-voltage (2.7 to 3.6V)
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3345F–FLASH–11/06 Packaging Information 8S1 – SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L
3345F–FLASH–11/06 8Y4 – SAP 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package (SAP) Y4 A8Y4 5/24/04 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 0.90 A1 0.00 – 0.05 D 5.80 6.00 6.20 E 4.70 4.90 5.10 D1 2.85 3.00 3.15 E1 2.85 3.00 3.15 b 0.35 0.40 0.45 e 1.27 TYP e1 3.81 REF L 0.50 0.60 0.70 PIN 1 ID L b e PIN 1 INDEX AREA A E D A
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3345F–FLASH–11/06
Revision History
Document No. Comments 3345F Removed preliminary status”
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