AT25F4096

AT25F4096_06 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 19

Technical content

Features

• Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet describes Mode 0 Operation  33 MHz Clock Rate  Byte Mode and 256-byte Page Mode for Program Operations  Sector Architecture: – Eight Sectors with 64K Bytes Each (4M) – 256 Pages per Sector  Product Identification Mode  Low-voltage Operation – 2.7 (V CC = 2.7V to 3.6V)  Sector Write Protection – Protect 1/8, 1/4, 1/2 or Entire Array  Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection  Self-timed Program Cycle (30 µs/Byte Typical)  Self-timed Sector Erase Cycle (1 second/Sector Typical)  Single Cycle Reprogramming (Erase and Program) for Status Register  High Reliability – Endurance: 10,000 Write Cycles Typical – Data Retention: 20 Years  8-lead EIAJ SOIC and 8-lead Small Array Package (SAP)

Description

The AT25F4096 provides 4,194,304 bits of serial reprogrammable Flash memory organized as 524,288 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F4096 is available in a space-saving 8-lead EIAJ SOIC and 8- lead SAP packages. Table 1. Pin Configurations

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(SCK). All write cycles are completely self-timed. Figure 1. Block Diagram

Table 2. Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL and VIH max are reference only and are not tested. Table 3. DC Characteristics (Preliminary – Subject to Change)

Table 4. AC Characteristics (Preliminary – Subject to Change)

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Notes: 1. The programming time for n bytes will be equal to n x t BPC.

1. This parameter is ensured by characterization at 3.0V, 25 °C only.
2. One write cycle consists of erasing a sector , followed by programming the same sector.

2454G–SFLSH–5/06 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25F4096 always operates as a slave. TRANSMITTER/RECEIVER: The AT25F4096 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received , no data will be shifted into the AT25F4096, and the serial output pin (SO) wi ll remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25F4096 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F4096. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial comm unication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The 25F4096 has a write lockout feature that can be activated by asserting the write protect pin (WP ). When the lockout feature is activated, locked-out sectors will be READ only. The write protect pin will allow normal read/write operations when held high. When the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal status re gister write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25F4096 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

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Figure 2. SPI Serial Interface

2454G–SFLSH–5/06 Functional The AT25F4096 is designed to interface direct ly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25F4096 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification. The following commands, Program, Sector Erase, Chip Erase, and WRSR are write instructions for AT25F4096. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the sta- tus of the WP pin. READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta- tus register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction. Table 5. Instruction Set for the AT25F4096 Table 6. Status Register Format

Table 7. Read Status Register Bit Definition indicates the device is WRITE ENABLED. Bits 5-6 are 0s when device is not in an internal write cycle. Bits 0-7 are 1s during an internal write cycle.

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manufacturer code (1FH = ATMEL), followed by the device code 64H. Table 8. Block Write Protect Bits

automatically return to write disable state at the completion of the WRSR cycle. long as the WP pin is held low. is transmitted via the SI line followed by the byte address to be read (Refer to Table 10). programming cycle, all commands will be ignored except the RDSR instruction. occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. has ended. Only the RDSR instruction is enabled during the program cycle. of the page is reached, the address will wrap around to the beginning of the same page. Table 9. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

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required to re-initiate the serial communication. instruction. Then the Sector Erase instruction can be executed. completion of the Sector Erase cycle. automatically return to the write disable state at the completion of the Chip Erase cycle. Table 10. Address Key Table 11. Sector Addresses

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Figure 6. RDSR Timing Figure 7. WRSR Timing Figure 8. READ Timing

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Figure 12. CHIP ERASE Timing Figure 13. RDID Timing

Ordering Information

Ordering Code Package Operation Range AT25F4096W-10SU-2.7 AT25F4096Y4-10YH-2.7(1) 8S2 8Y4 Lead-Free/Halogen-Free/ Industrial Temperature (–40°C to 85°C) AT25F4096 2454G–SFLSH–5/06 Note: 1. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. Package Type 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) Options –2.7 Low Voltage (2.7V to 3.6V)

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2454G–SFLSH–5/06

Package Information

8S2 – EIAJ SOIC

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) 10/7/03 8S2 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. Thi s drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mi smatch of the upper and lower dies and resin burrs are not included. 3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determine s the true geometric position. A 1.70 2.16 A1 0.05 0.25 b 0. 35 0.4 8 5 C 0.15 0. 35 5 D 5.1 3 5. 35 E1 5.1 8 5.40 2, 3 E 7.70 8.26 L 0.51 0. 85 ∅ 0° 8° e 1.27 B SC 4 End View Side View e b A D E N C L Top View

2454G–SFLSH–5/06 8Y4-SAP 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package (SAP) Y4 A8Y4 5/24/04 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 0.90 A1 0.00 – 0.05 D 5.80 6.00 6.20 E 4.70 4.90 5.10 D1 2.85 3.00 3.15 E1 2.85 3.00 3.15 b 0.35 0.40 0.45 e 1.27 TYP e1 3.81 REF L 0.50 0.60 0.70 PIN 1 ID L b e PIN 1 INDEX AREA A E D A

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2454G–SFLSH–5/06

Revision History

Doc. Rev. Comments 2454G Changed ordering part number from AT25F4096Y4-10YU-2.7 to AT25F4096Y4-10YH-2.7 Added Note 1: “H” designates Green Package + RoHS Compliant, with NiPdAu Lead Finish to ordering information Removed ‘Preliminary’ from all pages

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