AT25F2048-W27-11

AT25F2048_07 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 19

Technical content

Features

• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• 33 MHz Clock Rate
• Byte Mode and 256-byte Page Mode for Program Operations
• Sector Architecture: – Four Sectors with 64K Bytes Each – 256 Pages per Sector
• Product Identification Mode
• Low-voltage Operation – 2.7 (V CC = 2.7V to 3.6V)
• Sector Write Protection – Protect 1/4, 1/2 or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection
• Self-timed Program Cycle (30 µs/Byte Typical)
• Self-timed Sector Erase Cycle (1 second/Sector Typical)
• Single Cycle Reprogramming (Erase and Program) for Status Register
• High Reliability – Endurance: 10,000 Write Cycles Typical – Data Retention: 20 Years
• 8-lead JEDEC SOIC and 8-lead Ultra Thin Small Array (SAP) Packages
• Die Sales: Wafer Form, Tape and Reel and Bumped Wafers

Description

The AT25F2048 provides 2,097,152 bits of serial reprogrammable Flash memory organized as 262,144 words of 8 bits eac h. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F2048 is available in a space-saving 8-lead JEDEC SOIC and Ultra Thin SAP package. Rev. 2455I–SFLSH–5/07 2Mbit High Speed SPI Serial Flash Memory 2M (262,144 x 8) AT25F2048 Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input CS SO WP GND VCC HOLD SCK SI CS SO WP GND VCC HOLD SCK SI 8-lead Ultra Thin SAP Bottom View 8-lead SOIC

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(SCK). All write cycles are completely self-timed. Figure 1. Block Diagram

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL and VIH max are reference only and are not tested. Table 1. Pin Capacitance(1) Table 2. DC Characteristics (Preliminary – Subject to Change)

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Notes: 1. The programming time for n bytes will be equal to n x t BPC.

1. This parameter is ensured by characterization at 3.0V, 25 °C only.
2. One write cycle consists of erasing a sector, followed by programming the same sector.

Table 3. AC Characteristics (Preliminary – Subject to Change)

2455I–SFLSH–5/07 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25F2048 always operates as a slave. TRANSMITTER/RECEIVER: The AT25F2048 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25F2048, and the serial output pin (SO) wi ll remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25F2048 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F2048. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial comm unication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The 25F2048 has a write lockout feature that can be activated by asserting the write protect pin (WP ). When the lockout feature is activated, locked-out sectors will be read only. The write protect pin will allow normal read/write operations when held high. When the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the in ternal status register write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25F2048 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

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Figure 2. SPI Serial Interface

2455I–SFLSH–5/07 Functional The AT25F2048 is designed to interface direct ly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25F2048 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 4. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification. The following commands, Program, Sector Erase, Chip Erase, and WRSR are write instructions for AT25F2048. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the sta- tus of the WP pin. READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta- tus register. The Ready/Busy and write enable status of the device can be determined by the RDSR instruction. Simila rly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction. Table 4. Instruction Set for the AT25F2048 Table 5. Status Register Format

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manufacturer code (1FH = ATMEL), followed by the device code, 63H. ties and functions as the regular memory cells (e.g., WREN, tWC, RDSR). Table 6. Read Status Register Bit Definition the device is WRITE ENABLED. Bits 4-6 are 0s when device is not in an internal write cycle. Bits 0-7 are 1s during an internal write cycle. Table 7. Block Write Protect Bits

write the status register, the device must first be write enabled via the WREN instruction. automatically return to write disable state at the completion of the WRSR cycle. long as the WP pin is held low. is transmitted via the SI line followed by the byte address to be read (Refer to Table 9). programming cycle, all commands will be ignored except the RDSR instruction. ended. Only the RDSR instruction is enabled during the program cycle. Table 8. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

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of the page is reached, the address will wrap around to the beginning of the same page. required to re-initiate the serial communication. instruction. Then the Sector Erase instruction can be executed. completion of the Sector Erase cycle. automatically return to the write disable state at the completion of the Chip Erase cycle. Table 9. Address Key Table 10. Sector Addresses

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Figure 6. RDSR Timing Figure 7. WRSR Timing Figure 8. READ Timing

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Figure 12. CHIP ERASE Timing Figure 13. RDID Timing

2455I–SFLSH–5/07 Note: 1. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing.

Ordering Information

Ordering Code Voltage Package Operation Range AT25F2048N-10SU-2.7 AT25F2048Y7-YH27-T (NiPdAu Lead Finish) 2.7 8S1 8Y7 Lead-free/Halogen-free/ Industrial Temperature (-40°C to 85°C) 2.7 AT25F2048-W27-11(1) 2.7 Die Sale Industrial Temperature (-40°C to 85°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) Options -2.7 Low Voltage (2.7V to 3.6V)

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2455I–SFLSH–5/07

Package Information

8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

2455I–SFLSH–5/07 8Y7 - SAP 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array Package (UTSAP) Y7 B8Y7 10/13/05 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 0.60 A1 0.00 – 0.05 D 5.80 6.00 6.20 E 4.70 4.90 5.10 D1 3.30 3.40 3.50 E1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 TYP e1 3.81 REF L 0.50 0.60 0.70 PIN 1 ID L b e PIN 1 INDEX AREA A E D A

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2455I–SFLSH–5/07

Revision History

Rev. No. Date Comments 2455I 5/2007 Added Die Sale product offering 2455H 4/2007 Changed Operation Range description Added ‘NiPdAu Lead Finish’ to AT25F2048Y7-YH27-T part number 2455G 3/2007 Implemented revision history Added SAP package Removed Preliminary

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