AT25512

AT25512_08 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 21

Technical content

Features

• Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1)  Data Sheet Describes Mode 0 Operation  Low-voltage Operation – 1.8 (V CC = 1.8V to 5.5V)  20 MHz Clock Rate (4.5 – 5.5V)  128-byte Page Mode and Byte Write Operation Supported  Block Write Protection – Protect 1/4, 1/2, or Entire Array  Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection  Self-timed Write Cycle (5 ms Max)  High-reliability – Endurance: 1 Million Write Cycles – Data Retention: >40 Years  Lead-free/Halogen-free Devices  8-lead JEDEC SOIC, 8-lead TSSOP and 8-lead SAP Packages  Die Sales: Wafer Form, Waffle Pack, and Bumped Die

Description

The AT25512 provides 524,288 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device is opti- mized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The dev ices are available in space saving 8-lead JEDEC SOIC, 8-lead TSSOP and 8-lead SAP packages. In addition, the entire family is available in 1.8V (1.8V to 5.5V) versions. The AT25512 is enabled through the Chip Select pin (CS ) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles ar e completely self-timed, and no separate Erase cycle is required before Write. Table 0-1. Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect 5165E–SEEPR–8/08 SPI Serial EEPROM 512K (65,536 x 8) AT25512

5165E–SEEPR–8/08 AT25512 Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate Program Enable and Program Disable instructions are pro- vided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attemp ts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Figure 1-1. Block Diagram 1. Absolute Maximum Ratings* mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin 65536x 8

5165E–SEEPR–8/08 AT25512 Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 1-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25° C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions Max Units Conditions COUT Output Capacitance (SO) 8 pF V OUT = 0V CIN Input Capacitance (CS, SCK, SI, WP, HOLD)6 p F V IN = 0V Table 1-2. DC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V(unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V at 20 MHz, SO = Open, Read 9.0 10.0 mA ICC2 Supply Current VCC = 5.0V at 10 MHz, SO = Open, Read, Write 5.0 7.0 mA ICC3 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read, Write 2.2 3.5 mA ISB1 Standby Current V CC = 1.8V, CS = VCC 0.2 3.0 µA ISB2 Standby Current V CC = 2.7V, CS = VCC 0.5 3.0 µA ISB3 Standby Current V CC = 5.0V, CS = VCC 2.0 5.0 µA IIL Input Leakage V IN = 0V to VCC –3.0 3.0 µA IOL Output Leakage V IN = 0V to VCC, TAC = 0⋅ C to 70⋅ C –3.0 3.0 µA VIL (1) Input Low-voltage –1.0 V CC x 0.3 V VIH (1) Input High-voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low-voltage 3.6 ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V VOH1 Output High-voltage I OH = −1.6 mA V CC –0.8 V VOL2 Output Low-voltage 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V VOH2 Output High-voltage I OH = −100 µA V CC –0.2 V

5165E–SEEPR–8/08 AT25512 Table 1-3. AC Characteristics Applicable over recommended operating range from TAI = –40⋅ C to + 85⋅ C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5–5.5 2.7–5.5 1.8–5.5 MHz tRI Input Rise Time 4.5–5.5 2.7–5.5 1.8–5.5 µs tFI Input Fall Time 4.5–5.5 2.7–5.5 1.8–5.5 µs tWH SCK High Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tWL SCK Low Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tCS CS High Time 4.5–5.5 2.7–5.5 1.8–5.5 100 100 200 ns tCSS CS Setup Time 4.5–5.5 2.7–5.5 1.8–5.5 100 100 200 ns tCSH CS Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 100 100 200 ns tSU Data In Setup Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tH Data In Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tHD Hold Setup Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tCD Hold Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tV Output Valid 4.5–5.5 2.7–5.5 1.8–5.5 ns tHO Output Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 ns t LZ Hold to Output Low Z 4.5–5.5 2.7–5.5 1.8–5.5 100 ns

5165E–SEEPR–8/08 AT25512 Notes: 1. This parameter is characterized and is no t 100% tested. Contact Atmel for further information. 2. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25512 always operates as a slave. TRANSMITTER/RECEIVER: The AT25512 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25512, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25512 is selected when the CS pin is low. When the device is not selected, data will not be accepted vi a the SI pin, and the serial ou tput pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25512. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg- ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT 25512 in a system with the WP pin tied to tHZ Hold to Output High Z 4.5–5.5 2.7–5.5 1.8–5.5 100 ns tDIS Output Disable Time 4.5–5.5 2.7–5.5 1.8–5.5 100 ns tWC Write Cycle Time 4.5–5.5 2.7–5.5 1.8–5.5 ms Endurance(1) 5.0V, 25⋅ C, Page Mode 1M Write Cycles Table 1-3. AC Characteristics (Continued) Applicable over recommended operating range from TAI = –40⋅ C to + 85⋅ C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units

5165E–SEEPR–8/08 AT25512 ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. Figure 2-1. SPI Serial Interface 3. Functional Description The AT25512 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25512 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in see Table 4-3. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. AT25512

5165E–SEEPR–8/08 AT25512 WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. Th e WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register in struction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25512 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read onl y. The block write protection levels and corresponding status register control bits are shown in Table 3-4. Table 3-1. Instruction Set for the AT25512 Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array Table 3-2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 3-3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not write enabled. Bit 1 = “1” indicates the device is write enabled. Bit 2 (BP0) See Table 3-4 on page 8. Bit 3 (BP1) See Table 3-4 on page 8. Bits 4 − 6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 3-5 on page 8. Bits 0 − 7 are “1”s during an internal write cycle.

5165E–SEEPR–8/08 AT25512 The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). The WRSR instruction also allows the user to enable or disable the write protect (WP ) pin through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Ha rdware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the Status Register, including the Bloc k Protect bits and the WPEN bit, and the block- protected sections in the memory array are disabl ed. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. READ SEQUENCE (READ): Reading the AT25512 via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte address to be read (see Table 3-6 on page 9). Upon completion, any data on the SI line will be ignored. The da ta (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be cont inued since the byte address is automati- cally incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25512, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruc- tion. Then a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Table 3-4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP1 BP0 AT25512 00 0 N o n e 1(1/4) 0 1 C000 – FFFF 2(1/2) 1 0 8000 – FFFF 3(All) 1 1 0000 – FFFF Table 3-5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected X High 1 Protected Writable Writable

5165E–SEEPR–8/08 AT25512 Protection Level. During an in ternal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write op-code is transmitted via the SI line followed by the byte address and the data (D7 – D0) to be programmed (see Table 3-6). Programming will start after the CS pin is brought high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be dete rmined by initiating a Read Status Register (RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register instruction is enabled during the Write programming cycle. The AT25512 is capable of a 128-byte Page Write operation. After each byte of data is received, the seven low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 128 byte s of data are transmitted, the address coun- ter will roll over and the previously written data will be overwritten. The AT25512 is automatically returned to the write disable state at the completion of a Write cycle. NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 3-6. Address Key Address AT25512 AN A15 − A0

5165E–SEEPR–8/08 AT25512 5. Part Marking Scheme TOP MARK Pin 1 Indicator (Dot) * H Y W W

5 F 1

<- Pin 1 Indicator Y = SEAL YEAR WW = SEAL WEEK 6: 2006 0: 2010 02 = Week 2 7: 2007 1: 2011 04 = Week 4 50 = Week 50 52 = Week 52

5165E–SEEPR–8/08 AT25512 AT25512N-SH-B/T Seal Year TOP MARK | Seal Week | | | A T M L H Y W W

• Lot Number Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK 6: 2006 0: 2010 02 = Week 2 7: 2007 1: 2011 04 = Week 4 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark

5165E–SEEPR–8/08 AT25512 AT25512Y7-YH-T Seal Year TOP MARK | Seal Week | | | A T M L H Y W W

• Lot Number Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK 6: 2006 0: 2010 02 = Week 2 7: 2007 1: 2011 04 = Week 4 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark

5165E–SEEPR–8/08 AT25512 6. AT25512 Ordering Information Notes: 1. “-B” denotes bulk. 3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Ordering Code Voltage Package Operation Range AT25512N-SH-B(1) AT25512N-SH-T(2) AT25512-TH-B(1) AT25512-TH-T(2) AT25512Y7-YH-T(2) 1.8 1.8 1.8 1.8 1.8 8S1 8S1 8A2 8A2 8Y7 Lead-free/Halogen-free NiPDAu Lead Finish Industrial Temperature (–40° C to 85° C) AT25512-W-11 (3) 1.8 Die Sale Industrial Temperature (–40° C to 85° C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y7 8-lead, 6.00mm x 4.90mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) Options –1.8 Low-voltage (1.8V to 5.5V)

5165E–SEEPR–8/08 AT25512 7. Packaging Information 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 3/17/05 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A1 . 35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D4 . 80 – 5.05 E1 3.81– 3.99 E 5.79 – 6.20 e 1.27 B SC L 0.40 – 1.27 θ 0˚ – 8˚ ØØ EE NN CC E1E1 END VIEW AA bb LL A1A1 ee DD TOP VIEW SIDE VIEW

5165E–SEEPR–8/08 AT25512 8A2 – TSSOP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

5165E–SEEPR–8/08 AT25512 8Y7 - SAP 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array Package (UTSAP) Y7 B8Y7 10/13/05 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 0.60 A1 0.00 – 0.05 D 5.80 6.00 6.20 E 4.70 4.90 5.10 D1 3.30 3.40 3.50 E1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 TYP e1 3.81 REF L 0.50 0.60 0.70 PIN 1 ID L b e PIN 1 INDEX AREA A E D A

5165E–SEEPR–8/08 AT25512 8. Revision History Doc. Rev. Date Comments 5165E 8/2008 Updated for 1.8V - 5.5V operation 5165D 5/2008 Added part marking diagram information 5165C 8/2007 Changed address bit number to seven on page 9 Removed Preliminary status 5165B 6/2007 Changed spacing on table notes Reworked figure 4-8 Updated to new template Changed status to Preliminary 5165A 1/2007 Initial document release.

5165E–SEEPR–8/08 Headquarters International Atmel Corporation San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza

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