AT25320N

AT25320N ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 21

Technical content

Features

• Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1)  Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)  3.0 MHz Clock Rate (5V)  32-byte Page Mode  Block Write Protection – Protect 1/4, 1/2, or Entire Array  Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection  Self-timed Write Cycle (5 ms Typical)  High-reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years  Automotive Grade Devices Available  8-lead PDIP , 8-lead JEDEC SOIC and 14-lead TSSOP Packages

Description

The A T25080/160/320/640 provides 8192/16384/32768/65536 bits of serial electri- cally-erasable programmable read only memory (EEPROM) organized as 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25080/160/320/640 is available in space saving 8-lead PDIP , 8- lead JEDEC SOIC and 14-lead TSSOP packages. The AT25080/160/320/640 is enabled through the Chip Select pin (CS ) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate ERASE cycle is required before WRITE. SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8) 32K (4096 x 8) 64K (8192 x 8) AT25080 AT25160 AT25320 AT25640 0675M–SEEPR–9/03 Pin Configuration Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect DC Don’t Connect 8-lead PDIP CS SO WP GND VCC HOLD SCK SI 8-lead SOIC CS SO WP GND VCC HOLD SCK SI 14-lead TSSOP CS SO NC NC NC WP GND VCC HOLD NC NC NC SCK SI

2 AT25080/160/320/640

0675M–SEEPR–9/03 BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Sepa- rate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Block Diagram Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin

0675M–SEEPR–9/03 Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics(1) Note: 1. V IL min and VIH max are reference only and are not tested. Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Symbol Test Conditions Max Units Conditions COUT Output Capacitance (SO) 8 pF V OUT = 0V CIN Input Capacitance(CS, SCK, SI, WP, HOLD)6 p F V IN = 0V Applicable over recommended operating range from: T AI = -40°C to +85 °C, VCC = +1.8V to +5.5V, V CC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 3.6 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current V CC = 5.0V at 1 MHz, SO = Open, Read 3.0 mA ICC2 Supply Current VCC = 5.0V at 2 MHz, SO = Open, Read, Write 5.0 mA ISB1 Standby Current V CC = 1.8V, CS = VCC 0.1 1.0 µA ISB2 Standby Current V CC = 2.7V, CS = VCC 0.2 2.0 µA ISB3 Standby Current V CC = 5.0V, CS = VCC 2.0 5.0 µA IIL Input Leakage V IN = 0V to VCC -3.0 µA IOL Output Leakage V IN = 0V to VCC, TAC = 0°C to 70°C -3.0 3.0 µA VIL (1) Input Low-voltage -0.6 V CC x 0.3 V VIH (1) Input High-voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low-voltage 4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V VOH1 Output High-voltage I OH = -1.6 mA V CC - 0.8 V VOL2 Output Low-voltage 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V VOH2 Output High-voltage I OH = -100 µA V CC - 0.2 V

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0675M–SEEPR–9/03 AC Characteristics Applicable over recommended operating range from T AI = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 3.0 2.1 0.5 MHz tRI Input Rise Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 µs tFI Input Fall Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 µs tWH SCK High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 133 200 800 ns tWL SCK Low Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 133 200 800 ns tCS CS High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 250 250 1000 ns tCSS CS Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 250 250 1000 ns tCSH CS Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 250 250 1000 ns tSU Data In Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 100 ns tH Data In Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 100 ns tHD Hold Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 100 100 400 tCD Hold Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 200 200 400 ns tV Output Valid 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 133 200 800 ns tHO Output Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 ns

0675M–SEEPR–9/03 Note: 1. This parameter is characterized and is not 100% tested. tLZ Hold to Output Low Z 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 100 100 100 ns tHZ Hold to Output High Z 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 100 100 100 ns t DIS Output Disable Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 250 250 1000 ns tWC Write Cycle Time 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 ms Endurance (1) 5.0V , 25°C, Page Mode 1M Write Cycles AC Characteristics (Continued) Applicable over recommended operating range from T AI = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units

6 AT25080/160/320/640

0675M–SEEPR–9/03 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080/160/320/640 always operates as a slave. TRANSMITTER/RECEIVER: The AT25080/160/320/640 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080/160/320/640, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25080/160/320/640 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080/160/320/640. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta- tus register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25080/160/320/640 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

0675M–SEEPR–9/03 SPI Serial Interface

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0675M–SEEPR–9/03 Functional The AT25080/160/320/640 is designed to interface directly with the synchronous serial periph- eral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080/160/320/640 ut ilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the sta- tus of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be deter- mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 1. Instruction Set for the AT25080/160/320/640 Table 2. Status Register Format Table 3. Read Status Register Bit Definition Bit 2 (BP0) See Table 4 on page 9. Bit 3 (BP1) See Table 4 on page 9. Bits 4 - 6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5 on page 9. Bits 0 - 7 are 1s during an internal write cycle.

corresponding status register control bits are shown in Table 4. memory which are not block-protected. Table 4. Block Write Protect Bits Table 5. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

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address allowing the entire memory to be read in one cont inuous READ cycle. be ignored except the RDSR instruction. the SCK low-time immediately after clocking in the D0 (LSB) data bit. the WRITE programming cycle. required to re-initiate the serial communication. Table 6. Address Key

0675M–SEEPR–9/03 Timing Diagrams Synchronous Data Timing (for Mode 0) WREN Timing WRDI Timing SO VOH VOL HI-Z HI-Z tV VALID INSI VIH VIL tHtSU tDIS SCK VIH VIL tWH tCSH CS VIH VIL tCSS tCS tWL tHO

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0675M–SEEPR–9/03 RDSR Timing WRSR Timing READ Timing CS SCK 0123456789 1 0 1 1 1 2 1 3 1 4 SI INSTRUCTION SO 76543210 DATA OUT MSB HIGH IMPEDANCE HIGH IMPEDANCE INSTRUCTION DATA IN 8 9 10 11 12 13 14 15 CS SCK SI SO CS SCK SI SO ... 89 1 0 15 14 13 11 20 21 22 23 24 25 26 27 28 29 30 HIGH IMPEDANCE INSTRUCTION BYTE ADDRESS MSB DATA OUT

0675M–SEEPR–9/03 WRITE Timing HOLD Timing 0 0 1 1 2 2 3 3... 89 1 0 15 14 13 11 20 21 22 23 24 25 26 27 28 29 30 31 HIGH IMPEDANCE CS SCK SI SO INSTRUCTION BYTE ADDRESS DATA IN SO SCK HO LD tCD tHD tHZ tLZ tCD tHD CS

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0675M–SEEPR–9/03 Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics table s. Ordering Code Package Operation Range A T25080-10PI-2.7 A T25080N-10SI-2.7 A T25080T1-10TI-2.7 8P3 8S1 14A2 Industrial (-40°C to 85°C) A T25080-10PI-1.8 A T25080N-10SI-1.8 A T25080T1-10TI-1.8 8P3 8S1 14A2 Industrial (-40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V)

0675M–SEEPR–9/03 Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics table s. Ordering Code Package Operation Range A T25160-10PI-2.7 A T25160N-10SI-2.7 A T25160T1-10TI-2.7 8P3 8S1 14A2 Industrial (-40°C to 85°C) A T25160-10PI-1.8 A T25160N-10SI-1.8 A T25160T1-10TI-1.8 8P3 8S1 14A2 Industrial (-40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V)

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0675M–SEEPR–9/03 Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics table s. Ordering Code Package Operation Range A T25320-10PI-2.7 A T25320N-10SI-2.7 A T25320T1-10TI-2.7 8P3 8S1 14A2 Industrial (-40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)

0675M–SEEPR–9/03 Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics table s. Ordering Code Package Operation Range A T25640-10PI-2.7 A T25640N-10SI-2.7 A T25640T1-10TI-2.7 8P3 8S1 14A2 Industrial (-40°C to 85°C) A T25640-10PI-1.8 A T25640N-10SI-1.8 A T25640T1-10TI-1.8 8P3 8S1 14A2 Industrial (-40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V)

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0675M–SEEPR–9/03 Packaging Information 8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B D E e Lb2 b A2 A N eA c

4 PLCS

(Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. A 0.210 2 A2 0.115 0.1 30 0.195 b 0.014 0.01 8 0.022 5 b2 0.045 0.060 0.070 6 b3 0.0 30 0.0 39 0.045 6 c 0.00 8 0.010 0.014 D 0. 355 0. 365 0.400 3 D1 0.005 3 E 0. 300 0. 310 0. 325 4 E1 0.240 0.250 0.2 80 3 e 0.100 B SC eA 0. 300 BSC 4 L 0.115 0.1 30 0.1

0675M–SEEPR–9/03 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

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0675M–SEEPR–9/03 14A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 12/28/01 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 4.90 5.00 5.10 2, 5 E 6.40 B SC E1 4. 30 4.40 4.50 3, 5 A – – 1.20 A2 0. 80 1.00 1.05 b 0.19 – 0. 30 4 e 0.65 B SC L 0.45 0.60 0.75 L1 1.00 REF A L D E E1 e b 14A2,14-lead (4.4 x 5 mm Body), 0.65 Pitch, Thin Shrink Small Outline Package (TSSOP) Notes: 1. Thi s drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for additional information. 2. Dimen sion D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimen sion E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimen sion b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in exce ss of the b dimension at maximum material condition. Dambar cannot be located on the lower r adius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimen sion D and E1 to be determined at Datum Plane H. 14A2 A Top View Side View End View

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