Download PDFAT25320B ATMEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 23
Technical content
Features
- Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation – 1.8 (V CC = 1.8V to 5.5V) 20 MHz Clock Rate (5V) 32-byte Page Mode Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years Automotive Devices Available 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead TSSOP and 8-lead Ultra Lead Frame Land Grid Array (ULA) Packages Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
Description
The AT25320B/640B provides 32768/65536 bits of serial electrically-erasable pro- grammable read-only memory (EEPROM) organized as 4 096/8192 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25320B/640B is available in space-saving 8-lead PDIP, 8- lead JEDEC SOIC, 8-lead Ultra Thin Mini- MAP (MLP 2x3), 8-lead Ultra Lead Frame Land Grid Array (ULA) and 8-lead TSSOP packages. The AT25320B/640B is enabled through the Chip Select pin (CS ) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate erase cycle is required before write. Table 0-1. Pin Configuration Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input SPI Serial EEPROMs 32K (4096 x 8) 64K (8192 x 8) AT25320B AT25640B Advance Information 8535B–SEEPR–7/08 CS SO WP GND VCC HOLD SCK SI 8-lead PDIP CS SO WP GND VCC HOLD SCK SI 8-lead TSSOP
8535B–SEEPR–7/08 AT25320B/640B Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware da ta protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. CS SO WP GND VCC HOLD SCK SI 8-lead SOIC VCC HOLD SCK SI CS SO WP GND 8-lead Ultra Thin Mini-MAP (MLP 2x3) Bottom View 8-ball dBGA2 VCC HOLD SCK SI CS SO WP GND Bottom View VCC HOLD SCK SI CS SO WP GND 8-lead Ultra Lead Fr ame Land Gr id Arr ay (ULA) Bottom View Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin
8535B–SEEPR–7/08 AT25320B/640B Figure 0-1. Block Diagram Table 0-2. Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested. Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions Max Units Conditions COUT Output Capacitance (SO) 8 pF V OUT = 0V CIN Input Capacitance (CS, SCK, SI, WP, HOLD)6 p F V IN = 0V
8535B–SEEPR–7/08 AT25320B/640B Table 0-3. DC Characteristics Notes: 1. V IL min and VIH max are reference only and are not tested. 2. Worst case measured at 85 °C Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter Test Co ndition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current V CC = 5.0V at 20 MHz, SO = Open, Read 7.5 10.0 mA ICC2 Supply Current VCC = 5.0V at 20 MHz, SO = Open, Read, Write 4.0 10.0 mA ICC3 Supply Current VCC = 5.0V at 5 MHz, SO = Open, Read, Write 4.0 6.0 mA ISB1 Standby Current V CC = 1.8V, CS = VCC < 0.1 6.0 (2) µA ISB2 Standby Current V CC = 2.7V, CS = VCC 0.3 7.0 (2) µA ISB3 Standby Current V CC = 5.0V, CS = VCC 2.0 10.0 (2) µA IIL Input Leakage V IN = 0V to VCC –3.0 3.0 µA IOL Output Leakage V IN = 0V to VCC, TAC = 0°C to 70°C –3.0 3.0 µA VIL (1) Input Low-voltage –0.6 V CC x 0.3 V VIH (1) Input High-voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low-voltage 4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V VOH1 Output High-voltage I OH = −1.6 mA V CC - 0.8 V VOL2 Output Low-voltage 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V VOH2 Output High-voltage I OH = −100 µA V CC - 0.2 V
8535B–SEEPR–7/08 AT25320B/640B Table 0-4. AC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5–5.5 2.7–5.5 1.8–5.5 MHz tRI Input Rise Time 4.5–5.5 2.7–5.5 1.8–5.5 µs tFI Input Fall Time 4.5–5.5 2.7–5.5 1.8–5.5 µs tWH SCK High Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tWL SCK Low Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tCS CS High Time 4.5–5.5 2.7–5.5 1.8–5.5 100 ns tCSS CS Setup Time 4.5–5.5 2.7–5.5 1.8–5.5 100 ns tCSH CS Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 100 ns tSU Data In Setup Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tH Data In Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tHD HOLD Setup Time 4.5–5.5 2.7–5.5 1.8–5.5 tCD HOLD Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 ns tV Output Valid 4.5–5.5 2.7–5.5 1.8–5.5 ns tHO Output Hold Time 4.5–5.5 2.7–5.5 1.8–5.5 ns
8535B–SEEPR–7/08 AT25320B/640B Note: 1. This parameter is characterized and is not 100% tested. 1. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25320B/640B always operates as a slave. TRANSMITTER/RECEIVER: The AT25320B/640B has separate pins designated for data trans- mission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25320B/640B, and the serial ou tput pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25320B/640B is selected when the CS pin is low. When the device is not selected, data will not be accepted vi a the SI pin, and the serial ou tput pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25320B/640B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communi- cation, the HOLD pin is brought high while the SCK pi n is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg- ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write tLZ HOLD to Output Low Z 4.5–5.5 2.7–5.5 1.8–5.5 100 ns tHZ HOLD to Output High Z 4.5–5.5 2.7–5.5 1.8–5.5 200 ns tDIS Output Disable Time 4.5–5.5 2.7–5.5 1.8–5.5 200 ns tWC Write Cycle Time 4.5–5.5 2.7–5.5 1.8–5.5 ms Endurance(1) 3.3V, 25°C, Page Mode 1M Write Cycles Table 0-4. AC Characteristics (Continued) Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units
8535B–SEEPR–7/08 AT25320B/640B operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25320B/640B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. Figure 1-1. SPI Serial Interface 2. Functional Description The AT25320B/640B is designed to interface dire ctly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25320B/640B utilizes an 8-bit instruction register. The list of instructions and their opera- tion codes are contained in Table 2-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. AT25320B/640B Table 2-1. Instruction Set for the AT25320B/640B Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register
8535B–SEEPR–7/08 AT25320B/640B WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. Th e WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register in struction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protec- tion employed. These bits are set by using the WRSR instruction. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25320B/640B is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read onl y. The block write protection levels and corresponding status register control bits are shown in Table 2-4 on page 9. The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, t WC, RDSR). WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array Table 2-2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 2-3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY) indicates the device is READY . Bit 0 = “1” indicates the write cycle is in progress. Bit 1 (WEN) Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the device is write enabled. Bit 2 (BP0) See Table 2-4 on page 9. Bit 3 (BP1) See Table 2-4 on page 9. Bits 4–6 are “0”s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 2-5 on page 9. Bits 0–7 are “1”s during an internal write cycle. Table 2-1. Instruction Set for the AT25320B/640B Instruction Name Instruction Format Operation
8535B–SEEPR–7/08 AT25320B/640B The WRSR instruction also allows the user to enable or disable the write protect (WP ) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Ha rdware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the block-pro- tected sections in the memory array are disabled. Writes are only allowed to sections of the memory that are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low. READ SEQUENCE (READ): Reading the AT25320B/640B via the Serial Output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the read op- code is transmitted via the SI line followed by the byte address to be read (A15–A0, see Table 2- 6). Upon completion, any data on the SI line will be ignored. The data (D7 –D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowe st address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25320B/640B, two separate instruc- tions must be executed. First, the device must be write enabled via the WREN instruction. Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal wr ite cycle, all commands will be ignored except the RDSR instruction. Table 2-4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP1 BP0 AT25320B AT25640B 0 0 0 None None 1(1/4) 0 1 0C00 −0FFF 1800 −1FFF 2(1/2) 1 0 0800 −0FFF 1000 −1FFF 3(All) 1 1 0000 −0FFF 0000 −1FFF Table 2-5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writeable Writeable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writeable Protected
X High 0 Protected Protected Protected X High 1 Protected Writeable Writeable
8535B–SEEPR–7/08 AT25320B/640B A write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15 –A0) and the data (D7–D0) to be programmed (see Table 2-6). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a read status register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25320B/640B is capable of a 32-byte page wr ite operation. After each byte of data is received, the five low-order address bits are internally incremented by one; the high-order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll over and the previously wr itten data will be overwritten. The AT25320B/640B is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. 3. Timing Diagrams Figure 3-1. Synchronous Data Timing (for Mode 0) Table 2-6. Address Key Address AT25320B AT25640B AN A11–A0 A12–A0 Don’t Care Bits A 15–A12 A15–A13 SO VOH VOL HI-Z HI-Z tV VALID INSI VIH VIL tHtSU tDIS SCK VIH VIL tWH tCSH CS VIH VIL tCSS tCS tWL tHO
8535B–SEEPR–7/08 AT25320B/640B Figure 3-8. HOLD Timing SO SCK HOLD tCD tHD tHZ tLZ tCD tHD CS
8535B–SEEPR–7/08 AT25320B/640B Notes: 1. “B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP , Ultra Thin Mini-MAP , SOT23, and dBGA2 = 5K per reel. 3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. 4. AT25320B Ordering Information Ordering Code Voltage Package Operation Range AT25320B-PU (Bulk form only) 1.8 8P3 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) AT25320BN-SH-B(1) (NiPdAu Lead Finish) 1.8 8S1 AT25320BN-SH-T(2) (NiPdAu Lead Finish) 1.8 8S1 AT25320B-TH-B(1) (NiPdAu Lead Finish) 1.8 8A2 AT25320B-TH-T(2) (NiPdAu Lead Finish) 1.8 8A2 AT25320BY6-YH-T(2) (NiPdAu Lead Finish) 1.8 8Y6 AT25320BD3-DH-T(2) (NiPdAu Lead Finish) 1.8 8D3 AT25320BU2-UU-T(2) (NiPdAu Lead Finish) 1.8 8U2-1 AT25320B-W-11(3) 1.8 Die Sale Industrial Temperature (−40 to 85°C) Package Type 8P3 8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm) 8D3 8-lead, 1.8 mm x 2.2 mm Body, Ultra Leadframe Land Grid Array (ULA) 8U2-1 8-lead, 8.35 mm x 3.73 mm Body, 0.75 mm Pitch, VFBGA Package (dBGA2) Options −1.8 Low Voltage (1.8 to 5.5V)
8535B–SEEPR–7/08 AT25320B/640B Notes: 1. “B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP , Ultra Thin Mini-MAP , SOT23, and dBGA2 = 5K per reel. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. 5. AT25640B Ordering Information Ordering Code Voltage Package Operation Range AT25640B-PU (Bulk form only) 1.8 8P3 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) AT25640BN-SH-B(1) (NiPdAu Lead Finish) 1.8 8S1 AT25640BN-SH-T(2) (NiPdAu Lead Finish) 1.8 8S1 AT25640B-TH-B(1) (NiPdAu Lead Finish) 1.8 8A2 AT25640B-TH-T(2) (NiPdAu Lead Finish) 1.8 8A2 AT25640BY6-YH-T(2) (NiPdAu Lead Finish) 1.8 8Y6 AT25640BD3-DH-T(2) (NiPdAu Lead Finish) 1.8 8D3 AT25640BU2-UU-T(2) (NiPdAu Lead Finish) 1.8 8U2-1 AT25640B-W-11(3) 1.8 Die Sale Industrial Temperature (−40 to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3mm) 8D3 8-lead, 1.8 mm x 2.2 mm Body, Ultra Leadframe Land Grid Array (ULA) 8U2-1 8-lead, 8.35 mm x 3.73 mm Body, 0.75 mm Pitch, VFBGA Package (dBGA2) Options −1.8 Low Voltage (1.8 to 5.5V)
8535B–SEEPR–7/08 AT25320B/640B 6. Packaging Information 8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c
4 PLCS
A – – 0.210 2 A2 0.115 0.1 30 0.195 b 0.014 0.01 8 0.022 5 b2 0.045 0.060 0.070 6 b3 0.0 30 0.0 39 0.045 6 c 0.00 8 0.010 0.014 D 0. 355 0. 365 0.400 3 D1 0.005 – – 3 E 0. 300 0. 310 0. 325 4 E1 0.240 0.250 0.2 80 3 e 0.100 B SC eA 0. 300 BSC 4 L 0.115 0.1 30 0.150 2 Top View Side View End View
8535B–SEEPR–7/08 AT25320B/640B 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L
8535B–SEEPR–7/08 AT25320B/640B 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e
8535B–SEEPR–7/08 AT25320B/640B 8Y6 – Mini MAP San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) D8Y6 10/16/07 Notes: 1. Thi s drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, toler ances, datums, etc. 2. Dimen sion b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the termin al has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the device through this pad, so if soldered it should be tied to ground COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.00 B SC E 3.00 BSC D2 1.40 1.50 1.60 E2 - - 1.40 A - - 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 A3 0.20 REF L 0.20 0. 30 0.40 e 0.50 B SC b 0.20 0.25 0. 30 2 A2A2 b (8X)(8X) Pin 1 IDPin 1 ID Pin 1Pin 1 IndexIndex AreaArea A1A1 A3A3 D E A L (8X)L (8X) e (6X)e (6X) 1.50 REF .1.50 REF. D2D2 E2E2
8535B–SEEPR–7/08 AT25320B/640B 8D3 - ULA 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe Land Grid Array (ULA) D3 08D3 11/15/05 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 0.40 A1 0.00 – 0.05 D 1.70 1. 80 1.90 E 2.10 2.20 2. 30 b 0.15 0.20 0.25 e 0.40 TYP e1 1.20 REF L 0.25 0. 30 0. 35 0.10 0.15 b 6 57 E D 1 2 PIN #1 ID TOP VIEW L b A e PIN #1 ID SIDE VIEW BOTTOM VIEW
8535B–SEEPR–7/08 AT25320B/640B 8U2-1 - dBGA2 TITLE DRAWING NO.GPC REV. Package Drawing Contact: p ackagedrawings@atmel.com 8U2-1GWW C 8U2-1, 8 ball, 2.35 x 3.73 mm Body, 0.75 mm pitch 2/25/08 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0. 81 0.91 1.00 A1 0.15 0.20 0.25 A2 0.40 0.45 0.50 b 0.25 0. 30 0. 35 D 2. 35 BSC E 3.73 BSC e 0.75 B SC e1 0.74 REF d 0.75 B SC d1 0. 80 REF 2. Dimension 'b' is measured at the maximum solder ball diameter. 1. This drawing is for general information. Notes:
8535B–SEEPR–7/08 AT25320B/640B
Revision History
Doc. Rev. Date Comments 8535B 7/2008 Modified ‘Endurance’ parameter on page 6 8535A 4/2008 Initial document release.
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