AT25128_05 ATMEL

Document overview

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Technical content

Features

  • Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1)  Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)  3 MHz Clock Rate  64-byte Page Mode and Byte Write Operation  Block Write Protection – Protect 1/4, 1/2, or Entire Array  Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection  Self-timed Write Cycle (5 ms Typical)  High-reliability – Endurance: 100,000 Write Cycles – Data Retention: >200 Years  Automotive Grade, Extended Temperature and Lead-Free Devices Available  8-lead PDIP, 8-lead EIAJ SOIC, 8-lead and 16-lead JEDEC SOIC, 14-lead and 20-lead TSSOP, and 8-lead Leadless Array Packages

Description

The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead PDIP (AT25128/256), 8-lead EIAJ SOIC (AT25128/256), 8-lead and 16-lead JEDEC SOIC (AT25128), 14-lead TSSOP (AT25128), 20-lead TSSOP (AT25128/256), and 8-lead Leadless Array (AT25256) packages. In addition, the entire Table 1. Pin Configuration *Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.

2 AT25128/256

cycle is required before Write. pin to protect against inadvertent write attempts to the status register. Figure 1. Block Diagram periods may affect device reliability.

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL and VIH max are reference only and are not tested. Table 2. Pin Capacitance(1) Table 3. DC Characteristics

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Table 4. AC Characteristics

0872O–SEEPR–03/05 Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK ) is always an input, the AT25128/256 always operates as a slave. TRANSMITTER/RECEIVER: The AT25128/256 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128/256, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the seri al output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial comm unication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the inter nal write cycle has already been initiated, WP going low will have no effect on any write operation to the stat us register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25128/256 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. tHZ Hold to Output High Z 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 100 200 300 ns tDIS Output Disable Time 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 200 250 1000 ns tWC Write Cycle Time 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 ms Endurance(1) 5.0V, 25°C, Page Mode 100K Write Cycles Table 4. AC Characteristics (Continued)

6 AT25128/256

0872O–SEEPR–03/05 Figure 2. SPI Serial Interface The AT25128/256 is designed to interface dire ctly with the synchronous serial periph- eral interface (SPI) of the 6800 type series of microcontrollers. The AT25128/256 utilizes an 8-bi t instruction re gister. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. AT25128/256 Table 5. Instruction Set for the AT25128/256

one of four levels of protection. The AT25128/256 is divided into four array segments. tection levels and corresponding status register control bits are shown in Table 8. Table 6. Status Register Format Table 7. Read Status Register Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY ) indicates the device is READY . Bit 0 = “1” indicates the write cycle is in progress. indicates the device is WRITE ENABLED. Bits 4 - 6 are “0”s when device is not in an internal write cycle. Bits 0 – 7 are “1”s during an internal write cycle. Table 8. Block Write Protect Bits

8 AT25128/256

the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. the lowest address allowing the entire memory to be read in one continuous read cycle. will be ignored except the RDSR instruction. must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. Table 9. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

ted, the address counter will roll over and the previously written data will be overwritten. ing edge is required to reinitiate the serial communication. Figure 3. Synchronous Data Timing Table 10. Address Key

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Figure 4. WREN Timing Figure 5. WRDI Timing Figure 6. RDSR Timing

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Figure 10. HOLD Timing

0872O–SEEPR–03/05 Notes: 1. This device is not recommended for new designs. Please refer to AT25128A. 2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. AT25128(1) Ordering Information Ordering Code(2) Package Operation Range AT25128-10PI-2.7 AT25128N-10SI-2.7 AT25128W-10SI-2.7 AT25128N1-10SI-2.7 AT25128T1-10TI-2.7 8P3 8S1 8S2 16S1 14A2 Industrial Temperature (–40°C to 85°C) AT25128-10PI-1.8 AT25128N-10SI-1.8 AT25128W-10SI-1.8 AT25128N1-10SI-1.8 AT25128T1-10TI-1.8 8P3 8S1 8S2 16S1 14A2 Industrial Temperature (–40°C to 85°C) AT25128N-10SJ-2.7 AT25128N-10SJ-1.8 8S1 8S1 Lead-Free/Industrial Temperature (–40°C to 85°C) AT25128N-10SE-2.7 8S1 High Grade/Extended Temperature (–40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 16S1 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options –2.7 Low-voltage (2.7V to 5.5V) –1.8 Low-voltage (1.8V to 5.5V)

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0872O–SEEPR–03/05 Notes: 1. This device is not recommended for new designs. Please refer to AT25256A. 2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. AT25256(1) Ordering Information Ordering Code(2) Package Operation Range AT25256-10PI-2.7 AT25256W-10SI-2.7 AT25256-10CI-2.7 AT25256T2-10TI-2.7 8P3 8S2 8CN3 20A2 Industrial Temperature (–40°C to 85°C) AT25256-10PI-1.8 AT25256W-10SI-1.8 AT25256-10CI-1.8 AT25256T2-10TI-1.8 8P3 8S2 8CN3 20A2 Industrial Temperature (–40°C to 85°C) AT25256W-10SJ-2.7 AT25256W-10SJ-1.8 8S2 8S2 Lead-Free/Industrial Temperature (–40°C to 85°C) AT25256W-10SE-2.7 8S2 High Grade/Extended Temperature (–40°C to 125°C)Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8CN3 8-lead, 0.230" Wide, Leadless Array Package (LAP) 20A2 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options –2.7 Low-voltage (2.7V to 5.5V) –1.8 Low-voltage (1.8V to 5.5V)

0872O–SEEPR–03/05 Packaging Information 8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c

4 PLCS

A – – 0.210 2 A2 0.115 0.1 30 0.195 b 0.014 0.01 8 0.022 5 b2 0.045 0.060 0.070 6 b3 0.0 30 0.0 39 0.045 6 c 0.00 8 0.010 0.014 D 0. 355 0. 365 0.400 3 D1 0.005 – – 3 E 0. 300 0. 310 0. 325 4 E1 0.240 0.250 0.2 80 3 e 0.100 B SC eA 0. 300 BSC 4 L 0.115 0.1 30 0.150 2 Top View Side View End View

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0872O–SEEPR–03/05 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1. 35 – 1.75 B 0. 31 – 0.51 C 0.17 – 0.25 D 4. 80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 B SC L 0.40 – 1.27 ∅ 0° – 8° Top View End View Side View e B D A N E C L

0872O–SEEPR–03/05 8S2 – EIAJ SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) 10/7/03 8S2 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. Thi s drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mi smatch of the upper and lower dies and resin burrs are not included. 3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determine s the true geometric position. A 1.70 2.16 A1 0.05 0.25 b 0. 35 0.4 8 5 C 0.15 0. 35 5 D 5.1 3 5. 35 E1 5.1 8 5.40 2, 3 E 7.70 8.26 L 0.51 0. 85 ∅ 0° 8° e 1.27 B SC 4 End View Side View e b A D E N C L Top View

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0872O–SEEPR–03/05 8CN3 – LAP 1150 E.Cheyenne Mtn Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8CN3, 8-lead, (6 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) B8CN3 11/8/04 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.36 0.41 0.46 Note 1 D 5.89 5.99 6.09 E 4.83 4.93 5.03 e 1.27 BSC e1 0.56 REF L 0.62 0.67 0.72 Note 1 L1 0.92 0.97 1.02 Note 1 Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm Pin1 Corner Marked Pin1 Indentifier 0.10 mm TYP Top View L b e Side View A Bottom View E D

0872O–SEEPR–03/05 16S1 – JEDEC SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 16S1 10/15/01 16S1, 16-lead, 0.150" Body, Plastic Gull Wing Small Outline (SOIC ) A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. L is the length of terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024 in). H N Top View C E A B L e D A 1.35 – 1.75 B 0.33 – 0.51 5 C 0.19 – 0.25 D 9.80 – 10.00 2 E 3.80 – 4.00 3 e 1.27 BSC H 5.80 – 6.20 4 L 0.40 – 1.27 Side View End View

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0872O–SEEPR–03/05 14A2 – TSSOP D 4.90 5.00 5.10 2, 5 E 6.40 B SC E1 4. 30 4.40 4.50 3, 5 A – – 1.20 A2 0. 80 1.00 1.05 b 0.19 – 0. 30 4 e 0.65 B SC L 0.45 0.60 0.75 L1 1.00 REF San Jose, CA 95131 TITLE DRAWING NO. R REV. 12/28/01 A L D E E1 e b 14A2,14-lead (4.4 x 5 mm Body), 0.65 Pitch, Thin Shrink Small Outline Package (TSSOP) Notes: 1. Thi s drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for additional information. 2. Dimen sion D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimen sion E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimen sion b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in exce ss of the b dimension at maximum material condition. Dambar cannot be located on the lower r adius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimen sion D and E1 to be determined at Datum Plane H. 14A2 A Top View Side View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

0872O–SEEPR–03/05 20A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 6/3/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 6.40 6.50 6.60 2, 5 E 6.40 B SC E1 4. 30 4.40 4.50 3, 5 A – – 1.20 A2 0. 80 1.00 1.05 b 0.19 – 0. 30 4 e 0.65 B SC L 0.45 0.60 0.75 L1 1.00 REF 20A2, 20-lead (4.4 x 6.5 mm Body), 0.65 pitch, Thin Shrink Small Outline Package (TSSOP) Notes: 1. Thi s drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional inform ation. 2. Dimen sion D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimen sion E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimen sion b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minim um space between protrusion and adjacent lead is 0.07 mm. 5. Dimen sion D and E1 to be determined at Datum Plane H. 20A2 C A L D A2 E E1 e b Top View Side View End View

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