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Document overview
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Technical content
Features
Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) ̶ Data Sheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation ̶ VCC = 1.8V to 5.5V 20MHz Clock Rate (5V) 64-byte Page Mode and Byte Write Operation Block Write Protection ̶ Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5ms max) High Reliability ̶ Endurance: 1,000,000 Write Cycles ̶ Data Retention: 100 Years Green (Pb/Halogen-free/RoHS Compliant) Packaging Options Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT25128B/256B provides 131,072/262,144 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25128B/256B is available in space saving JEDEC SOIC, TSSOP, UDFN, and VFBGA packages. The AT25128B/256B is enabled through the Chip Select pin ( CS) and accessed via a 3-Wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Block Write protection is enabled by programming the status register with one of four blocks of Write Protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware Data Protection is provided via the WP pin to protect against inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. AT25128B and AT25256B SPI Serial EEPROM 128K (16,384 x 8), 256K (32,768 x 8) DATASHEET
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 1. Pin Configurations Table 1-1. Pin Configurations 2. Absolute Maximum Ratings* Pin Name Function CS Chip Select GND Ground HOLD Suspends Serial Input SCK Serial Data Clock SI Serial Data Input SO Serial Data Output VCC Power Supply WP Write Protect Voltage on any pin *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Drawings are not to scale. 8-lead SOIC CS SO WP GND VCC HOLD SCK SI Top View Top View 8-lead TSSOP CS SO WP GND V CC HOLD SCK SI VCC HOLD SCK SI CS SO WP GND 8-ball VFBGA Bottom View 8-pad UDFN Bottom View VCC HOLD SCK SI CS SO WP GND
3AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 3. Block Diagram Figure 3-1. Block Diagram Memory Array 16,384/32,768 x 8 Status Register Data Register Mode Decode Logic Clock Generator Output Buffer Address Decoder VCC
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 4. Electrical Characteristics
4.1 Pin Capacitance (1)
Table 4-1. Pin Capacitance Note: 1. This parameter is characterized and is not 100% tested.
4.2 DC Characteristics
Table 4-2. DC Characteristics Note: 1. V IL min and VIH max are reference only and are not tested. Applicable over recommended operating range from TA = 25°C, f = 1MHz, VCC = +5V (unless otherwise noted). Symbol Test Conditions Max Units Conditions COUT Output Capacitance (SO) 8 pF VOUT = 0V CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5V at 20MHz SO = Open, Read 9 10 mA ICC2 Supply Current VCC = 5V at 10MHz SO = Open, Read, Write 5 7 mA ICC3 Supply Current VCC = 5V at 1MHz SO = Open, Read, Write 2.2 3.5 mA ISB1 Standby Current VCC = 1.8V, CS = VCC 0.2 3 μA ISB2 Standby Current VCC = 2.5V, CS = VCC 0.5 3 μA ISB3 Standby Current VCC = 5.0V, CS = VCC 2 5 μA IIL Input Leakage VIN = 0V to VCC -3 3 μA IOL Output Leakage VIN = 0V to VCC TAC = 0°C to 70°C -3 3 μA VIL (1) Input Low-voltage -1 VCC x 0.3 V VIH (1) Input High-voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low-voltage 3.6V VCC 5.5V IOL = 3.00mA 0.4 V VOH1 Output High-voltage 3.6V VCC 5.5V IOH = -1.60mA VCC – 0.8 V VOL2 Output Low-voltage 1.8V VCC 3.6V IOL = 0.15mA 0.2 V VOH2 Output High-voltage 1.8V VCC 3.6V IOH = -100μA VCC – 0.2 V
5AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014
4.3 AC Characteristics
Table 4-3. AC Characteristics Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 MHz tRI Input Rise Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 μs tFI Input Fall Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 μs tWH SCK High Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns tWL SCK Low Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns tCS CS High Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 100 200 ns tCSS CS Setup Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 100 200 ns tCSH CS Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 100 200 ns tSU Data In Setup Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns tH Data In Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns tHD Hold Setup Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns tCD Hold Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns tV Output Valid 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns tHO Output Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ns
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 Note: 1. This parameter is characterized and is not 100% tested. 5. Serial Interface Description Master: The device that generates the serial clock. Slave: Because the Serial Clock pin (SCK) is always an input, the AT25128B/256B always operates as a slave. Transmitter/Receiver: The AT25128B/256B has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains the opcode which defines the operations to be performed. Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25128B/256B, and the serial output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. Chip Select: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the SO pin will remain in a high-impedance state. Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high-impedance state. Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25128B/256B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to one. tLZ Hold to Output Low Z 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 ns tHZ Hold to Output High Z 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 ns tDIS Output Disable Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 ns tWC Write Cycle Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 ms Endurance(1) 3.3V, 25C, Page Mode 1,000,000 Write Cycles Table 4-3. AC Characteristics (Continued) Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units
7AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 Figure 5-1. SPI Serial Interface Master: Microcontroller Slave: AT25128B/256B Data Out (MOSI) Data In (MISO) Serial Clock (SPI CK) SS0 SS1 SS2 SS3 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 6. Functional Description The AT25128B/256B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 6800 series of microcontrollers. The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Figure 6-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 6-1. Instruction Set for the AT25010B/020B/040B Write Enable (WREN): The device will power-up in the Write Disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during a WREN instruction. Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. Read Status Register (RDSR): The Read Status Register instruction provides access to the status register. The Read/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6-2. Status Register Format Table 6-3. Read Status Register Bit Definition Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is ready. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not write enabled. Bit 1 = 1 indicates the device is write enabled. Bit 2 (BP0) See Table 6-4. Bit 3 (BP1) See Table 6-4. Bits 4 to 6 are zeros when the device is not in an internal write cycle. Bit 7 (WPEN) See Table 6-5. Bits 0 to 7 are ones during an internal write cycle.
9AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128B/256B is divided into four array segments. None, one-quarter (¼), one-half (½), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read-only. The block write protection levels and corresponding status register control bits are shown in Table 6-4. Bits BP1, BP0, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, t WC, RDSR). Table 6-4. Block Write Protect Bits The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is one. The hardware write protection is disabled when either the WP pin is high or the WPEN bit is zero. When the device is hardware write protected, writes to the Status Register including the Block Protect bits, the WPEN bit, and the block protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP pin is held low. Table 6-5. WPEN Operation Read Sequence (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read opcode is transmitted via the SI line followed by the byte address to be read (Table 6-6). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The Read Sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll-over to the lowest address allowing the entire memory to be read in one continuous read cycle. Level Status Register Bits Array Addresses Protected BP1 BP0 AT25128B AT25256B 0 0 0 None None 1 ( ¼) 0 1 3000 – 3FFF 6000 – 7FFF 2 ( ½) 1 0 2000 – 3FFF 4000 – 7FFF 3 (All) 1 1 0000 – 3FFF 0000 – 7FFF WPEN WP WEN Protected Blocks Unprotected Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected X High 1 Protected Writable Writable
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 Write Sequence (WRITE): In order to program the AT25128B/256B, the Write Protect pin (WP) must be held high and two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write opcode is transmitted via the SI line followed by the byte address and the data (D7 D0) to be programmed (see Table 6-6 for the address key). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction. If Bit 0 is one, the write cycle is still in progress. If Bit 0 is zero, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25128B/256B is capable of an 64-byte Page Write operation. After each byte of data is received, the six low-order address bits are internally incremented by one; the high-order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll-over, and the previously written data will be overwritten. The AT25128B/256B is automatically returned to the Write Disable state at the completion of a write cycle. Note: If the WP pin is brought low or if the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. Table 6-6. Address Key Address AT25128B AT25256B AN A13 –A 0 A14 –A 0 Don’t Care Bits A15 –A 14 A15
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 8. Ordering Code Detail Atmel Designator Product Family Device Density Device Revision Shipping Carrier Option Operating Voltage 128 = 128 kilobit 256 = 256 kilobit 25 = Standard SPI Serial EPPROM B or Blank = Bulk (Tubes) T = Tape and Reel L = 1.8V to 5.5V Package Device Grade or Wafer/Die Thickness H = Green, NiPdAu Lead Finish, Industrial Temperature Range (-40°C to +85°C) U = Green, Matte Sn Lead Finish, Industrial Temperature Range (-40°C to +85°C) 11 = 11mil Wafer Thickness Package Option SS = JEDEC SOIC X = TSSOP MA = UDFN C = VFBGA WWU = Wafer Unsawn WDT = Die in Tape and Reel AT25128B-SSHL-B
15AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 9. Part Markings DRAWING NO. REV. TITLE 25128-256BSM A 3/11/14 25128-256BSM, AT25128B and AT25256B Package Marking Information Package Mark Contact: DL-CSO-Assy_eng@atmel.com Note 2: Package drawings are not to scale Note 1: designates pin 1 AT25128B and AT25256B: Package Marking Information Catalog Number Truncation AT25128B Truncation Code ###: 5DB AT25256B Truncation Code ###: 5EB Date Codes Voltages Y = Year M = Month WW = Work Week of Assembly % = Minimum Voltage 4: 2014 8: 2018 A: January 02: Week 2 L: 1.8V min 5: 2015 9: 2019 B: February 04: Week 4 7: 2017 1: 2021 L: December 52: Week 52 Country of Assembly Lot Number Grade/Lead Finish Material @ = Country of Assembly AAA...A = Atmel Wafer Lot Number U: Industrial/Matte Tin/SnAgCu H: Industrial/NiPdAu Trace Code Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel Example: AA, AB.... YZ, ZZ ATM: Atmel ATML: Atmel AAAAAAAA###% @ATMLHYWW 8-lead SOIC 8-lead TSSOP AAAAAAA ###% @ ATHYWW 8-pad UDFN ### H%@ YXX 2.0 x 3.0 mm Body ###U@YMXX 2.35 x 3.73 mm Body 8-ball VFBGA
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 10. Ordering Information Notes: 1. B = Bulk delivery in tubes. SOIC and TSSOP = 100 per tube 2. T = Tape and Reel SOIC = 4,000 per reel TSSOP, UDFN, and VFBGA = 5,000 per reel 3. Contact Atmel Sales for Wafer sales. Atmel Ordering Code Lead Finish Package Voltage Operation Range AT25128B-SSHL-B (1) NiPdAu (Lead-free/Halogen-free) 8S1 1.8V to 5.5V Industrial Temperature (-40 to +85C) AT25128B-SSHL-T (2) AT25128B-XHL-B (1) AT25128B-XHL-T (2) AT25128B-MAHL-T (2) 8MA2 AT25128B-CUL-T (2) SnAgCu (Lead-free/Halogen-free) 8U2-1 AT25128B-WWU11L (3) — Wafer AT25256B-SSHL-B (1) NiPdAu (Lead-free/Halogen-free) 8S1 1.8V to 5.5V Industrial Temperature (-40 to +85C) AT25256B-SSHL-T (2) AT25256B-XHL-B (1) AT25256B-XHL-T (2) AT25256B-MAHL-T (2) 8MA2 AT25256B-CUL-T (2) SnAgCu (Lead-free/Halogen-free) 8U2-1 AT25256B-WWU11L (3) — Wafer Package Type 8S1 8-lead, 0.15" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Plastic Ultra Thin Dual Flat No Lead (UDFN) 8U2-1 8-ball, 2.35mm x 3.73mm body, 0.75mm pitch, Very Thin, Fine-Pitch Ball Grid Array (VFBGA)
17AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 11. Packaging Information 11.1 8S1 — 8-lead JEDEC SOIC DRAWING NO. REV. TITLE GPC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ØØ 0° – 8° Ø E N TOP VIEW C END VIEW A b L e D SIDE VIEW Package Drawing Contact: packagedrawings@atmel.com 8S1 G 6/22/11 Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) SWB
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 11.2 8X — 8-lead TSSOP DRAWING NO. REV. TITLE GPC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 b 0.19 0.25 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF C 0.09 - 0.20 Side View End ViewTop View A L D N b Pin 1 indicator this corner E e Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. Package Drawing Contact: packagedrawings@atmel.com 8X E 2/27/14 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) TNR C
19AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 11.3 8MA2 — 8-pad UDFN DRAWING NO. REV. TITLE GPC 8MA2 F 6/6/14 8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No-Lead Package (UDFN) YNZ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.50 0.55 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 D 1.90 2.00 2.10 D2 1.20 - 1.60 E 2.90 3.00 3.10 E2 1.20 - 1.60 b 0.18 0.25 0.30 3 C 1.52 REF L 0.30 0.35 0.40 e 0.50 BSC K 0.20 - - TOP VIEW SIDE VIEW BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com C E Pin 1 ID D A e (6x) L (8x) b (8x) Pin#1 ID K Notes: 1. This drawing is for general information only. Refer to Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. 3. Dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 4. The Pin #1 ID on the Bottom View is an orientation feature on the thermal pad.
AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 11.4 8U2-1 — 8-ball VFBGA DRAWING NO. REV. TITLE GPC Package Drawing Contact: packagedrawings@atmel.com 8U2-1 G 6/11/13 8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GWW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.81 0.91 1.00 A1 0.15 0.20 0.25 A2 0.40 0.45 0.50 b 0.25 0.30 0.35 D 2.35 BSC E 3.73 BSC e 0.75 BSC e1 0.74 REF d 0.75 BSC d1 0.80 REF 2. Dimension 'b' is measured at the maximum solder ball diameter. 1. This drawing is for general Notes: A d 0.08 C C f 0.10 C Øb j n0.15 m CAB j n0.08 m C A (4X)d 0.10 B A1 BALL PAD CORNER D E SIDE VIEWTOP VIEW e (e1) d D C B A A1 BALL PAD CORNER (d1)
8 SOLDER BALLS
21AT25128B/256B [DATASHEET] Atmel-8698D-SEEPROM-AT25128B-256B-Datasheet_072014 12. Revision History Doc. Rev. Date Comments 8698D 07/2014 Update part markings, 8MA2 and 8U2-1 package drawings, package 8A2 to 8X, template, logos, and disclaimer page. No change to functional specification. 8698C 08/2011 Update 8A2 and 8S1 package drawings. Correct page 13, Device Density from 156K to 256K. Correct page 9, table headings. Correct cross references on pages 7, 8, and 9. 8698B 03/2010 Update Catalog Numbering Scheme. Update Ordering Information and package types. 8698A 12/2009 Initial document release.
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