AT25128A-10PI-2.7

AT25128A_05 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 21

Technical content

Features

• Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1)  Data Sheet Describes Mode 0 Operation  Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)  20 MHz Clock Rate (5V)  64-byte Page Mode and Byte Write Operation  Block Write Protection – Protect 1/4, 1/2, or Entire Array  Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection  Self-timed Write Cycle (5 ms Max)  High-reliability – Endurance: 1 Million Write Cycles – Data Retention: >100 Years  Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available  8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead SAP Packages  Die Sales: Wafer Form, Waffle Pack, and Bumped Die

Description

The AT25128A/256A provides 1 31,072/262,144 bits of seri al electric ally-erasable programmable read only memory (EEPROM) org anized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial appli- cations where low-power and low-voltage operation are essential. The devices are available in sp ace saving 8-lead PDIP , 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8- lead TSSOP , 8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate Erase cycle is required before Write. Table 1. Pin Configurations

2 AT25128A/256A

vided via the WP pin to protect against inadvertent write attempts to the status register. Figure 1. Block Diagram Note: 1. This p arameter is characterized and is not 100% tested. periods may affect device reliability. Table 2. Pin Capacitance(1)

Note: 1. V IL and VIH max are reference only and are not tested. Table 3. DC Characteristics Table 4. AC Characteristics

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Note: 1. This p arameter is characterized and is not 100% tested. Contact Atmel for further information. Table 4. AC Characteristics (Continued)

3368H–SEEPR–8/05 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the seri al clock pin ( SCK) is always an input, the AT2512 8A/256A always operates as a slave. TRANSMITTER/RECEIVER: The AT2512 8A/256A h as separate pins design ated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with C S going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no d ata will be shifted into the AT25128A/256A, and the seri al output pin ( SO) will rem ain in a high imped ance state until the f alling edge of C S is detected again. This will reiniti alize the seri al communication. CHIP SELECT: The AT2512 8A/256A is selected when the C S pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the C S pin to select the AT2512 8A/256A. When the device is selected and a seri al sequence is underw ay, HOLD can be used to p ause the seri al communication with the m aster device without resetting the seri al sequence. To p ause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low ( SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write oper ations when held high. When the WP pin is brought low and WPEN bit is “1”, all write oper a- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the st atus register. If the intern al write cycle h as already been initi ated, WP going low will h ave no effect on any write oper ation to the st atus register. The WP pin function is blocked when the WPEN bit in the st atus register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

6 AT25128A/256A

Figure 2. SPI Serial Interface

3368H–SEEPR–8/05 Functional The AT2512 8A/256A is designed to interf ace directly with the synchronous seri al peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT2512 8A/256A utilizes an 8-bit instruction re gister. The list of instructions and their operation codes are contained in see Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction dis ables all programming modes. The WRDI instruction is indepen- dent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Re ad Status Register instruction provides access to the st atus register. The Re ady/Busy and Write En able status of the device can be determined by the RD SR instruction. Similarly, the Block Write Protection bits indic ate the extent of protection employed. These bits are set by using the WR SR instruction. Table 5. Instruction Set for the AT25128A/256A Table 6. Status Register Format Table 7. Read Status Register Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY ) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. the device is write enabled. Bit 2 (BP0) See Table 8 on page 8. Bit 3 (BP1) See Table 8 on page 8. Bits 4 − 6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 9 on page 8. Bits 0 − 7 are “1”s during an internal write cycle.

8 AT25128A/256A

one of four levels of protection. The AT25128A/256A is divided into four array segments. tion levels and corresponding status register control bits are shown in Table 8. and functions as the regular memory cells (e.g. WREN, tWC, RDSR). the WPEN bit, and the block-protected sections in the memory array are dis abled. Writes are only allowed to sections of the memory which are not block-protected. “0”, as long as the WP pin is held low. the lowest address allowing the entire memory to be read in one continuous read cycle. Table 8. Block Write Protect Bits Table 9. WPEN Operation

0 X 0 Protected Protected Protected

1 Low 0 Protected Protected Protected

write cycle, all commands will be ignored except the RDSR instruction. occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. the Write programming cycle. the completion of a Write cycle. ing edge is required to re-initiate the serial communication. Table 10. Address Key

10 AT25128A/256A

Figure 3. Synchronous Data Timing Figure 4. WREN Timing Figure 5. WRDI Timing

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Figure 9. WRITE Timing Figure 10. HOLD Timing

3368H–SEEPR–8/05 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V r ange, please refer to perform ance values in the AC and DC Ch aracteristics tables. 2. “U” design ates Green package + RoHS compliant. 3.A v ailable in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please Contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT25128A-10PI-2.7 AT25128AN-10SI-2.7 AT25128AW-10SI-2.7 AT25128A-10TI-2.7 8P3 8S1 8S2 8A2 Industrial Temperature (−40°C to 85°C) AT25128A-10PI-1.8 AT25128AN-10SI-1.8 AT25128AW-10SI-1.8 AT25128A-10TI-1.8 8P3 8S1 8S2 8A2 Industrial Temperature (−40°C to 85°C) AT25128A-10PU-2.7(2) AT25128A-10PU-1.8(2) AT25128AN-10SU-2.7(2) AT25128AN-10SU-1.8(2) AT25128AW-10SU-2.7(2) AT25128AW-10SU-1.8(2) AT25128A-10TU-2.7(2) AT25128A-10TU-1.8(2) AT25128AU2-10UU-1.8(2) AT25128AY4-10YU-1.8(2) 8P3 8P3 8S1 8S1 8S2 8S2 8A2 8A2 8U2-1 8Y4 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) Die Sale Die Sale Industrial Temperature (−40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8U2-1 8-ball, die Ball Grid Array Package (dBGA2) 8A2 8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP) 8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) Options −2.7 Low-voltage (2.7V to 5.5V) −1.8 Low-voltage (1.8V to 5.5V)

14 AT25128A/256A

3368H–SEEPR–8/05 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V r ange, please refer to perform ance values in the AC and DC Ch aracteristics tables. 2. “U” design ates Green package + RoHS compliant. 3.A v ailable in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT25256A-10PI-2.7 AT25256AN-10SI-2.7 AT25256AW-10SI-2.7 AT25256A-10TI-2.7 8P3 8S1 8S2 8A2 Industrial Temperature (−40°C to 85°C) AT25256A-10PI-1.8 AT25256AN-10SI-1.8 AT25256AW-10SI-1.8 AT25256A-10TI-1.8 8P3 8S1 8S2 8A2 Industrial Temperature (−40°C to 85°C) AT25256A-10PU-2.7(2) AT25256A-10PU-1.8(2) AT25256AN-10SU-2.7(2) AT25256AN-10SU-1.8(2) AT25256AW-10SU-2.7(2) AT25256AW-10SU-1.8(2) AT25256A-10TU-2.7(2) AT25256A-10TU-1.8(2) AT25256AU2-10UU-1.8(2) AT25256AY4-10YU-1.8(2) 8P3 8P3 8S1 8S1 8S2 8S2 8A2 8A2 8U2-1 8Y4 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) Die Sale Die Sale Industrial Temperature (−40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8U2-1 8-ball, die Ball Grid Array Package (dBGA2) 8A2 8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP) 8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) Options −2.7 Low-voltage (2.7V to 5.5V) −1.8 Low-voltage (1.8V to 5.5V)

3368H–SEEPR–8/05 Packaging Information 8P3 – PDIP

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San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimen sions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA mea sured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c

4 PLCS

A – – 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 – – 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2 Top View Side View End View

16 AT25128A/256A

3368H–SEEPR–8/05 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

3368H–SEEPR–8/05 8S2 – EIAJ SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) 10/7/03 8S2 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. Thi s drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mi smatch of the upper and lower dies and resin burrs are not included. 3. It i s recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determine s the true geometric position. A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 2, 3 E 7.70 8.26 L 0.51 0.85 ∅ 0° 8° e 1.27 BSC 4 End View Side View e b A D E N C L Top View

18 AT25128A/256A

3368H–SEEPR–8/05 8U2-1 – dBGA2 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. PO8U2-1 A 6/24/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2) A 0.81 0.91 1.00 A1 0.15 0.20 0.25 A2 0.40 0.45 0.50 b 0.25 0.30 0.35 1 D 2.35 BSC E 3.73 BSC e 0.75 BSC e1 0.74 REF d 0.75 BSC d1 0.80 REF 1. Dimension 'b' is measured at the maximum solder ball diameter. This drawing is for general information only. d A Side View Top View Bottom View

8 Solder Balls

A B C D (e1) e A1 BALL PAD CORNER (d1) 1. b DA1 BALL PAD CORNER E

3368H–SEEPR–8/05 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

20 AT25128A/256A

3368H–SEEPR–8/05 8Y4 – SAP 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package (SAP) Y4 A8Y4 5/24/04 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 0.90 A1 0.00 – 0.05 D 5.80 6.00 6.20 E 4.70 4.90 5.10 D1 2.85 3.00 3.15 E1 2.85 3.00 3.15 b 0.35 0.40 0.45 e 1.27 TYP e1 3.81 REF L 0.50 0.60 0.70 A E A1 b PIN 1 INDEX AREA D A PIN 1 ID L e

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