AT25128A

AT25128A_07 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 18

Technical content

Features

• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation
• Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V)
• Automotive Temperature Range −40°C to +125°C
• 5 MHz Clock Rate
• 64-byte Page Mode and Byte Write Operation
• Block Write Protection – Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection
• Self-timed Write Cycle (5 ms max)
• High Reliability – Endurance: 1 Million Write Cycles – Data Retention: >100 Years
• 8-lead JEDEC SOIC and 8-lead TSSOP Packages

Description

The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and automotive applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT25128A/256A is enabled through the Chip Select pin (CS ) and accessed via a three-wire interface consisting of Serial Da ta Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate erase cycle is required before write. Table 1. Pin Configurations

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Figure 1. Block Diagram periods may affect device reliability.

Note: 1. This parameter is characterized and is not 100% tested.

1. V IL and VIH max are reference only and are not tested.

Table 2. Pin Capacitance(1) Table 3. DC Characteristics

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Note: 1. This parameter is ensured by characterization only. Table 4. AC Characteristics

5088F–SEEPR–2/07 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input , the AT25128A/256A always operates as a slave. TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the device is not selected, data will not be acce pted via the SI pin, and the SO pin will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128A/256A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register . If the internal write cycl e has already been initiated, WP going low will have no effect on any write operation to the stat us register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

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Figure 2. SPI Serial Interface

5088F–SEEPR–2/07 Functional The AT25128A/256A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128A/256A utilizes an 8-bit instruction register. Th e list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions mu st therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is indepen- dent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The Ready /Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the ext ent of protection employed. These bits are set by using the WRSR instruction. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128A/256A is divided into four array segments. Table 5. Instruction Set for the AT25128A/256A Table 6. Status Register Format Table 7. Read Status Register Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY ) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. indicates the device is write enabled. Bits 4–6 are “0”s when device is not in an internal write cycle. Bits 0–7 are “1”s during an internal write cycle.

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and corresponding status register control bits are shown in Table 8. tions as the regular memory cells (e.g., WREN, tWC, RDSR). are only allowed to sections of the memory that are not block-protected. is transmitted via the SI line followed by the byte address to be read (see Table 10). the lowest address, allowing the entire memory to be read in one continuous read cycle. Table 8. Block Write Protect Bits Table 9. WPEN Operation

0 X 0 Protected Protected Protected

0 X 1 Protected Writeable Writeable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writeable Protected

will be ignored except the RDSR instruction. ing the SCK low time immediately after clocking in the D0 (LSB) data bit. the completion of a write cycle. edge is required to reinitiate the serial communication. Table 10. Address Key

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Figure 3. Synchronous Data Timing Figure 4. WREN Timing Figure 5. WRDI Timing

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Figure 8. READ Timing Figure 9. WRITE Timing Figure 10. HOLD Timing

5088F–SEEPR–2/07 Ordering Code Package Operation Range AT25128AN-10SQ-2.7 AT25128A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low-voltage (2.7V to 5.5V)

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5088F–SEEPR–2/07 Ordering Code Package Operation Range AT25256AN-10SQ-2.7 AT25256A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low-voltage (2.7V to 5.5V)

5088F–SEEPR–2/07 Packaging Information 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

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5088F–SEEPR–2/07 8A2 – TSSOP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

5088F–SEEPR–2/07

Revision History

Doc. Rev. Date Comments 5088F 2/2007 Revision history implemented Removed PDIP package offering Removed Pb’d parts

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