Download PDFAT25128 ATMEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 12
Technical content
Features
- Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Low Voltage and Standard Voltage Operation 5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 1.8 (VCC = 1.8V to 3.6V)
- 2.1 MHz Clock Rate
- 32-Byte Page Mode
- Block Write Protection Protect 1/4, 1/2, or Entire Array
- Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
- Self-Timed Write Cycle (5 ms Typical)
- High Reliability Endurance: 100,000 Cycles Data Retention: 100 Years
- Automotive Grade and Extended Temperature Devices Available
- 8-Pin PDIP, 14-pin, 16-pin JEDEC SOIC, and 20-Pin TSSOP Packages
Description
The AT25128 provides 131,072 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 16,384 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT25128 is available in space saving 8-pin PDIP, JEDEC SOIC, and 14-pin and 20-pin TSSOP packages. (continued) Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground V CC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect DC Don’t Connect CS SO WP GND VCC HOLD SCK SI 8-Pin PDIP CS SO NC NC NC WP GND VCC HOLD NC NC NC SCK SI 14-Pin SOIC CS SO NC NC NC NC WP GND VCC HOLD NC NC NC NC SCK SI 16-Lead SOIC NC CS SO SO NC NC WP GND DC NC NC VCC HOLD HOLD NC NC SCK SI DC NC 20-Lead TSSOP*
*NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* The AT25128 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instruc- tions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial commu- nication without resetting the serial sequence. Description (Continued)
2 AT25128
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 3.6 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open 3.0 mA ICC2 Supply Current VCC = 5.0V at 2 MHz, SO = Open 5.0 mA ISB1 Standby Current V CC = 1.8V CS = VCC 0.1 µA ISB2 Standby Current V CC = 2.7V CS = VCC 0.2 0.5 µA ISB3 Standby Current V CC = 5.0V CS = VCC 0.5 2.0 µA IIL Input Leakage V IN = 0V to VCC -3.0 3.0 µA IOL Output Leakage VIN = 0V to VCC , TAC = 0°C to 70°C -3.0 3.0 µA VIL (1) Input Low Voltage -1.0 V CC x 0.3 V VIH (1) Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V VOH1 Output High Voltage I OH = -1.6 mA VCC - 0.8 V VOL2 Output Low Voltage1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V VOH2 Output High Voltage I OH = -100 µAV CC - 0.2 V Note: 1. VIL min and VIH max are reference only and are not tested. Pin Capacitance (1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions Max Units Conditions C OUT Output Capacitance (SO) 8 pF V OUT = 0V C IN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF V IN = 0V Note: 1. This parameter is characterized and is not 100% tested. AT25128
(continued) AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2.1 2.1 0.5 MHz tRI Input Rise Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 µs t FI Input Fall Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 µs t WH SCK High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 300 800 ns t WL SCK Low Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 200 800 ns tCS CS High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns tCSS CS Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns tCSH CS Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns tSU Data In Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 ns tH Data In Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 ns t HD Hold Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 400 ns t CD Hold Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 400 ns t V Output Valid 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 200 800 ns tHO Output Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 ns tLZ Hold to Output Low Z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 100 ns
4 AT25128
Symbol Parameter Voltage Min Max Units tHZ Hold to Output High Z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 100 ns tDIS Output Disable Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns tWC Write Cycle Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 ms AC Characteristics (Continued) AT25128
Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25128 always operates as a slave. TRANSMITTER/RECEIVER: The AT25128 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitial- ize the serial communication. CHIP SELECT: The AT25128 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin ( WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1", all write opera- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status reg- ister. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is ”0". This will allow the user to install the AT25128 in a system with the WP pin tied to ground and still be able to write to the status regis- ter. All WP pin functions are enabled when the WPEN bit is set to “1". SPI Serial Interface
6 AT25128
68HC11 series of microcontrollers. Table 1. All instructions, addresses, and data are trans- Table 1. Instruction Set for the AT25128 Register instruction provides access to the status register. Bits 4-6 are 0s when device is not in an internal write cycle. Bits 0-7 are 1s during an internal write cycle. tection. The AT25128 is divided into four array segments. control bits are shown in Table 3. Table 3. Block Write Protect Bits which are not block-protected.
Table 4. WPEN Operation
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
by the byte address to be read (A15-A0, Refer to Table 5). Upon completion, any data on the SI line will be ignored. AT25128, two separate instructions must be executed. mands will be ignored except the RDSR instruction. ately after clocking in the D0 (LSB) data bit. Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. disable state at the completion of a WRITE cycle. edge is required to re-initiate the serial communication. Table 5. Address Key
8 AT25128
Timing Diagrams (for SPI Mode 0 (0,0)) Synchronous Data Timing WRDI Timing WREN Timing AT25128
0123456789 1 0 1 1 1 2 1 3 1 4 SI INSTRUCTION SO 76543210 DATA OUT MSB HIGH IMPEDANCE RDSR Timing READ Timing
10 AT25128
tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package Operation Range 5 5000 2.0 2100 AT25128-10PC 8P3 Commercial AT25128-10SC 14S (0 °C to 70°C) AT25128N1-10SC 16S1 AT25640T2-10TC 20T 10 3000 0.5 2100 AT25128-10PC-2.7 8P3 Commercial AT25128-10SC-2.7 14S (0 °C to 70°C) AT25128N1-10SC-2.7 16S1 AT25128T2-10TC-2.7 20T 20 3000 0.2 500 AT25128-10PC-1.8 8P3 Commercial AT25128-10SC-1.8 14S (0 °C to 70°C) AT25128N1-10SC-1.8 16S1 AT25128T2-10TC-1.8 20T 5 5000 2.0 2100 AT25128-10PI 8P3 Industrial AT25128-10SI 14S (-40 °C to 85°C) AT25128N1-10SI 16S1 AT25128T2-10TI 20T 10 3000 0.5 2100 AT25128-10PI-2.7 8P3 Industrial AT25128-10SI-2.7 14S (-40 °C to 85°C) AT25128N1-10SI-2.7 16S1 AT25128T2-10TI-2.7 20T 20 3000 0.2 500 AT25128-10PI-1.8 8P3 Industrial AT25128-10SI-1.8 14S (-40 °C to 85°C) AT25128N1-10SI-1.8 16S1 AT25128T2-10TI-1.8 20T
Ordering Information
8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 14S 14-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 16S1 16-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 20T 20-Lead, 0.170" Wide, Thin Super Small Outline Package (TSSOP) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 3.6V)