Download PDFAT25080B_10 ATMEL
Document overview
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Technical content
Features
Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation – 1.8 (V CC = 1.8V to 5.5V) 20 MHz Clock Rate (5V) 32-byte Page Mode Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years Green (Pb/Halide-free/RoHS Compliant) Packaging Options Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
Description
The AT25080B/160B provides 8192/16384 bits of serial electrically-erasable program- mable read-only memory (EEPROM) organized as 1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25080B/160B is available in space-saving 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, 8-lead XDFN, and 8-ball VFBGA packages. The AT25080B/160B is enabled through the Chip Select pin ( CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate erase cycle is required before write. Table 0-1. Pin Configuration Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input VCC HOLD SCK SI CS SO WP GND 8-lead UDFN Bottom View CS SO WP GND 8-lead SOIC VCC HOLD SCK SI 8-lead TSSOP CS SO WP GND VCC HOLD SCK SI VCC HOLD SCK SI CS SO WP GND 8-ball VFBGA Bottom View VCC HOLD SCK SI CS SO WP GND 8-lead XDFN Bottom View SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8) AT25080B AT25160B 5228D–SEEPR–4/10
5228D–SEEPR–4/10 AT25080B/160B Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. 1. Absolute Maximum Ratings* Figure 1-1. Block Diagram “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin
5228D–SEEPR–4/10 AT25080B/160B Table 1-1. Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested. Table 1-2. DC Characteristics Notes: 1. V IL min and VIH max are reference only and are not tested. 2. Worst case measured at 85 C Applicable over recommended operating range from TA =2 5C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions Max Units Conditions COUT Output Capacitance (SO) 8 pF V OUT =0 V CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF V IN =0 V Applicable over recommended operating range from: TAI = –40Ct o+ 8 5C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current V CC = 5.0V at 20 MHz, SO = Open, Read 7.5 10.0 mA ICC2 Supply Current VCC = 5.0V at 20 MHz, SO = Open, Read, Write 4.0 10.0 mA ICC3 Supply Current VCC = 5.0V at 5 MHz, SO = Open, Read, Write 4.0 6.0 mA ISB1 Standby Current V CC = 1.8V, CS = VCC < 0.1 6.0 (2) µA ISB2 Standby Current V CC = 2.5V, CS = VCC 0.3 7.0 (2) µA ISB3 Standby Current V CC = 5.0V, CS = VCC 2.0 10.0 (2) µA IIL Input Leakage V IN =0 Vt oV CC –3.0 3.0 µA IOL Output Leakage V IN =0 Vt oV CC,T AC = 0°C to 70°C –3.0 3.0 µA VIL (1) Input Low-voltage –0.6 V CC x 0.3 V VIH (1) Input High-voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low-voltage 3.6V VCC 5.5V IOL = 3.0 mA 0.4 V VOH1 Output High-voltage I OH = 1.6 mA V CC - 0.8 V VOL2 Output Low-voltage 1.8V VCC 3.6V IOL = 0.15 mA 0.2 V VOH2 Output High-voltage I OH = 100 µA V CC - 0.2 V
5228D–SEEPR–4/10 AT25080B/160B Table 1-3. AC Characteristics Applicable over recommended operating range from TAI = –40Ct o+ 8 5C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5–5.5 2.5–5.5 1.8–5.5 MHz tRI Input Rise Time 4.5–5.5 2.5–5.5 1.8–5.5 µs tFI Input Fall Time 4.5–5.5 2.5–5.5 1.8–5.5 µs tWH SCK High Time 4.5–5.5 2.5–5.5 1.8–5.5 ns tWL SCK Low Time 4.5–5.5 2.5–5.5 1.8–5.5 ns tCS CS High Time 4.5–5.5 2.5–5.5 1.8–5.5 100 ns tCSS CS Setup Time 4.5–5.5 2.5–5.5 1.8–5.5 100 ns tCSH CS Hold Time 4.5–5.5 2.5–5.5 1.8–5.5 100 ns tSU Data In Setup Time 4.5–5.5 2.5–5.5 1.8–5.5 ns tH Data In Hold Time 4.5–5.5 2.5–5.5 1.8–5.5 ns tHD HOLD Setup Time 4.5–5.5 2.5–5.5 1.8–5.5 tCD HOLD Hold Time 4.5–5.5 2.5–5.5 1.8–5.5 ns tV Output Valid 4.5–5.5 2.5–5.5 1.8–5.5 ns tHO Output Hold Time 4.5–5.5 2.5–5.5 1.8–5.5 ns
5228D–SEEPR–4/10 AT25080B/160B Note: 1. This parameter is characterized and is not 100% tested. 2. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080B/160B always operates as a slave. TRANSMITTER/RECEIVER: The AT25080B/160B has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte con- tains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080B/160B, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25080B/160B is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080B/160B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the mas- ter device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin ( WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. TheWP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25080B/160B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. tLZ HOLD to Output Low Z 4.5–5.5 2.5–5.5 1.8–5.5 100 ns t HZ HOLD to Output High Z 4.5–5.5 2.5–5.5 1.8–5.5 200 ns t DIS Output Disable Time 4.5–5.5 2.5–5.5 1.8–5.5 200 ns t WC Write Cycle Time 4.5–5.5 2.5–5.5 1.8–5.5 ms Endurance (1) 3.3V, 25°C, Page Mode 1M Write Cycles Table 1-3. AC Characteristics (Continued) Applicable over recommended operating range from TAI = –40Ct o+ 8 5C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units
5228D–SEEPR–4/10 AT25080B/160B Figure 2-1. SPI Serial Interface AT25080B/160B
5228D–SEEPR–4/10 AT25080B/160B 3. Functional Description The AT25080B/160B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080B/160B utilizes an 8-bit instruction register. The list of instructions and their operation codes are con- tained in Table 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to- low CS transition. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All program- ming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 3-1. Instruction Set for the AT25080B/160B Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array Table 3-2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 3-3. Read Status Register Bit Definition Bit Definition B i t0(RDY) Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 (WEN) Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the device is write enabled. Bit 2 (BP0) See Table 3-4 on page 8. Bit 3 (BP1) See Table 3-4 on page 8. Bits 4–6 are “0”s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 3-5 on page 8. Bits 0–7 are “1”s during an internal write cycle.
5228D–SEEPR–4/10 AT25080B/160B WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec- tion. The AT25080B/160B is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 3-4. The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regu- lar memory cells (e.g., WREN, t WC, RDSR). The WRSR instruction also allows the user to enable or disable the write protect ( WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either theWP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory that are not block-protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low. READ SEQUENCE (READ): Reading the AT25080B/160B via the Serial Output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed by the byte address to be read (A15–A0, see Table 3-6). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, theCS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. Table 3-4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP1 BP0 AT25080B AT25160B 0 0 0 None None 1(1/4) 0 1 0300 03FF 0600 07FF 2(1/2) 1 0 0200 03FF 0400 07FF 3(All) 1 1 0000 03FF 0000 07FF Table 3-5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writeable Writeable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writeable Protected
X High 0 Protected Protected Protected X High 1 Protected Writeable Writeable
5228D–SEEPR–4/10 AT25080B/160B WRITE SEQUENCE (WRITE): In order to program the AT25080B/160B, two separate instructions must be exe- cuted. First, the device must be write enabled via the WREN instruction. Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15 –A0) and the data (D7 –D 0 )t ob ep r o - grammed (see Table 3-6). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a read status register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25080B/160B is capable of a 32-byte page write operation. After each byte of data is received, the five low- order address bits are internally incremented by one; the high-order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25080B/160B is automatically returned to the write disable state at the completion of a write cycle. Note: If the device is not write-enabled (WREN), the device will ignore the write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. Table 3-6. Address Key Address AT25080B AT25160B AN A9–A0 A10–A0 Don’t Care Bits A 15–A10 A15–A11
5228D–SEEPR–4/10 AT25080B/160B 5. Ordering Code Detail Atmel Designator Product Family Device Density Device Revision Shipping Carrier Option Operating Voltage 080 = 8-kilobit 160 = 16-kilobit B or blank = Bulk (tubes) T = Tape and reel L = 1.8V to 5.5V Packaged Device Grade or Wafer/Die Thickness Package Option H = Green, NiPdAu lead finish Temperature range -40°C to +85°C U = Green, matte Sn lead finish Temperature range -40°C to +85°C 11 = 11 mil wafer thickness SS = JEDEC SOIC X = TSSOP MA = UDFN ME = XDFN C = VFBGA WWU = Wafer unsawn WDT = Die in Tape and Reel AT25080B-SSHL-B
5228D–SEEPR–4/10 AT25080B/160B 6. Part Markings
6.1 AT25080B
| Seal Week | | | A T M L H Y W W 5 8 B L @ * LOT NUMBER PIN 1 INDICATOR (DOT) Top Mark Seal Year @ = Country of Ass’y Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 PIN 1 INDICATOR (DOT) A T H Y W W 5 8 B L @ ATMEL LOT NUMBER Top Mark @ = Country of Ass’y Y = SEAL YEAR 8: 2008 2: 2012 9: 2009 3: 2013 0: 2010 4: 2014 1: 2011 5: 2015 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 |---|---|---| 5 8 B |---|---|---| H L @ |---|---|---| Y X X |---|---|---| PIN 1 INDICATOR (DOT) Top Mark Y = YEAR OF ASSEMBLY @ = Country of Ass’y XX= ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013
5228D–SEEPR–4/10 AT25080B/160B AT25080B-MEHL AT25080B-CUL |---|---|---| 5 8 B |---|---|---| Y X X |---|---|---| PIN 1 INDICATOR (DOT) Top Mark Y = YEAR OF ASSEMBLY XX= ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013 5 8 B U B Y M X X * <-- PIN 1 INDICATOR Top Mark B = Country of Origin Y = One Digit Year Code M = One Digit Month Code XX= TRACE CODE (ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK) Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009 M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY J = OCTOBER K = NOVEMBER L = DECEMBER
5228D–SEEPR–4/10 AT25080B/160B
6.2 AT25160B
| Seal Week | | | A T M L H Y W W
5 A B L @
- LOT NUMBER PIN 1 INDICATOR (DOT) Top Mark Seal Year @ = Country of Ass’y Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 PIN 1 INDICATOR (DOT) A T H Y W W
@ = Country of Ass’y Y = SEAL YEAR 8: 2008 2: 2012 9: 2009 3: 2013 0: 2010 4: 2014 1: 2011 5: 2015 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 |---|---|---|
5 A B
|---|---|---| H L @ |---|---|---| Y X X |---|---|---| PIN 1 INDICATOR (DOT) Top Mark Y = YEAR OF ASSEMBLY @ = Country of Ass’y XX= ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013
5228D–SEEPR–4/10 AT25080B/160B AT25160B-MEHL AT25160B-CUL |---|---|---| |---|---|---| Y X X |---|---|---| PIN 1 INDICATOR (DOT) Top Mark Y = YEAR OF ASSEMBLY XX= ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013
5 A B U
- <-- PIN 1 INDICATOR Top Mark B = Country of Origin Y = One Digit Year Code M = One Digit Month Code XX= TRACE CODE (ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK) Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009 M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY J = OCTOBER K = NOVEMBER L = DECEMBER
5228D–SEEPR–4/10 AT25080B/160B 7. Ordering Codes Note: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube). 2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel). 3. Contact Atmel Sales for Wafer sales. Ordering Code Voltage Package Operation Range AT25080B-SSHL-B (1) (NiPdAu Lead Finish) AT25080B-SSHL-T(2) (NiPdAu Lead Finish) AT25080B-XHL-B(1) (NiPdAu Lead Finish) AT25080B-XHL-T(2) (NiPdAu Lead Finish) AT25080B-MAHL-T(2) (NiPdAu Lead Finish) AT25080B-MEHL-T(2) (NiPdAu Lead Finish) AT25080B-CUL-T(2) (SnAgCu Ball Finish) 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 8S1 8S1 8A2 8A2 8MA2 8ME1 8U3-1 Lead-free/Halogen-free/ Industrial Temperature (40 to 85C) AT25080B-WWU11L (3) 1.8V to 5.5V Die Sale Industrial Temperature (40 to 85C) Package Type 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8MA2 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin, Dual No Lead Package (UDFN) 8ME1 8-lead (1.80 mm x 2.20 mm Body) Extra Thin DFN (XDFN) 8U3-1 8-ball, die Ball Grid Array Package (VFBGA)
5228D–SEEPR–4/10 AT25080B/160B Note: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube). 2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel). 3. Contact Atmel Sales for Wafer sales. Ordering Code Voltage Package Operation Range AT25160B-SSHL-B (1) (NiPdAu Lead Finish) AT25160B-SSHL-T(2) (NiPdAu Lead Finish) AT25160B-XHL-B(1) (NiPdAu Lead Finish) AT25160B-XHL-T(2) (NiPdAu Lead Finish) AT25160B-MAHL-T(2) (NiPdAu Lead Finish) AT25160B-MEHL-T(2) (NiPdAu Lead Finish) AT25160B-CUL-T(2) (SnAgCu Ball Finish) 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 8S1 8S1 8A2 8A2 8MA2 8ME1 8U3-1 Lead-free/Halogen-free/ Industrial Temperature (40 to 85C) AT25160B-WWU11L (3) 1.8V to 5.5V Die Sale Industrial Temperature (40 to 85C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8MA2 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin, Dual No Lead Package (UDFN) 8ME1 8-lead (1.80 mm x 2.20 mm Body) Extra Thin DFN (XDFN) 8U3-1 8-ball, die Ball Grid Array Package (VFBGA)
5228D–SEEPR–4/10 AT25080B/160B 8. Packaging Information 8S1 – JEDEC SOIC Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV. TITLE GPC 8S1 E 12/11/09 8S1, 8-lead, (0.150” Wide Body), Plastic Gull Wing Outline (JEDEC SOIC) SWB
1.27 BSC
1.75 0.25 0.51 0.25 5.05 3.99 6.20 1.27 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1.35 0.10 0.31 0.17 4.80 3.81 5.79 0.40 A b C D E e L θ Notes: 1. These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. E 1234 8765 GND NC NC NC SDA SCL NC V CC Ø C L A b e D End ViewTop View Side View
5228D–SEEPR–4/10 AT25080B/160B 8A2 – TSSOP COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV. TITLE GPC 8A2 D 12/11/09 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2, 8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) TNR 2.90 4.30 0.80 0.19 0.45 D E A b e L 3.00
6.40 BSC
4.40 1.00
0.65 BSC
0.60
1.00 RE3
13.10 4.50 1.20 1.05 0.30 0.75 2, 5 3, 5 End ViewTop View L 1234 Pin 1 indicator this corner E GND NC NC NC 8765 SDA SCL NC V CC Side View A D b e
5228D–SEEPR–4/10 AT25080B/160B 8MA2 - UDFN COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV. TITLE GPC 8MA2 A 4/15/08 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229 for proper dimensions, tolerances, datums, etc. 2. The terminal #1 ID is a laser-marked feature. 3. Dimensions b applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) YNZ 1.40 1.20 0.50 0.00 0.30 0.18 0.20 D E A C L e b K
2.00 BSC
3.00 BSC
1.50 1.30 0.55 0.02
0.152 REF
0.35
0.50 BSC
0.25 1.60 1.40 0.60 0.05 0.55 0.40 0.30 C E A Pin 1 ID D e (6x) L (8x) b (8x) Pin#1 ID (R0.10) 0.35 K
5228D–SEEPR–4/10 AT25080B/160B 8ME1 - XDFN COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV. TITLE GPC 8ME1 A 8/3/09 8ME1, 8-lead (1.80 x 2.20 mm Body) Extra Thin DFN (XDFN) DTP 0.00 1.70 2.10 0.15 0.26 A D E b e L 1.80 2.20 0.20
0.40 TYP
1.20 REF
0.30 0.40 0.05 1.90 2.30 0.25 0.35 Bottom ViewTop View Side View 8 7 6 5 1 2 3 4 D E PIN #1 ID A PIN #1 ID b L e b 0.10 0.15
5228D–SEEPR–4/10 AT25080B/160B 8U3-1 - VFBGA COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Package Drawing Contact: packagedrawings@atmel.com DRAWING NO. REV. TITLE PO8U3-1 C 9/19/07 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, 0.73 0.09 0.40 0.20 A b D E e d 0.79 0.14 0.45 0.25
1.50 BSC
0.25 REF
1.00 BSC
0.85 0.19 0.50 0.30 2 Top View End View Notes: 1. This drawing is for general information only. 2. Dimension ‘b’ is measured at maximum solder ball diameter. 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu E D PIN 1 BALL PAD CORNER b1. A 8 7 6 5 1 2 3 4 Bottom View (8 SOLDER BALLS) PIN 1 BALL PAD CORNER (d1) d (e1) e
5228D–SEEPR–4/10 AT25080B/160B 9. Revision History Doc. Rev. Date Comments 5228D 4/2010 Update Ordering Code Detail and Ordering Information 5228C 8/2009 Change Catalog Scheme Add Marking Details 5228B 7/2008 Change ‘Endurance’ parameter on page 6 5228A 9/2007 Initial document release
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