ASDMP-2D ABRACON

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 1

Technical content

0.028 0.70 0.026 0.65 0.033 0.85 0.028 0.70 0.03 0.65 0.015 0.375 0.033 0.85 0.033 ±0.002 0.85 ±0.05 0.098 ±0.002 2.50 ±0.05 0.079 ±0.002 2 ±0.05 456 1 2 3 0.9[.035] REF 0.028 ±0.004 0.7 ±0.10 0.004 0.1 REF 0.026 ±0.00 0.65 ±0 0.010 ±0.005 0.25 ±0.13 0.032 0.825 4 5 6 13 2 Recommended Land Pattern FOR LVPECL,LVDS,HCSL NOTE: Recommended using approximately 0.01uf bypass capacitor between PIN 6 and 3 Via to Power LayerVia to GND Layer Recommended Land Pattern FOR CMOS Via to Power Layer Via to GND Layer 1 2 Pin Function

1 Tri-state

3 GND

4 Output

5 NC (CMOS) Output

(LVPECL, LVDS, HCSL)

6 Vdd

WEIGHT: SHEET 1 OF 1SCALE:10:1 DWG NO. TITLE: REVISIONDO NOT SCALE DRAWING MATERIAL: DATESIGNATURENAME DEBUR AND BREAK SHARP EDGES FINISH:UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCH(MM) SURFACE FINISH: TOLERANCES: LINEAR: ANGULAR: Q.A MFG APPV'D CHK'D DRAWN

30332 Esperanza, Rancho Santa margarita, California 92688

VOLTAGE CONTROLLED TEMP. COMPENSATED SMD CRYSTAL OSCILLATOR