AS6C4016

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Fast access time :55ns Low power consumption: Operating current:30mA (TYP .) Standby current : 4A (TYP .) LL-version Single 2.7V~5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage :1.5V(MIN.) Lead free and green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA GENERAL DESCRIPTION The is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The operates fromasi ngle power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTLcompatible PRODUCT FAMILY Power DissipationProduct Family Operating Temperature Vcc Range Speed Standby(ISB1,TYP .) Operating(Icc,TYP .) (I) -40 ~ 85 2.7 ~ 5.5V 55ns 4µA(LL) 30mA FUNCTIONAL BLOCK DIAGRAM TO O R T I O V OU OO U R L W W L AA C C R YY2 c/2 C C M 7 2 c/2 T O R T R PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A17 Address Inputs DQ0 – DQ15 Data Inputs/Outputs CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower ByteControl UB# Upper Byte Control VCC Power Supply VSS Ground 512KX8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 1 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

CE# WE# LB# UB# OE# T C C C LAA C LW W LW W C LAA C C CR C C C C C C C C ABSOLUTE MAXIMUN RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1 -0.5 to 6.5 V Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V Operating Temperature TA -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 mA Soldering Temperature (under 10 sec) TSOLDER 260 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. 512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 2 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

I/O OPERATIONMODE CE# OE# WE# LB# UB# DQ0-DQ7 DQ8-DQ15 SUPPLY CURRENT Standby H X X X X X X H X H High–Z High–Z High–Z High–Z I SB1 Output Disable L L H H H H L X X L High–Z High–Z High–Z High–Z I CC,ICC1 Read L L L L L L H H H L H L H L L D OUT High–Z DOUT High–Z DOUT DOUT ICC,ICC1 Write L L L X X X L L L L H L H L L D IN High–Z DIN High–Z DIN DIN ICC,ICC1 Note: H = V IH, L = VIL, X = Don't care. DC ELECTRICALCHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. *3 MAX. UNIT Supply Voltage VCC 2.7 3.0 5.5 V Input High Voltage V IH Input Low Voltage V IL *1 - 0.2 - 0.6 V Input Leakage Current I LI VCC VIN VSS - 1 - 1 µA Output Leakage Current ILO VCC VOUT VSS Output Disabled - 1 - 1 µA Output High Voltage V OH IOH = -1mA 2.4 - - V Output Low Voltage V OL IOL = 2mA - - 0.4 V - 55 - 30 60 mAICC Cycle time = Min. CE# = VIL, II/O = 0mA Other pins at VIL or VIH Average Operating Power supply Current ICC1 Cycle time = 1µs CE# 0.2V, II/O = 0mA Other pins at 0.2V or VCC-0.2V - 4 10 mA Standby Power Supply Current ISB1 CE# V CC-0.2V Others at 0.2V or VCC-0.2V LLI - 4 50 *4 µA Notes: 2. Over/Undershoot specifications are characterized, not 100% tested. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25 4. 25µA for special request CAPACITANCE (TA = 25 , f= 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note : These parameters are guaranteed by device characterization, but not production tested. 512KX8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 3 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

Input Pulse Levels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICALCHARACTERISTICS (1)READ CYCLE AS6C4016-55PARAMETER SYM. MIN. MAX. UNIT Read Cycle Time tRC 55 - ns Address Access Time tAA - 55 ns Chip Enable Access Time tACE - 55 ns Output Enable Access Time t OE - 30 ns Chip Enable to Output in Low-Z t CLZ* 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - ns Chip Disable to Output in High-Z t CHZ* - 20 ns Output Disable to Output in High-Z tOHZ* - 20 ns Output Hold from Address Change tOH 10 - ns LB#, UB# Access Time tBA - 55 ns LB#, UB# to High-Z Output t BHZ* - 25 ns LB#, UB# to Low-Z Output tBLZ* 10 - ns (2)WRITECYCLE AS6C4016-55PARAMETER SYM. MIN. MAX. UNIT Write Cycle Time tWC 55 - ns Address Valid to End of Write t AW 50 - ns Chip Enable to End of Write t CW 50 - ns Address Set-up Time tAS 0 - ns Write Pulse Width tWP 45 - ns Write Recovery Time tWR 0 - ns Data to Write Time Overlap t DW 25 - ns Data Hold from End of Write Time tDH 0 - ns Output Active from End of Write t OW* 5 - ns Write to Output in High-Z tWHZ* - 20 ns LB#, UB# Valid to End of Write t BW 45 - ns *These parameters are guaranteed by device characterization, but not production tested. 512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 4 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

READ CYCLE1(Address Controlled) (1,2) READ CYCLE2(CE# and OE# Controlled) (1,3,4,5) Dout Data Valid High-ZHigh-Z tCLZ tOLZ tCHZ tOHZ tOH OE# tOE LB#,UB# tBHZ tACE CE# tAA Address tRC tBA tBLZ Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. 512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 5 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

WRITECYCLE1 (WE#Controlled)(1,2,3,5,6) WRITECYCLE2 (CE#Controlled)(1,2,5,6) 512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 6 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

WRITECYCLE3 (LB#,UB# Controlled) (1,2,5,6) Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.t OW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 7 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention V DR CE# V CC - 0.2V 1.5 -5.5 V Data Retention Current I DR VCC = 1.5V, CE# V CC-0.2V Others at 0.2V or VCC-0.2V LLI - 2 30 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1)(CE# controlled) Vcc CE# VDR 1.5V CE# V cc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) Low Vcc Data Retention Waveform (2)(LB#, UB# controlled) Vcc LB#,UB# VDR 1.5V LB#,UB # V cc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) 512KX8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 8 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

44-pin400milTSOP- PackageOutlineDimension b 0.30 - 0.45 11.8 - 17.7 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473 E1 9.957 10.160 10.363 392 400 408 y - - 0.076 - - 3 0o 3o 6o 0o 3o 6o 512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 9 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

48-ball6mm 8mmTFBGAPackageOutlineDimension 512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 10 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM

512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 11 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM Alliance Organization VCC Range Package Operating Temp Speed ns AS6C4016-55ZIN 256K x 16 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 C - 85 C 55 AS6C4016-55BIN 256K x 16 2.7 - 5.5V 48ball TFBGA Industrial ~ -40 C - 85 C 55 Part Numbering System AS6C 4016 -55 X X N Device Number Package Option Temperature Range 40 = 4M 44pin TSOP II I = Industriallow power S RAM prefix 16 =x16 Access Ti me 48 ball TFBGA (-40 to + 85 C) N = Lead Free Ro HS compliant part

512K X 8 BIT LOW POWER CMOS SRAM January 2007MARCH 2008 MARCH/2008, V 1.0 Alliance Memory Inc. Page 12 of 12 AS6C4016 256K X 16 BIT SUPER LOW POWER CMOS SRAM Copyright © Alliance Memory All Rights Reserved Alliance Memory, Inc

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