AS6C1016

AS6C1016 ETC2

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Technical content

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 0

REVISION HISTORY

Revision Description Issue Date Rev. 1.0 Initial Issue Nov.19.2008 Rev. 1.1 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Revised PACKAGE OUTLINE DIMENSION in page 11 Revised VDR to 1.5V May.6.2010 Rev. 1.2 Revised ORDERING INFORMATION in page 12 Aug.30.2010 Rev. 1.3 Revised typo in PRODUCT FAMILY page 1 Oct.4.2010 Rev. 1.4 Deleted E Grade Aug.9.2011

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 1

FEATURES

 Fast access time : 55ns  Low power consumption: Operating current : 20mA (TYP.) Standby current : 2A (TYP.)  Single 2.7V ~ 5.5V power supply  All outputs TTL compatible  Fully static operation  Tri-state output  Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15)  Data retention voltage : 1.5V (MIN.)  Green package available  Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA GENERAL DESCRIPTION The AS6C1016 is a 1,048,576-bit low power CMOS static random access memory organized as 65,536 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C1016 is well designed for low power application, and particularly well suited for bat tery back-up nonvolatile memory application. The AS6C1016 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed Power Dissipation Standby(ISB1,TYP .) Operating(Icc,TYP .) AS6C1016(I) -40 ~ 85℃ 2.7 ~ 5.5V 55/70ns 2µA 20/18mA FUNCTIONAL BLOCK DIAGRAM CONTROL CIRCUIT CE# WE# OE# DECODER 64Kx16 MEMORY ARRAY COLUMN I/O A0-A15 Vcc Vss DQ8-DQ15 Upper Byte DQ0-DQ7 Lower Byte I/O DATA CIRCUIT LB# UB# PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A15 Address Inputs DQ0 – DQ15 Data Inputs/Outputs CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 2 PIN CONFIGURATION AS6C1016 DQ15DQ0 DQ1 DQ2 Vcc Vss NC A15 DQ14 DQ12 DQ13 DQ11 Vss Vcc DQ10 DQ9 DQ3 DQ4 TSOP II 22 23 A14 DQ6 DQ7 DQ5 DQ8 A13 A12 NC A10 NC A11 CE# WE# LB# UB# OE# TFBGA NC A10A9 A11 A14 A8 NC WE# DQ9 DQ14 DQ15 NC Vss NC A13 DQ8 Vcc Vcc DQ7 A15 Vss CE# LB# DQ6 DQ2 DQ0 A2OE# A1 A6A5 A4UB# 1 2 3 4 5 6 H G C D E F A B A12 NC NC A7 NC DQ10 DQ11 DQ12 DQ13 DQ5 DQ4 DQ3 DQ1 ABSOLUTE MAXIMUN RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1 -0.5 to 6.5 V Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V Operating Temperature TA -40 to 85(I grade) ℃ Storage Temperature TSTG -65 to 150 ℃ Power Dissipation PD 1 W DC Output Current IOUT 50 mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 3 TRUTH TABLE MODE CE# OE# WE# LB# UB# I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 Standby H X X X X X X H X H High – Z High – Z High – Z High – Z ISB1 Output Disable L L H H H H L X X L High – Z High – Z High – Z High – Z ICC,ICC1 Read L L L L L L H H H L H L H L L DOUT High – Z DOUT High – Z DOUT DOUT ICC,ICC1 Write L L L X X X L L L L H L H L L DIN High – Z DIN High – Z DIN DIN ICC,ICC1 Note: H = V IH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . *4 MAX. UNIT Supply Voltage VCC 2.7 3.0 5.5 V Input High Voltage VIH *1 2.4 - VCC+0.3 V Input Low Voltage VIL *2 - 0.2 - 0.6 V Input Leakage Current ILI VCC ≧ VIN ≧ VSS - 1 - 1 µA Output Leakage Current ILO VCC ≧ VOUT ≧ VSS, Output Disabled - 1 - 1 µA Output High Voltage VOH IOH = -1mA 2.4 2.7 - V Output Low Voltage VOL IOL = 2mA - - 0.4 V Average Operating Power supply Current ICC Cycle time = Min. CE# = VIL , II/O = 0mA Other pins at VIL or VIH - 55 - 20 60 mA ICC1 Cycle time = 1µs CE# = 0.2V , II/O = 0mA Other pins at 0.2V or VCC - 0.2V - 4 10 mA Standby Power Supply Current ISB1 CE# ≧VCC - 0.2V Others at 0.2V or VCC - 0.2V LL/LLI - 2 50 µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 4 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. AS6C1016-55 UNIT MIN. MAX. Read Cycle Time tRC 55 - ns Address Access Time tAA - 55 ns Chip Enable Access Time tACE - 55 ns Output Enable Access Time tOE - 30 ns Chip Enable to Output in Low-Z tCLZ* 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - ns Chip Disable to Output in High-Z tCHZ* - 20 ns Output Disable to Output in High-Z tOHZ* - 20 ns Output Hold from Address Change tOH 10 - ns LB#, UB# Access Time tBA - 55 ns LB#, UB# to High-Z Output tBHZ* - 25 ns LB#, UB# to Low-Z Output tBLZ* 10 - ns (2) WRITE CYCLE PARAMETER SYM. AS6C1016-55 UNIT MIN. MAX. Write Cycle Time tWC 55 - ns Address Valid to End of Write tAW 50 - ns Chip Enable to End of Write tCW 50 - ns Address Set-up Time tAS 0 - ns Write Pulse Width tWP 45 - ns Write Recovery Time tWR 0 - ns Data to Write Time Overlap tDW 25 - ns Data Hold from End of Write Time tDH 0 - ns Output Active from End of Write tOW* 5 - ns Write to Output in High-Z tWHZ* - 20 ns LB#, UB# Valid to End of Write tBW 50 - ns *These parameters are guaranteed by device characterization, but not production tested.

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 5 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) Dout Data Valid tOHtAA Address tRC Previous Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) Dout Data Valid High-ZHigh-Z tCLZ tOLZ tCHZ tOHZ tOH OE# tOE LB#,UB# tBHZ tACE CE# tAA Address tRC tBA tBLZ Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 6 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW tWRtAS (4) TOW LB#,UB# CE# tAW Address tWC tBW WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCW CE# Address tWRtAS tAW tWC tWP tBW

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 7 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCW CE# Address tWR tAS tAW tWC tWP tBW Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 8 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . MAX. UNIT VCC for Data Retention VDR CE# ≧ VCC - 0.2V 1.5 - 5.5 V Data Retention Current IDR VCC = 1.5V CE# ≧ VCC - 0.2V Others at 0.2V or VCC-0.2V LL/LLI - 0.5 20 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) Vcc CE# VDR ¡Ù 1.5V CE# ¡Ù Vcc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) Low Vcc Data Retention Waveform (2) (LB#, UB# controlled) Vcc LB#,UB# VDR ¡Ù 1.5V LB#,UB# ¡Ù Vcc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.)

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 9 PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension θ SYMBOLS DIMENSIONS IN MILLMETERS DIMENSIONS IN MILS b 0.30 - 0.45 11.8 - 17.7 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473 E1 9.957 10.160 10.363 392 400 408 y - - 0.076 - - 3 Θ 0o 3o 6o 0o 3o 6o

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 10 48-ball 6mm × 8mm TFBGA Package Outline Dimension

64K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc. Rev. 1.4 11

ORDERING INFORMATION

Alliance Organization VCC Range Package Operating Temp Speed ns AS6C1016-55ZIN 64K x 16 2.7V – 5.5V 44pin TSOP II Industrial ~ -40°C - 85°C 55 AS6C1016-55BIN 64K x 16 2.7V – 5.5V 48ball TFBGA Industrial - -40°C - 85°C 55 PART NUMBERING SYSTEM AS6C 1016 -55 X X N Low power SRAM prefix Device Number 10 = 1M 16 = x16 Access Time Package Options: T = 44 pin TSOP II B = 48 ball TFBGA Temperature Range: I = Industrial (-40°C to +85°C) N = Lead Free ROHS Compliant Part

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