AS3842

AS384X ETC

Document overview

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Technical content

Features

¥ 2.5 V bandgap reference trimmed to 1.0% and temperature-compensated ¥ Standard temperature range extended to 105¡C ¥ AS3842/3 oscillations trimmed for precision duty cycle clamp ¥ AS3844/5 have exact 50% max duty cycle clamp ¥ Advanced oscillator design simplifies synchronization ¥ Improved specs on UVLO and hysteresis provide more predictable start-up and shutdown ¥ Improved 5 V regulator provides better AC noise immunity ¥ Guaranteed performance with current sense pulled below ground

Description

The AS3842 family of control ICs provide pin-for-pin replacement of the industry standard UC3842 series of devices. The devices are redesigned to provide significantly improved tolerances in power sup- ply manufacturing. The 2.5 V reference has been trimmed to 1.0% tolerance. The oscillator discharge current is trimmed to provide guar- anteed duty cycle clamping rather than specified discharge current. The circuit is more completely specified to guarantee all parameters impacting power supply manufacturing tolerances. In addition, the oscillator and flip-flop sections have been enhanced to provide additional performance. The R T/CT pin now doubles as a syn- chronization input that can be easily driven from open collector/open drain logic outputs. This sync input is a high impedance input and can easily be used for externally clocked systems. The new flip-flop topol- ogy allows the duty cycle on the AS3844/5 to be guaranteed between 49 and 50%. The AS3843/5 requires less than 0.5 mA of start-up cur- rent over the full temperature range. SEMICONDUCTOR Pin Configuration Ñ Top view 14L SOIC (D14)8L SOIC (D8) VREG VCC OUT GND COMP VFB ISENSE RT/CT VREG NC V CC VC COMP NC VFB OUT PWR G GND I SENSE NC RT/CT NC PDIP (N) VREG VCC OUT GND COMP V FB ISENSE RT/CT Circuit Type: Current Mode Controller (See Table A) Package Style D8 = D14 = N = Pin Plastic SOIC Pin Plastic SOIC Pin Plastic DIP AS384X D8 13 Packaging Option: T = Tube = Tape and Reel (13" Reel Dia)

Ordering Information

Model V CC(min) VCC(on) Typ. I CC AS3842 10 16 97% 0.5 mA AS3843 7.6 8.4 97% 0.3 mA AS3844 10 16 49.5% 0.5 mA AS3845 7.6 8.4 49.5% 0.3 mA

Figure 1. Block Diagram of the AS3842/3/4/5 Sense this information to terminate the gate drive of the output.

4 RT/CT Oscillator frequency and maximum output duty cycle are set by connecting a resistor

accomplish a synchronization function. 5 GND Circuit common ground, power ground, and IC substrate. 7 VCC Positive supply voltage for the IC.

8 VREG This 5 V regulated output provides charging current for the capacitor C T through the

AS384xCurrent Mode Controller Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage (ICC < 30 mA) VCC Self-Limiting V Supply Voltage (Low Impedance Source) VCC 30 V Output Current IOUT ±1 A Output Energy (Capacitive Load) 5 µJ Analog Inputs (Pin 2, Pin 3) Ð0.3 to 30 V Error Amp Sink Current 10 mA Maximum Power Dissipation PD 8L SOIC 750 mW 8L PDIP 1000 mW 14L SOIC 950 mW Maximum Junction Temperature TJ 150 ¡C Operating Temperature 0 to 150 ¡C Storage Temperature Range TSTG Ð65 to 150 ¡C Lead Temperature, Soldering 10 Seconds TL 300 ¡C Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above indicated in the operational s ections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may af fect reliability. Recommended Conditions Parameter Symbol Rating Unit Supply Voltage VCC AS3842,4 15 V AS3843,5 10 V Oscillator fOSC 50 to 500 kHz Typical Thermal Resistances Package qJA qJC Typical Derating 8L PDIP 95¡C/W 50¡C/W 10.5 mW/¡C 8L SOIC 175¡C/W 45¡C/W 5.7 mW/¡C 14L SOIC 130¡C/W 35¡C/W 7.7 mW/¡C

AS384x Current Mode Controller

Electrical Characteristics

Electrical characteristics are guaranteed over full junction temperature range (0 to 105 ¡C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, RT = 10 k½, and CT = 3.3 nF, unless otherwise stated. To override UVLO, VCC should be raised above 17 V prior to test. Parameter Symbol Test Condition Min. Typ. Max. Unit

5 V Regulator

Output Voltage VREG TJ = 25¡C, IREG = 1 mA 4.95 5.00 5.05 V Line Regulation PSRR 12 ² VCC ² 25 V 2 10 mV Load Regulation 1 ² IREG ² 20 mA 2 10 mV Temperature Stability1 TCREG 0.2 0.4 mV/¡C Total Output Variation1 Line, load, temperature 4.85 5.15 V Long-term Stability1 Over 1,000 hrs at 25¡C 5 25 mV Output Noise Voltage VNOISE 10 Hz ² f ² 100 kHz, TJ = 25¡C 50 µV Short Circuit Current ISC 30 100 180 mA

2.5 V Internal Reference

Nominal Voltage VFB T = 25¡C; IREG = 1 mA 2.475 2.500 2.525 V Line Regulation PSRR 12 V ² VCC ² 25 V 2 5 mV Load Regulation 1 ² IREG ² 20 mA 2 5 mV Temperature Stability1 TCVFB 0.1 0.2 mV/¡C Total Output Variation1 Line, load, temperature 2.450 2.500 2.550 V Long-term Stability1 Over 1,000 hrs at 125¡C 2 12 mV Oscillator Initial Accuracy fOSC TJ = 25¡C 47 52 57 kHz Voltage Stability 12 V ² VCC ² 25 V 0.2 1 % Temperature Stability1 TCf TMIN ² TJ ² TMAX 5 % Amplitude fOSC VRT/CT peak-to-peak 1.6 V Upper Trip Point VH 2.9 V Lower Trip Point VL 1.3 V Sync Threshold VSYNC 400 600 800 mV Discharge Current ID 7.5 8.7 9.5 mA Duty Cycle Limit RT = 680 ½, CT = 5.3 nF, TJ = 25¡C 46 50 52 %

AS384xCurrent Mode Controller Electrical Characteristics (contÕd) Electrical characteristics are guaranteed over full junction temperature range (0 to 105 ¡C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, RT = 10 k½, and CT = 3.3 nF, unless otherwise stated. To override UVLO, VCC should be raised above 17 V prior to test. Parameter Symbol Test Condition Min. Typ. Max. Unit Error Amplifier Input Voltage VFB TJ = 25¡C 2.475 2.500 2.525 V Input Bias Current IBIAS Ð0.1 Ð1 µA Voltage Gain AVOL 2 ² VCOMP ² 4 V 65 90 1 dB Transconductance Gm 1 mA/mV Unity Gain Bandwidth1 GBW 0.8 1.2 MHz Power Supply Rejection Ratio PSRR 12 ² VCC ² 25 V 60 70 dB Output Sink Current ICOMPL VFB = 2.7 V, VCOMP = 1.1 V 2 6 mA Output Source Current ICOMPH VFB = 2.3 V, VCOMP = 5 V 0.5 0.8 mA Output Swing High VCOMPH VFB = 2.3 V, RL = 15 k½ to Ground 5 5.5 V Output Swing Low VCOMPL VFB = 2.7 V, RL = 15 k½ to Pin 8 0.7 1.1 V Current Sense Comparator ISENSE Level Shift2 VLS VSENSE = 0 V 1.5 V Maximum Input Signal2 VCOMP = 5 V 0.9 1 1.1 V Power Supply Rejection Ratio PSRR 12 ² VCC ² 25 V 70 dB Input Bias Current IBIAS Ð1 Ð10 µA Propagation Delay to Output1 tPD 85 150 ns Output Output Low Level VOL ISINK = 20 mA 0.1 0.4 V VOL ISINK = 200 mA 1.5 2.2 V Output High Level VOH ISOURCE = 20 mA 13 13.5 V VOH ISOURCE = 200 mA 12 13.5 V Rise Time1 tR CL = 1 nF 50 150 ns Fall Time1 tF CL = 1 nF 50 150 ns Housekeeping Start-up Threshold VCC(on) 3842/4 15 16 17 V 3843/5 7.8 8.4 9.0 V Minimum Operating Voltage VCC(min) 3842/4 9 10 11 V After Turn On 3843/5 7.0 7.6 8.2 V Output Low Level in UV State VOUV ISINK = 20 mA, VCC = 6 V 1.5 2.0 V Over-Temperature Shutdown4 TOT 125 ¡C

AS384x Current Mode Controller Electrical Characteristics (contÕd) Electrical characteristics are guaranteed over full junction temperature range (0 to 105 ¡C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, RT = 10 k½, and CT = 3.3 nF, unless otherwise stated. To override UVLO, VCC should be raised above 17 V prior to test. Parameter Symbol Test Condition Min. Typ. Max. Unit PWM Maximum Duty Cycle Dmax 3842/3 94 97 100 % Minimum Duty Cycle Dmin 3842/3 0 % Maximum Duty Cycle Dmax 3844/5 49 49.5 50 % Minimum Duty Cycle Dmin 3844/5 0 % Supply Current Start-up Current ICC 3842/4, VFB = VSENSE = 0 V, VCC = 14 V 0.5 1.0 mA 3843/5, VFB = VSENSE = 0 V, VCC = 7 V 0.3 0.5 mA Operating Supply Current ICC 9 17 mA VCC Zener Voltage VZ ICC = 25 mA 30 V Notes: 1. This parameter is not 100% tested in production. 2. Parameter measured at trip point of PWM latch. 3. Transfer gain is the relationship between current sense input and corresponding error amplifier output at the PWM latch trip poi nt and is mathematically expressed as follows: 4. At the over-temperature threshold, T OT, the oscillator is disabled. The 5 V reference and the PWM stages, including the PWM latch, remain powered. = ÐA I V VCOMP SENSE ≤ ≤Δ Δ ; 0.2 V 0.8SENSE

AS384x Current Mode Controller Typical Performance Curves Figure 6 Figure 8 Figure 7 Figure 9 0 20 40 60 80 100 120 140 ISC – Regulator Source Current (mA) –12 –16 –20 –24 Regulator Load Regulation ΔVREG – Regulator Voltage Change (mV) 150°C 25°C –55°C 0.3 1 RT – Timing Register (kΩ ) 3 10 100Maximum Duty Cycle (%) Maximum Duty Cycle vs Timing Resistor 10 100 1 M 100

0.1 CT – Timing Capacitor (nF)

Timing Capacitor vs Oscillator Frequency FOSC – Oscillator Frequency (kHz) RT = 680 Ω RT = 1 kΩ RT = 2.2 kΩ RT = 4.7 kΩ RT = 10 kΩ TA – Ambient Temperature (°C) –55 –35 –15 5 25 45 65 85 105 125 100 Maximum Duty Cycle (%) Maximum Duty Cycle Temperature Stability RT = 10 kΩ RT = 2.2 kΩ RT = 1 kΩ RT = 680 Ω

Application Information

The AS3842/3/4/5 family of current-mode control ICs are low cost, high performance controllers which are pin compatible with the industry stan - dard UC3842 series of devices. Suitable for many switch mode power supply applications, these ICs have been optimized for use in high frequency of f-line and DC-DC converters. The AS3842 has been enhanced to provide signifi - cantly improved performance, resulting in excep- tionally better tolerances in power supply manufacturing. In addition, all electrical charac - teristics are guaranteed over the full 0 to 105 ¡C temperature range. Among the many enhance - ments are: a precision trimmed 2.5 volt reference (+/Ð 1% of nominal at the error amplifier input), a significantly reduced propagation delay from cur- rent sense input to the IC output, a trimmed oscil- lator for precise duty-cycle clamping, a modified flip-flop scheme that gives a true 50% duty ratio clamp on 3844/45 types, and an improved 5 V regulator for better AC noise immunity . Further- more, the AS3842 provides guaranteed perfor - mance with current sense input below ground. The advanced oscillator design greatly simplifies synchronization. The device is more completely specified to guarantee all parameters that impact power supply manufacturing tolerances. Section 1 Ð Theory of Operation The functional block diagram of the AS3842 is shown in Figure 1. The IC is comprised of the six basic functions necessary to implement current mode control; the under-voltage lockout; the refer- ence; the oscillator; the error amplifier; the current sense comparator/PWM latch; and the output. The following paragraphs will describe the theory of operation of each of the functional blocks.

1.1 Under-voltage lockout (UVLO)

The under-voltage lockout function of the AS3842 holds the IC in a low quiescent current (² 1 mA) ÒstandbyÓ mode until the supply voltage CC) exceeds the upper UVLO threshold volt - age. This guarantees that all of the ICÕ s internal circuitry are properly biased and fully functional before the output stage is enabled. Once the IC turns on, the UVLO threshold shifts to a lower level (hysteresis) to prevent V CC oscillations. The low quiescent current standby mode of the AS3842 allows ÒbootstrappingÓÐÑa technique used in off-line converters to start the IC from the rectified AC line voltage initially, after which power to the IC is provided by an auxiliary winding off the power supplyÕs main transformer. Figure 14 shows a typical bootstrap circuit where capacitor (C) is AS384x Current Mode Controller R < VDC MIN 1 mA R >1 mA

16 V/10 V (3842/4)

C AS384x

7 VCC

Figure 14. Bootstrap Circuit

charged via resistor (R) from the rectified AC line. When the voltage on the capacitor (VCC) reaches the upper UVLO threshold, the IC (and hence, the power supply) turns on and the voltage on C begins to quickly discharge due to the increased operating current. During this time, the auxiliary winding begins to supply the current necessary to run the IC. The capacitor must be sufficiently large to maintain a voltage greater than the lower UVLO threshold during start-up. The value of R must be selected to provide greater than 1 mAof current at the minimum DC bus voltage (R < VDCmin/1 mA). The UVLO feature of the AS3842 has significant advantages over standard 3842 devices. First, the UVLO thresholds are based on a temperature compensated bandgap reference rather than con- ventional zeners. Second, the UVLO disables the output at power down, of fering additional protec- tion in cases where V REG is heavily decoupled. The UVLO on some 3842 devices shuts down the 5 volt regulator only , which results in eventual power down of the output only after the 5 volt rail collapses. This can lead to unwanted stresses on the switching devices during power down. The AS3842 has two separate comparators which monitor both V CC and VREF and hold the output low if either are not within specification. The AS3842 family of fers two dif ferent UVLO options. The AS3842/4 has UVLO thresholds of 16 volts (on) and 10 volts (off). The AS3843/5 has UVLO levels of 8.4 volts (on) and 7.6 volts (off).

1.2 Reference (VREG and VFB)

The AS3842 effectively has two precise bandgap based temperature compensated voltage refer - ences. Most obvious is the VREG pin (pin 8) which is the output of a series pass regulator. This 5.0 V output is normally used to provide charging cur - rent to the oscillator Õs timing capacitor (Section 1.3). In addition, there is a trimmed internal 2.5 V reference which is connected to the non-inverting (+) input of the error amplifier . The tolerance of the internal reference is ± 1% over the full speci- fied temperature range, and ± 1% for V REG. The reference section of the AS3842 is greatly improved over the standard 3842 in a number of ways. For example, in a closed loop system, the voltage at the error amplifierÕs inverting input (V FB, pin 1) is forced by the loop to match the voltage at the non-inverting input. Thus, V FB is the voltage which sets the accuracy of the entire system. The

2.5 V reference of the AS3842 is tightly trimmed

for precision at V FB, including errors caused by the op amp, and is specified over temperature. This method of trim provides a precise reference voltage for the error amplifier while maintaining the original 5 V regulator specifications. In addi - tion, force/sense (Kelvin) bonding to the package pin is utilized to further improve the 5 V load reg- ulation. Standard 3842s, on the other hand, spec- ify tight regulation for the 5 V output only and rate it over line, load and temperature. The voltage at V FB, which is of critical importance, is loosely specified and only at 25¡C. The reference section, in addition to providing a precise DC reference voltage, also powers most of the ICÕ s internal circuitry . Switching noise, therefore, can be internally coupled onto the ref - erence. With this in mind, all of the logic within the AS3842 was designed with ECL type circuitry which generates less switching noise because it runs at essentially constant current regardless of logic state. This, together with improved AC noise rejection, results in substantially less switching noise on the 5 V output. The reference output is short circuit protected and can safely deliver more than 20 mA to power external circuitry.

1.3 Oscillator

The newly designed oscillator of the AS3842 is enhanced to give significantly improved perfor - mance. These enhancements are discussed in AS384xCurrent Mode Controller

hence, the maximum duty ratio.

1.3.1 Selecting timing components RT

5 V REG

6 OUTPUT

5 GND

Figure 15. Oscillator Set-up and Waveforms

erence voltage, ID is the discharge current.

1.3.2 Oscillator enhancements

Table 1. RT vs Maximum Duty Ratio

1.3.3 Synchronization

simple circuits for implementing synchronization.

1.4 Error amplifier (COMP)

is forced to remain in its Òpull-upÓ condition.

1 COMP

Figure 17. Error Amplifier Compensation

2 K 2 K

3 KCMOS

Figure 16. Synchronization

the converterÕs output is at the desired voltage. amplified by the high gain of the error amplifier . purpose of the clamp is discussed in Section 1.5.

1.4.1 Loop compensation

(> 45¡) to ensure stability.

1.2 MHz with approximately 57 ¡C of phase mar -

Figure 18. Gain/Phase Response of the AS3842 Figure 19. A Typical Compensation Network

has no effect on the loop gain/phase response. ever, is beyond the scope of this application note.

1.5 ISENSE current comparator/PWM

mance with the current sense input below ground. allowed at the output for each oscillator period. inductor current of the converter. Figure 20. The current will continue to ramp up

produce 1.0 V at the maximum allowed current.

1.6 Output (OUT)

sourcing and sinking up to 1 A of peak current.

1.7 Over-temperature shutdown

5 V REG2R

Figure 20. Current Sense/PWM Latch Circuit and W aveforms Figure 21. Optional Current Transformer

through a nominal hysteresis band.

2.1 Leading edge filter

prematurely terminating the output pulse. A simple RC filter is used to suppress the spike.

2.2 Slope compensation

Figure 22. Slope Compensation

when operated at duty ratios greater than 50%. the slope compensation to the current waveform. as depicted in Figure 23(b). Figure 23. Slope Compensation

instabilities caused by the low amplitude of the current sense ramp waveform. In such a case, any noise on the waveform can be suf ficient to trip the comparator resulting in random and pre - mature pulse termination. The addition of a small amount of artificial ramp (slope compensation) can eliminate such problems without drastically affecting the overall performance of the system.

2.3 Circuit layout and other

The electronic noise generated by any switch- mode power supply can cause severe stability problems if the circuit is not layed-out (wired) properly. A few simple layout practices will help to minimize noise problems. When building prototype breadboards, never use plug-in protoboards or wire wrap construction. For best results, do all breadboarding on double sided PCB using ground plane techniques. Keep all traces and lead lengths to a minimum. Avoid large loops and keep the area enclosed within any loops to a minimum. Use common point grounding techniques and separate the power ground traces from the signal ground traces. Locate the control IC and circuitry away from switching devices and magnetics. Also, the tim - ing capacitorÕs ground connection must be right at pin 5 as shown in Figure 15. These grounding and wiring techniques are very important because the resistance and inductance of the traces are significant enough to generate noise glitches which can disrupt the normal operation of the IC. Also, to provide a low impedance path for high frequency noise, V CC and VREF should be decou- pled to IC ground with 0.1 µF capacitors. Addi- tional decoupling in other sensitive areas may also be necessary. It is very important to locate the decoupling capacitors as close as possible to the circuit being decoupled. AS384x Current Mode Controller