AS3820

Dialog Semiconductor

16-Channel White LED Controller for LCD Backlight

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PDF pages: 52

Technical content

1 Description

The AS3820 is a 16 channel precision LED controller for use in LCD-backlight panels. Dynamic power feedback controls the external power supply to guarantee best efficiency. Built-in safety features include thermal shutdown as well as open and short LED detection. The device is programmable via serial interface.

2 Features

All LED backlight topologies x No limit of VLED or ILED, device is not exposed to high voltage/high current
Optimum power savings through local dimming x 16 fully flexible 12 bit PWM generators (period, high time, delay, reverse)
Highest brightness uniformity x One global high accuracy 10 bit DAC which sets the LED current (±0.5% accuracy)
Full platform approach x Dedicated device family (AS382x)(1) is available, all SW compatible
Global dimming mode available x AS3820E is pre-programed to external PWM mode. VSYNC pin is used as PWM input
Synchronization with TV frame x VSYNC and HSYNC inputs available as well as a digital PLL integrated (2)
Lowest BOM x Due to 2 pin concept of the output channel: no HV protection, no cascade FETs
Digital enhanced DC-DC feedback x Feedback function is compatible to every DC-DC architecture and configurable via SPI (2)
On chip safety features x Short/open LED detection, temperature shutdown, register lock/unlock, SPI transfer checksum

3 Applications

The AS3820 is suitable for LED backlighting for LCD such as TV sets and monitors. Notes: Note 1. The device family AS382x includes AS3820 and AS3824. Note 2. Patent protected NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 2 of 52 05-Feb-2019 Figure 3.1 : AS3820 Typical Application Enable DCDC Switch output voltage range Dynamic power control Dynamic power control NOT RECOMMENDED FOR NEW DESIGNS

1 G1 A_I/O Connect to gate of external transistor

2 S1 A_I/O Connect to source of external transistor

3 V3_2 P Digital supply output. Connect 2.2μF capacitor to GND

4 VSYNC DI_PD Vertical sync frequency

5 HSYNC DI_PD Clock input for PWM generators

6 VDD P Power supply. Connect 4.7μF bypass capacitor to GND

7 FB2 A_I/O Power supply feedback output2

8 FB1 A_I/O Power supply feedback output1

9 VSSA P GND

10 VSS_SENSE P GND

11 S16 A_I/O Connect to source of external transistor

12 G16 A_I/O Connect to gate of external transistor

13 S15 A_I/O Connect to source of external transistor

14 G15 A_I/O Connect to gate of external transistor

15 S14 A_I/O Connect to source of external transistor

4 Pinout Description

Figure 4.1 : QFN-48 Pin Diagram of AS3820 (Top View) NOT RECOMMENDED FOR NEW DESIGNS

16 G14 A_I/O Connect to gate of external transistor

17 S13 A_I/O Connect to source of external transistor

18 G13 A_I/O Connect to gate of external transistor

19 G12 A_I/O Connect to gate of external transistor

20 S12 A_I/O Connect to source of external transistor

21 G11 A_I/O Connect to gate of external transistor

22 S11 A_I/O Connect to source of external transistor

23 G10 A_I/O Connect to gate of external transistor

24 S10 A_I/O Connect to source of external transistor

25 G9 A_I/O Connect to gate of external transistor

26 S9 A_I/O Connect to source of external transistor

27 xFAULT DO_OD Fault output. Open drain. Connect pullup to V3_2

28 DCDCEN DO GPIO output to enable DC-DC converter

29 MODE3D DO GPIO output to enable 3D mode

30 xCS DI_PU SPI interface chip select 31 SDO DO SPI interface data output. Tristate output

32 V3_2 P LED current output

33 SCL DI_PD Exposed Pad: Connect to GND

34 SDI DI_PD Digital supply output

35 S8 A_I/O Connect to source of external transistor

36 G8 A_I/O Connect to gate of external transistor

37 S7 A_I/O Connect to source of external transistor

38 G7 A_I/O Connect to gate of external transistor

39 S6 A_I/O Connect to source of external transistor

40 G6 A_I/O Connect to gate of external transistor

41 S5 A_I/O Connect to source of external transistor

42 G5 A_I/O Connect to gate of external transistor

43 G4 A_I/O Connect to gate of external transistor

4 Pinout Description (cont’d)

NOT RECOMMENDED FOR NEW DESIGNS

44 S4 A_I/O Connect to source of external transistor

45 G3 A_I/O Connect to gate of external transistor

46 S3 A_I/O Connect to source of external transistor

47 G2 A_I/O Connect to gate of external transistor

48 S2 A_I/O Connect to source of external transistor

EP VSSA P Exposed PAD. Connect to VSSP Note 1. If an output channel X is not used, short Gx and Sx. A_I/O: Analog pin P: Power pin DO: Digital Output DO_OD: Digital Output Open Drain DI: Digital Input DI_PU: Digital Input with Pull Up resistor DI_PD: Digital Input with Pull Down resistor NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 6 of 52 05-Feb-2019 Absolute maximum ratings are the parameter values or ranges which can cause permanent damage if exceeded. For maximum safe operating conditions, refer to the Electrical Characteristics section.

5 Absolute Maximum Ratings

Parameter Symbol Test Conditions Min Max Unit Electrical Parameters Supply Voltage to Ground VDDMAX Applicable for pin VDD -0.3 7 V Maximum Voltage Analog pins VANA_MAX (Note 1) -0.3 7 V Maximum Voltage Digital pins VDIG_MAX (Note 2) -0.3 5 V Latch-up Immunity ILATCH JEDEC JESD78D Nov 2011 ±100 mA Electrostatic Discharge Electrostatic Discharge ESDHBM Norm: MIL 883 E Method 3015 Human body model ±2000 V Temperature Ranges and Storage Conditions Junction Temperature TJMAX 150 °C Storage Temperature Range TSTRG -55 150 °C Package Body Temperature TBODY The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn) 260 °C Relative Humidity (non-condensing) RHNC 5 85 % Moisture Sensitivity Level MSL Maximum floor life time of 168h 3 Notes: Note 1. Pins: FB1,FB2,G1-G16, S1-S16,VSYNC, HSYNC. Note 2. Pins: V3_2, SDI, SDO, SCL, xCS, MODE3D, DCDCEN, xFAULT. NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 7 of 52 05-Feb-2019 Parameter Symbol Test Conditions Min Typ Max Unit Thermal Resistance case – ambient RTHCA See section 8.10 °C/W Junction Temperature TJ -20 115 °C Supply Voltages Supply Voltage VDD 4.5 5.5 V Voltage Regulator Output V3_2 ILOAD = 20mA 3.0 3.2 3.4 V Power-on Reset Level V3_2_POR Circuit stays in power down until V3_2 reaches V3_2_POR 1.6 2.2 V Under voltage Lockout Level VDD_UVL Current outputs are turned OFF if VDD is lower than VDD_UVL. This is done by resetting the CURRx bits. 2.4 2.9 V Quiescent Current, PWM = “0” IDDQ VDD = 5V, default setting 12 mA Supply Current IDDR VDD = 5V, HSYNC = 1MHz, VSYNC = 480Hz, Duty = 50%, VDAC = 250mV 13 mA Current Outputs Trimmed Current Accuracy at 25°C ILED_500_250 Trimmed during production. ILED = 100mA, DACref = 500mV, VDAC = 250mV, TJ = 25°C (excluding error of external Rset) -0.5 +0.5 % Channel to Channel Accuracy at 25°C ICH_250 ILED=100mA, DACref = 500mV, VDAC = 250mV, TJ = 25°C (excluding error of external Rset) -0.2 +0.2 % Current Accuracy Over VDAC ILED_500_ALL DACref = 500mV, VDAC = 200mV - 500mV, TJ = 25°C (excluding error of external Rset) -1.5 +1.5 % Current Accuracy Over VDAC and Temperature ILED_500_TMP DACref = 500mV, VDAC = 200mV – 500mV TJ = -20°C to 115°C (excluding error of external Rset) -2 +2 % Trimmed Current Accuracy at 25°C ILED_800_250 Trimmed during production. ILED = 100mA, DACref = 800mV, VDAC = 250mV, TJ = 25°C (excluding error of external Rset) -0.5 +0.5 % All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. VCC = 12V, -40°C ≤ TA ≤ 85°C, unless otherwise specified.

6 Electrical Characteristics

NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 8 of 52 05-Feb-2019 Parameter Symbol Test Conditions Min Typ Max Unit Current Outputs (cont’d) LED Current Accuracy Over VDAC I800_ALL DACref = 800mV, VDAC = 200mV - 800mV, TJ = 25°C (excluding error of external Rset) -1.5 +1.5 % LED Current Accuracy Over VDAC and Temperature I800_TEMP DACref = 800mV, VDAC = 200mV - 800mV, TJ = -20°C to 115°C (excluding error of external Rset) -2 +2 % Output current pin Gx IGX 3 4 mA Output resistor pin Gx RGX 1.0 1.3 kW Output voltage pin Gx Vgx Igx = 0mA VDD V Feedback Circuit, Fault Detectors Feedback Current Maximum IFBMAX VFB_X > 0.25V 255 mA Step Size of FB Counter (LSB) FB_IDAC_LSB 1 mA Overtemperature Limit TOVTEMP 130 140 150 °C Overtemperature Hysteresis THYST 10 °C Minimum Time to Detect Short tSHORT_MIN 300 ms PWM Generators Internal Clock for PWM fOSC 400 500 600 kHz HSYNC Frequency fHSYNC 100 2000 kHz VSYNC Frequency fVSYNC 60 480 Hz Digital Pins High Level Input Voltage VIH 1.3 V3_2 + 0.3 V Low Level Input Voltage VIL -0.3 0.8 V High Level Output Voltage VOH I = 2mA V3_2 - 0.3 V Low Level Output Voltage VOL I = 2mA 0.3 V Low Level Output Voltage Open Drain Outputs VOL_PD I = 2mA 0.3 V Input Resistance Pullup Inputs R_PU 300 kΩ Input Resistance Pulldown Inputs R_PD 300 kΩ VCC = 12V, -40°C ≤ TA ≤ 85°C, unless otherwise specified Electrical Characteristics (cont.) NOT RECOMMENDED FOR NEW DESIGNS

7 Functional Block Diagram

Figure 7.1 : AS3820 Functional Block Diagram NOT RECOMMENDED FOR NEW DESIGNS

7.1 Pin Equivalent Circuits

Figure 7.2 : Pin Equivalent Circuits VDD GND V3_2 GND V3_2 GND V3_2 GND V3_2 GND V3_2 GND GND VDD GND VDD Digital Input Digital Input with PullUp Digital Input with PullDown Digital inputs HSYNC,VSYNC Digital output Push/Pull Digital output open drain Feedback output Analog I/O 7V VDD GND NOT RECOMMENDED FOR NEW DESIGNS

8 Detailed Description

This section provides a detailed description of the device related components.

8.1 Current Outputs

Figure 8.1 : Detailed Block Diagram of Precision Current Sink

8.1.1 Precision Current Sink

All current sinks are built with an internal error amplifier A1 and an external power transistor. The external transistor can either be a NMOS or a NPN bipolar transistor. For low EMI radiation the slew rate of the amplifier output voltage can be adjusted.

8.1.2 Power Supply Feedback

The gate driving voltage for the external transistor is monitored to adjust the power supply output. If this voltage gets to high a comparator enables counting up of the “idac_fbX_counter” with 256μs clock speed. This increases the output current of the FB-IDAC and so the output voltage of the external power supply can be increased via pin FB1 or pin FB2. The feedback function of each output can be assigned to either FB1 or FB2. The power supply feedback can be turned OFF for every current channel separately.

8.1.3 Manual Control of the External Power Supply Voltage

The counter value “idac_fbX_counter” can also be preset by software if “fbcounter_man_fx” =1. This enables software control of the external power supply output voltage. NOT RECOMMENDED FOR NEW DESIGNS

8.1.4 Open LED Detection

If open led detection is enabled a broken LED-string is detected during PWM=1. If a LED-string is broken and the feedback function is enabled, the “idac_fbx_counter” will count up in order to increase the power supply output volt- age. After the “idac_fbx_counter” has reached its maximum value, a debounce counter is started. In order to run the debounce counter, the corresponding PWM-signal has to be high for more than 150μs. After the debounce couter has counted up for 32ms, the corresponding “OPENLED_x” bit is set and the output xFAUL T = “0”. Figure 8.2 : Open LED Detection

8.1.5 Short LED Detection

Short LED detection is implemented in two different ways: 1. With a built-in self-test (Short-BIST) circuit. 2. With two comparator inputs for monitoring external voltages (Short-COMP). The external voltage is divided by an external resistor and an internal current source. The output of the comparators only takes effect if all selected PWM-signals are “1” for a minimum time of “Tshortmin“ at the same time. The selection of Short1 or Short2 Group is done by “fb_ON_x” and “fb_sel_X”. F NOT RECOMMENDED FOR NEW DESIGNS

8.1.6 DAC

The reference voltage for the output stage is generated by an internal 10-bit DAC. The DAC reference can be selected between 500mV and 800mV depending on register settings. The DAC is trimmed during production with DACref = 800mV/VDAC = 250mV and DAQref = 500mV/VDAC = 250mV to guarantee an output current accuracy of ±0.5% on every current output. Figure 8.4 : DAC and DAC Reference Generation NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 14 of 52 05-Feb-2019 The DAC output voltage can be calculated with: DACref 1024 DAC...10-bit data value DACref...DAC reference voltage 500mV or 800mV

8.1.7 Registers in Current Output Stage

The access mode explanation is as follows: R: Read only RW, R/W: Read and write RWL: Read and write with lock ACS_WC: Auto clear and set, write clear RW_AC: Read and write, auto clear RW_AS: Read and write, auto set R/WC: Read and write clear PUSH: W rite Addr: 0x01 CUR_ON_1 Bit Bit Name Default Access Bit Description 7:0 CURR1 - CURR8 00000000 RW_AC Enables or disables current outputs. 0: Output OFF 1: Output ON Table 1: CUR_ON_1 Addr: 0x02 CUR_ON_2 Bit Bit Name Default Access Bit Description 7:0 CURR9 - CURR16 00000000 RW_AC Enables or disables current outputs. 0: Output OFF 1: Output ON Table 2: CUR_ON_2 NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 15 of 52 05-Feb-2019 Addr: 0x03 Fault_1 Bit Bit Name Default Access Bit Description

7 Autotoff_uv 1 RW

1...Undervoltage lockout: If VDD < VDD_UVL channels are turned OFF by resetting CURRx-bits

6 Short_bist_en 0 RW_AC

1...Starts built-in self-test (BIST) for short detection. Bit is cleared after BIST has finished 5:4 Short_cmp_en 00 RW Short detection with comparators: Not available in LQFP44 00...OFF 01...Enables short comp 1 10...Enables short comp 2 11...Enables short comp 1 and comp 2 3 Retrial_open 0 RW 1... Retrial open detection after autotoff_open was triggered

2 Autotoff_ot 1 RW

Automatic output turn OFF at overtemperature 0... Do not turn OFF current outputs on overtemperature 1... Turn OFF current outputs on overtemperature 1 Open_en 0 RW 1... Enable open LED detection for all channels

0 Autotoff_open 0 RW

Automatic feedback turn OFF on open LED detection 0... Do not turn OFF feedback on open LED detection 1... Turn OFF feedback on open LED detection Table 3: Fault_1 NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 16 of 52 05-Feb-2019 Addr: 0x04 GPIO_CTRL Bit Bit Name Default Access Bit Description 7:6 xFAULT_config 0 RW Output configuration pin xFAULT: 00...Open Drain 01...Push/Pull 10...Hi-Z, input only 11...No effect 5:4 Mode3D_config 0 RW Output configuration pin Mode3D: 00...Open Drain 01...Push/Pull 10...Hi-Z, input only, SHORT COMP 2 INPUT enabled 11...No effect 3 Mode3D 0 RW 0...Pin Mode3D = 0 1...Pin Mode3D = 1 2:1 DCDCEN_config 0 RW Output configuration pin DCDCEN: 00...Open Drain 01...Push/Pull 10...Hi-Z, input only, SHORT COMP 1 INPUT enabled 11...No effect 0 DCDCEN 0 RW 0...Pin DCDCEN = 0 1...Pin DCDCEN = 1 Table 4: FB_SEL1 Addr: 0x05 FB_SEL1 Bit Bit Name Default Access Bit Description 7:0 Fb_sel_1 – Fb_sel_8 00000000 RW Select FB-channel for current outputs 1 to 8 0...Select FB channel FB1 and short-comparator group 1 1...Select FB channel FB2 and short-comparator group 2 Table 5: FB_SEL1 Addr: 0x06 FB_SEL2 Bit Bit Name Default Access Bit Description 7:0 Fb_sel_9 – Fb_sel_16 00000000 RW Select FB-channel for current outputs 9 to 16 0...Select FB channel FB1 and short-comparator group 1 1...Select FB channel FB2 and short-comparator group 2 Table 6: FB_SEL2 NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 17 of 52 05-Feb-2019 Addr: 0x07 CURR_CTRL Bit Bit Name Default Access Bit Description 7:6 Sel_ac 00 RW Do not change

5 Fb_ac_off 0 RW

0...AC feedback enabled 1...AC feedback disabled (external BJT) If Ib_comp=1, FB_ac_off = 1 must be set

4 Ib_comp 0 RW

0 ...Bias current compensation OFF 1...Bias current compensation ON (external BJT) If Ib_comp=1, FB_ac_off = 1 must be set 3 DACref_buffer 0 RW 0...DAC output is buffered 1...DAC output is unbuffered 2 DACref 0 RW 0...DACref = 500mV 1...DACref = 800mV 1:0 Slew_rate 00 RW Select slew rate of output drivers. (Slew rate of VREF) 00...250mV/16μs 01...250mV/8μs 10...250mV/4μs 11...250mV/2μs Table 7: CURR_CTRL Addr: 0x08 SHORTLED_1 Bit Bit Name Default Access Bit Description 7:0 SHORTLED_1 – SHORTLED_8 00000000 R/WC Indicates short LED found with BIST on outputs 1 to 8 0...No short LED detected 1... Short LED detected Table 8: SHORTLED_1 Addr: 0x09 SHORTLED_2 Bit Bit Name Default Access Bit Description 7:0 SHORTLED_9 – SHORTLED_16 00000000 R/WC Indicates short LED found with BIST on outputs 9 to 16 0...No short LED detected 1... Short LED detected Table 9: SHORTLED_2 NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 18 of 52 05-Feb-2019 Addr: 0x0A OPENLED_1 Bit Bit Name Default Access Bit Description 7:0 OPENLED_1 – OPENLED_8 00000000 AS/WC Indicates open LED condition on outputs 1 to 8 0...No open LED detected 1... Open LED detected Table 10: OPENLED_1 Addr: 0x0B OPENLED_2 Bit Bit Name Default Access Bit Description 7:0 OPENLED_9 – OPENLED_16 00000000 AS/WC Indicates open LED condition on outputs 9 to 16 0...No open LED detected 1... Open LED detected Table 11: OPENLED_2 Addr: 0x0E FB_ON_1 Bit Bit Name Default Access Bit Description 7:0 FB_CURR_1 – FB_CURR _8 00000000 RW Enables or disables feedback function of output channels 0...No feedback function on CURRx 1... Function on CURRx Table 12: FB_ON_1 Addr: 0x0F FB_ON_2 Bit Bit Name Default Access Bit Description 7:0 FB_CURR_9 – FB_CURR _16 00000000 RW Enables or disables feedback function of output channels 0...No feedback function on CURRx 1... Function on CURRx Table 13: FB_ON_2 Addr: 0x0C Addr: 0x0D VDAC_H / VDAC_L Bit Bit Default Access Bit Description 7:0 1:0 0X80, 0X00 RW DAC input [9:0] Table 14: VDAC_H / VDAC_L NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 19 of 52 05-Feb-2019 Addr: 0x10 IDAC_FB1_COUNTER Bit Bit Name Default Access Bit Description 7:0 IDAC_FB1_COUNTER 00000000 RW Feedback 1 counter value. Can be overwritten if Fb_cnt_man_fb1 = 1 0x00... FB-current 0μA 0xFF... FB-current 255μA Table 15: IDAC_FB1_COUNTER Addr: 0x11 IDAC_FB12_COUNTER Bit Bit Name Default Access Bit Description 7:0 IDAC_FB2_COUNTER 00000000 RW Feedback 1 counter value. Can be overwritten if Fb_cnt_man_fb2 = 1 0x00... FB-current 0μA 0xFF... FB-current 255μA Table 16: IDAC_FB2_COUNTER Addr: 0x12 FBLOOP_CTRL Bit Bit Name Default Access Bit Description 7:6 Vtrip 00 RW Select gate trip voltage for feedback 00...5*(VDD/6) 01... 4*(VDD/6) 10... 3*(VDD/6) 11... 2*(VDD/6)

5 Fb_cnt_man_fb2 0 RW

0...FB2 counter runs automatically in feedback loop 1...FB2 counter is set manual

4 Fb_cnt_man_fb1 0 RW

0...FB1 counter runs automatically in feedback loop 1...FB1 counter is set manual 3:2 Fbcount_dn_time 01 RW FB1 and FB2 counter down counting clock cycle (1) 00...512μs 01...2048μs 10...4096μs 11...8192μs 1:0 Fbcount_up_time 01 RW FB1 and FB2 counter up counting clock cycle 00...1024μs 01... 256μs 10... 64μs 11... 16μs Note 1. Down counting starts after 200ms delay time. Table 17: FBLOOP_CTRL NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 20 of 52 05-Feb-2019 Addr: 0x60 STATUS Bit Bit Name Default Access Bit Description 7 STAT novsync 0 R 1...Indicates missing Vsync signal for longer than 100ms 6 STAT OT 0 R 1...Indicates Overtemperature fault happened 5 STAT Open 0 R 1...Indicates open detection fault happened 4 Short_bist 0 R 1...Indicates a short bist interrupt 3 Vcnt underflow 0 AS_WC 1...VSYNC signal to fast 2 Short2 0 AS_WC 1...Indicates short on channel group 2 1 Short1 0 AS_WC 1...Indicates short on channel group 1 0 Power_good 0 R 1...Power good. Indicates that VDD is greater than VDD_UVL Table 18: STATUS Addr: 0x63 SHORT_BIST_CTRL1 Bit Bit Name Default Access Bit Description 7:5 000 R Do not change 4 BIST_retrial 0 RW 0...No BIST retrial 1...Short BIST retrial after 1 second

3 BIST_steptime 0 RW

BIST counter step down time 0...64μs/step 1...128μs/step 2 Autotoff_BIST 0 RW 1...Shorted channels found by BIST are turned OFF 1:0 BIST_wait 0 RW Wait after max step down value of counter is reached (1) 00...No wait 01...Wait 1 VSYNC pulse 10...Wait 2 VSYNC pulses 11...Wait 3 VSYNC pulses Note 1. This option is necessary for phase shifted PWM. To ensure each channel is tested. Table 19: SHORT_BIST_CTRL1 Addr: 0x64 SHORT_BIST_MAXSTEP Bit Bit Name Default Access Bit Description 7:0 BISTmaxstep 11111111 RW Maximum down-counts of IDAC counter during BIST Table 20: SHORT_BIST_MAXSTEP NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 21 of 52 05-Feb-2019 Addr: 0x65 SHORT_BIST_CTRL2 Bit Bit Name Default Access Bit Description 7:6 00 R Do not change 5 COMP_retrial 0 RW 0...No COMP retrial 1...Short COMP retrial after 1 second 4 Autotoff_COMP 0 RW 1...Shorted channels found by COMP are turned OFF 3:0 COMP_LEVEL 1010 RW Short detection voltage based on exter- nal 100k resistor 0000...2V 0001...3V 0010...4V 0011...5V 0100...6V 0101...7V 0110...8V 0111...9V 1000...10V 1001...11V 1010...12V 1011...13V 1100...13V 1101...13V 1110...13V 1111...13V Table 21: SHORT_BIST_CTRL2 Addr: 0x6C COMPREG_1 Bit Bit Name Default Access Bit Description 7:0 CompReg1 – CompReg8 00000000 AS/AR Status of trip comparator Table 22: COMPREG_1 Addr: 0x6D COMPREG_2 Bit Bit Name Default Access Bit Description 7:0 CompReg9 – CompReg16 00000000 AS/AR Status of trip comparator Table 23: COMPREG_2 NOT RECOMMENDED FOR NEW DESIGNS

8.2 PWM Generators

Figure 8.5 : PWM Generators

8.2.1 Clock and Reset

The clock for the built-in PWM generators can be one of the three different sources listed below:

Internal RC oscillator with 500kHz
External clock signal. This is usually the HSYNC signal of the TV
Digital PLL (DPLL) clock derived from VSYNC

8.2.2 Digital PLL

A DPLL can be used to generate the PWM generator counter clock with a frequency that is a multiple of the VSYNC frequency. The frequency multiplication factor can be controlled to be either “PWMperiod” or “PLLmulti” by control bit “PLL_per_sel”. By default “PLL_per_sel”=”0” to control the frequency by “PWMperiod” which also defines the period for the PWM generators. If necessary, control bit “PLL_per_sel” can be set to control the frequency multiplication by register “PLLmulti” with 16-bit resolution and independently of PWMperiod. PLL_per_sel=0 (default): fDPLLout fVSYNC PWMperiod×= PLL_per_sel=1: fDPLLout fVSYNC PLLmulti×= The VSYNC frequency is determined by measuring the VSYNC period with an internal clock. Since the internal clock and the external VSYNC signal are asynchronous, the result of the measurement will jitter by one internal clock cycle. Therefore the generated DPLL-frequency jitters by one clock cycle. C C C C E NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 23 of 52 05-Feb-2019 In order to prevent starting of a new PWM-period at the end of the current PWM-period due to this jitter it is recom- mended to use the following setting:

Set PLL_per_sel=1
Set PLLmulti = PWMperiod -1 By either changing the input frequency at VSYNC or by changing the divider setting the DPLL will need up to 4 VSYNC cycles to settle to the new value. If fVSYNC > 8MHz/PLLmulti, the bit VCNT is set and a fault is indicated.

8.2.3 PWM Counter

Figure 8.6 : PWM Counter Each PWM-generator is build with a 13bit counter and digital comparators. The counter is counting up with tclk until the value stored in “PWMper” is reached. This resets the counter and starts the next period. While the counter value is below “PWMxHT” the PWM-signal is “1”, the rest of the period the PWM-signal is “0”. The output of each PWM-generator can also be inverted by means of the “PWMrev”. Figure 8.7 : PWMx, VSYNC and CLK Timing Diagram

8.2.4 SPI Data Update, UPDATEmode Bit

The PWM-settings that are programmed via the SPI-Interface take effect depending on the status of the “UPDATEmode”-bit. If UPDATEmode = 1 new data from the serial interface are stored at the next rising edge of VSYNC. PMWper *tclk PMWxHT *tclkPMWxDEL *tclk PMWx VSYNC clk NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 24 of 52 05-Feb-2019 If UPDATEmode = 0 new data from the serial interface are store immediately after xCS goes high and will take effect after current PWM cycle is finished. In this mode the values in the PWMxdel registers are ignored. There will be no Delay on the PWM signals. Figure 8.8 : UPDATE mode The PWMxHT-values are double buffered. HighTime values for the next VSYNC can be written even when the current HighTime is not finished. Within the first two HSYNC pulses after rising VSYNC no SPI data transfer is allowed.

8.2.5 Direct PWM Mode

The internal signals PWMx can also be direct applied at the VSYNC input if the bit Direct_PWM =1. In this mode the default driver has the following configuration:

All current outputs are ON
All feedback controls are enabled and connected to FB1
Open LED detection is enabled
Open LED detection auto turn OFF function is enabled
Open LED detection retrial function is enabled
Short LED detection (Short-COMP) is enabled
Short LED detection auto turn OFF function is enabled
Undervoltage lockout and overtemperature detection are enabled In this mode the device starts with default settings and can still be programmed via SPI. NOT RECOMMENDED FOR NEW DESIGNS

8.2.6 VSYNC Detect

If the bit ”VSYNCdet” is set (Register “PWM_CTRL”) the VSYNC detector monitors the presence of a VSYNC signal. If the VSYNC signal is missing for more than 100ms the following changes are done:

In Register “STATUS” the bit “STAT novsync” is set
Output xFAULT is acitivated (LOW)
Current outputs are turned OFF. All register settings remain while the outputs are turned OFF If the VSYNC signal is applied again the following changes are done:
In Register “STATUS” the bit “STAT novsync” is reset
Output xFAULT is deactivated
Current outputs are turned ON

8.2.7 VSYNC Duration

Since the VSYNC input is connected to an edge detector, there is no restriction on the duration of the VSYNC pulse. NOT RECOMMENDED FOR NEW DESIGNS

8.3 Registers in PWM Generators

RegAddr: 0x13 PWM_CTRL

7 PLL_per_sel 0 RW

0...DPLL-period = Vsync*PWMperiod 1...DPLL-period = Vsync*PLLmulti

6 ClockSrc1 0 RW

Clock source for internal PWM-generators 0…Internal RC oscillator or HSYNC (depending on ClockSrc0) 1...PLL output 5 Pwm_rev 0 RW 0...Normal PWM operation 1...PWM signals are inverted

4 VSYNCdet 0 RW _AS

0...VSYNC-detection OFF 1... VSYNC-detection ON. All current outputs are turned OFF if VSYNC signal is missing for 100ms

3 VSYNCedge 0 RW

Defines VSYNC trigger edge 0...VSYNC trigger on rising edge 1...VSYNC trigger on falling edge

2 Direct_PWM 0 RW _AS

Select external or internal PWM signal 0...PWM signal is generated internally 1...PWM signal is applied externally at pin VSYNC Factory trim bit is read during startup. See section Direct PWM Mode

1 Update_Mode 0 RW

Defines when internal registers are updated 0...Registers updated with rising edge of xCS 1...Registers updated with next VSYNC-edge

0 ClockSrc0 0 RW

Clock source for internal PWM-generators 0…Internal RC oscillator 1...External Pin HSYNC See Note 1 Note 1. This bit only takes effect when ClockSrc1 = 0. Table 24: PWM_CTRL RegAddr: 0x15 RegAddr: 0x14 PWMperiod Bit Bit Default Access Bit Description 4:0 7:0 0x00, 0x00 RW PWMper[12:0] sets PWM period Table 25: PWMperiod RegAddr: 0x17 RegAddr: 0x16 PWM1delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM1per[11:0] sets PWM1 delay Table 26: PWM1delay NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 27 of 52 05-Feb-2019 RegAddr: 0x19 RegAddr: 0x18 PWM2delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM2per[11:0] sets PWM2 delay Table 27: PWM2delay RegAddr: 0x1B RegAddr: 0x1A PWM3delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM3per[11:0] sets PWM3 delay Table 28: PWM3delay RegAddr: 0x1D RegAddr: 0x1C PWM4delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM4per[11:0] sets PWM4 delay Table 29: PWM4delay RegAddr: 0x1F RegAddr: 0x1E PWM5delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM5per[11:0] sets PWM5 delay Table 30: PWM5delay RegAddr: 0x21 RegAddr: 0x20 PWM6delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM6per[11:0] sets PWM6 delay Table 31: PWM6delay RegAddr: 0x23 RegAddr: 0x22 PWM7delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM7per[11:0] sets PWM7 delay Table 32: PWM7delay RegAddr: 0x25 RegAddr: 0x24 PWM8delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM8per[11:0] sets PWM8 delay Table 33: PWM8delay NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 28 of 52 05-Feb-2019 RegAddr: 0x27 RegAddr: 0x26 PWM9delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM9per[11:0] sets PWM9 delay Table 34: PWM9delay RegAddr: 0x29 RegAddr: 0x28 PWM10delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM10per[11:0] sets PWM10 delay Table 35: PWM10delay RegAddr: 0x2B RegAddr: 0x2A PWM11delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM11per[11:0] sets PWM11 delay Table 36: PWM11delay RegAddr: 0x2D RegAddr: 0x2C PWM12delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM12per[11:0] sets PWM12 delay Table 37: PWM12delay RegAddr: 0x2F RegAddr: 0x2E PWM13delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM13per[11:0] sets PWM13 delay Table 38: PWM13delay RegAddr: 0x31 RegAddr: 0x30 PWM14delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM14per[11:0] sets PWM14 delay Table 39: PWM14delay RegAddr: 0x33 RegAddr: 0x32 PWM15delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM15per[11:0] sets PWM15 delay Table 40: PWM15delay NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 29 of 52 05-Feb-2019 RegAddr: 0x35 RegAddr: 0x34 PWM16delay Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM16per[11:0] sets PWM16 delay Table 41: PWM16delay RegAddr: 0x36 LOCKUNLOCK Bit Bit Name Default Access Bit Description 7:0 LOCKUNLOCK 0x00 RW MagicByte to lock and unlock writing and reading of registers Writing into register: 0xCX...Unlock register Group1. Writing enabled 0xXA...Unlock register Group2. Writing enabled 0xCA...Unlock register Group1 and Group2. Writing enabled 0xAX...Lock register Group1. Writing disabled 0xXC...Lock register Group2. Writing disabled 0xAC...Lock register Group1 and Group2. Writing disabled X...Don’t care. All other values do not change the status of LOCKUNLOCK. Reading from register: 0x00....Group1 and Group2 are locked 0x01...Group1 is unlocked 0x02...Group2 is unlocked 0x03...Group1 and Group2 are unlocked Table 42: LOCKUNLOCK RegAddr: 0x38 RegAddr: 0x37 PWM1hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM1HT[11:0] sets PWM1 high time Table 43: PWM1hightime RegAddr: 0x3A RegAddr: 0x39 PWM2hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM2HT[11:0] sets PWM2 high time Table 44: PWM2hightime RegAddr: 0x3C RegAddr: 0x3B PWM3hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM3HT[11:0] sets PWM3 high time Table 45: PWM3hightime NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 30 of 52 05-Feb-2019 RegAddr: 0x3E RegAddr: 0x3D PWM4hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM4HT[11:0] sets PWM4 high time Table 46: PWM4hightime RegAddr: 0x40 RegAddr: 0x3F PWM5hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM5HT[11:0] sets PWM5 high time Table 47: PWM5hightime RegAddr: 0x42 RegAddr: 0x41 PWM6hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM6HT[11:0] sets PWM6 high time Table 48: PWM6hightime RegAddr: 0x44 RegAddr: 0x43 PWM7hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM7HT[11:0] sets PWM7 high time Table 49: PWM7hightime RegAddr: 0x46 RegAddr: 0x45 PWM8hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM8HT[11:0] sets PWM8 high time Table 50: PWM8hightime RegAddr: 0x48 RegAddr: 0x47 PWM9hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM9HT[11:0] sets PWM9 high time Table 51: PWM9hightime RegAddr: 0x4A RegAddr: 0x49 PWM10hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM10HT[11:0] sets PWM10 high time Table 52: PWM10hightime NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 31 of 52 05-Feb-2019 RegAddr: 0x4C RegAddr: 0x4B PWM11hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM11HT[11:0] sets PWM11 high time Table 53: PWM11hightime RegAddr: 0x4E RegAddr: 0x4D PWM12hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM12HT[11:0] sets PWM12 high time Table 54: PWM12hightime RegAddr: 0x50 RegAddr: 0x4F PWM13hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM13HT[11:0] sets PWM13 high time Table 55: PWM13hightime RegAddr: 0x52 RegAddr: 0x51 PWM14hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM14HT[11:0] sets PWM14 high time Table 56: PWM14hightime RegAddr: 0x54 RegAddr: 0x53 PWM15hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM15HT[11:0] sets PWM15 high time Table 57: PWM15hightime RegAddr: 0x56 RegAddr: 0x55 PWM16hightime Bit Bit Default Access Bit Description 3:0 7:0 0x00, 0x00 RW PWM16HT[11:0] sets PWM16 high time Table 58: PWM16hightime NOT RECOMMENDED FOR NEW DESIGNS

8.4 Power Supply

8.4.1 Voltage Regulator V3_2

A build in linear voltage regulator provides 3.2V supply voltage for external devices at pin V3_2. A 2.2μF decoupling capacitor should be connected to pin V3_2.

8.4.2 Interface Power Supply V3_2

Pin V3_2 supplies all digital inputs/outputs.

8.5 Safety Features

8.5.1 Temperature Shutdown

If “autotoff_ot” = 1 the outputs of the device are turned OFF when the die temperature reaches 140°C. If the die temperature goes below 130°C the outputs are turned ON again.

8.5.2 Register Lock/Unlock

To prevent wrong writing to registers due to noise on the seria interface a lock/unlock mechanism is implemented. Register 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x63, 0x64, 0x65 belong to Group1 and can only be written if Group1 is unlocked by the “LOCKUNLOCK”-byte (Reg: 0x36) Register 0x0C, 0x0D, 0x14, 0x15, 0x61, 0x62 belong to Group2 and can only be written if Group2 is unlocked by the “LOCKUNLOCK”-byte (Reg: 0x36) The default value of the Groups is locked.

8.6 Dynamic Feedback Control

The output of pins “FB1” and “FB2” can be used to control any external power supply for best power efficiency. Every power supply senses its output voltage with a resistive voltage divider. This voltage divider can be modified to set the output voltage between a minimum output voltage VMIN and a maximum output voltage VMAX. The design of the dynamic feedback control is done in 2 steps. Step 1: Calculate resistors R1 in order to achieve the desired voltage range (VMAX – VMIN) with 255μA maximum current DAC output. Figure 8.13 : Step 1 VoutMAX – VoutMIN 255μA NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 36 of 52 05-Feb-2019 VOUT = (1 + _______) x VSENSE + R1 x “idac_fbx_counter” x 1μA Example: VoutMIN = 60V, VoutMAX = 80V, VSENSE = 1.25V (VoutMAX – VoutMIN) (80V – 60V) 255μA 255μA R1 78kW VoutMIN 60V VSENSE 1.25V

8.7 GPIO

The two pins DCDCEN and Mode3D can be used to change the configuration of a DC-DC controller. These pins can also be used as general purpose input/output pins which can be configured as high impedance input, Push-Pull output or Open drain output. Also the output pin xFAULT can be configured. Figure 8.16 : GPIO

8.8 SPI Interface

For the data transfer a serial peripheral interface (SPI) is used. The SPI is configured to work only as SPI slave. If more than one driver is connected to a SPI master, they can be connected in a “Daisy Chain”-structure or a parallel structure.

8.8.1 SPI Daisy Chain Structure

All SPI slaves share the same clock (SCLK) and chip select (xCS) signal. In that configuration all devices can be treated as one big shift register. The devices are automatically enumerated as described in the next section. NOT RECOMMENDED FOR NEW DESIGNS

8.8.2 SPI Parallel Structure

All SPI slaves share the same input (SDI) output (SDO) and clock (SCLK) signal. Every single device can be addressed via the chip select (xCS) signal. In this configuration every device has the “DevAddr = 0x01”. Figure 8.18 : SPI Parallel Structure Micro Controller Master MOSI SCLK xCS MISO AS38xxSCLK SDI xCS SDO AS38xxSCLK SDI xCS SDO AS38xxSCLK SDI xCS SDO Device #1 Device #2 Device #N Micro Controller Master MOSI SCLK xCS_1 MISO AS38xxSCLK SDI xCS Device #1 AS38xxSCLK SDI xCS Device #2 AS38xxSCLK SDI xCS Device #N xCS_2 xCS_N SDO SDO SDO NOT RECOMMENDED FOR NEW DESIGNS

8.8.3 SPI Device Address Enumeration

The device address of each driver is automatically set by the position of the device in the chain. The first device has DevAddr = 0x01, the second device has DevAddr = 0x02 and so on. Device Addresses 0x00 and 0x3F are used for special broadcast writing commands described below.

8.8.4 SPI Protocol

When xCS=0 all slaves will be activated. The addressing and data section is organized in byte packages. Each message can be built with the following bytes: B S DevAddr[5:0] Addresses a specific driver and defines protocol information Bit Meaning Value B Broadcast B=1...Broadcast message to all devices B=0...Normal message to one single device S Singlebyte S=0...Block data read or write S=1...Single data transmission (only one byte) DevAddr[5:0] Device Address 0x00 Write/read same data to same register of all devices (B=1) 0x01 to 0x3E. Device addresses for device 1 to 62 0x3F Write different data to same register of all devices (B=1) Table 1: Device Address NrOfdata[7:0] Defines the number of data bytes in the data frame if S=0 Bit Meaning Value NrOfdata[7:0] Number of data bytes in frame 0x00 to 0xFF Table 2: Number of Data RW RegAddr[6:0] Register address to be read or written Bit Meaning Value RW Read/Write RW=0 Write to register address RW=1 Read from register address RegAddr[6:0] Select register address 0x00 to 0x60 Table 3: Register Address NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 39 of 52 05-Feb-2019 Data[7:0] Bit Meaning Value Data[7:0] Data 0x00 to 0xFF Table 4: Data Timing Figure 8.19 : Write Single Data into Single Device Figure 8.20 : Read Single Data from Single DA… Device Address RA… Register Address D… Data

8.8.5 SPI Protocol Examples

The following drawings show various SPI protocol examples. Write Single Data Figure 8.21 : Write to Reg0x02 of Dev0x01 xCS SCLK SDI SDO Hi-Z Start devices address enumeration Hi-Z Store data into registers DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 D7 D6 D5 D4 D3 D2 D1 D0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xCS SCLK SDI SDO Hi-Z Start devices address enumeration Hi-Z DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 D7 D6 D5 D4 D3 D2 D1 D0 Reg 0x07 0x06 0x05 0x04 0x03 0x02 0x00 0x01 Device 0x01 Reg 0x07 0x06 0x05 0x04 0x03 0x02 0x00 0x01 Device 0x02 Reg 0x07 0x06 0x05 0x04 0x03 0x02 0x00 0x01 Device 0x03 0x03 MOSI 0x010 1 0 0x02 0x03 DevAddr RegAddr Data MISO 0x00 0x00 0x00 NOT RECOMMENDED FOR NEW DESIGNS

8.9 Timing Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit SCLK frequency fSCLK 0 10 MHz xCS setup time t1 50 ns xCS hold time t2 100 ns xCS disable time t3 100 ns SDI setup time t4 5 ns SDI hold time t5 5 ns SCLK rise time t6 5 ns SCLK fall time t7 5 ns SCLK low time t8 40 ns SCLK high time t9 40 ns Output valid from SCLK low t10 10 ns SCLK falling to xCS rising edge t11 50 ns Figure 8.31 : PCB FR4, 1cm Distance from Ground

8.10 Thermal Characteristics QFN48

The thermal characteristics of the devices were measured at 25°C ambient temperature. The device was mounted on a double sided FR4 PCB with the bottom layer used as cooling area. NOT RECOMMENDED FOR NEW DESIGNS

9 Register Overview

Registers can only be written if Group1 is UNLOCKED. Default = LOCKED Registers can only be written if Group2 is UNLOCKED. Default = LOCKED 0x00 Used for block writing 0x00 0x01 CUR_ON_1 curr_8 curr_7 curr_6 curr_5 curr_4 curr_3 curr_2 curr_1 0x00 0x02 CUR_ON_2 curr_16 curr_15 curr_14 curr_13 curr_12 curr_11 curr_10 curr_9 0x00 0x03 FAULT_1 auto- toff_uv Short Bist_en Shortcmp_en retrial_ open autotoff_ ot open_en autotoff_ open 0x84 0x04 GPIO_CTRL fault_n_config mode3D_config mode3D DCDCEN_config DCDCEN 0x00 0x05 FB_SEL_1 fb_sel[8] fb_sel[7] fb_sel[6] fb_sel[5] fb_sel[4] fb_sel[3] fb_sel[2] fb_sel[1] 0x00 0x06 FB_SEL_2 fb_sel[16] fb_sel[15] fb_sel[14] fb_sel[13] fb_sel[12] fb_sel[11] fb_sel[10] fb_sel[9] 0x00 0x07 CURR_CTRL Sel_ac Fb_ac_off Ib_comp DACref _buffer DACref slew_rate 0x00 0x08 SHORTLED_1 shortled_8 shortled_7 shortled_6 shor- tled_5 shortled_4 shortled_3 shortled_2 shortled_1 0x00 0x09 SHORTLED_2 shortled_ shortled_ shortled_ shortled_ shortled_ shortled_ shortled_ shortled_ 9 0x00 0x0A OPENLED_1 open_8 open_7 open_6 open_5 open_4 open_3 open_2 open_1 0x00 0x0B OPENLED_2 open_16 open_15 open_14 open_13 open_12 open_11 open_10 open_9 0x00 0x0C VDAC_H DAC[9] DAC[8] DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] 0x80 0x0D VDAC_L DAC[1] DAC[0] 0x00 0x0E FB_ON_1 fb_cur8 fb_cur7 fb_cur6 fb_cur5 fb_cur4 fb_cur3 fb_cur2 fb_cur1 0x00 0x0F FB_ON_2 fb_cur16 fb_cur15 fb_cur14 fb_cur13 fb_cur12 fb_cur11 fb_cur10 fb_cur9 0x00 0x10 IDAC_FB1_ COUNTER idac_fb1_counter[7:0] 0x00 0x11 IDAC_FB2_ COUNTER idac_fb2_counter[7:0] 0x00 0x12 FBLOOP_ CTRL Vtrip FB_cnt_ man_fb2 FB_cnt_ man_fb1 fbcounter_dn_time fbcounter_up_time 0x05 0x13 PWM_CTRL DPLL_ per_sel clock src1 pwm_rev vsync_ det vsync_ edge direct_ pwm update_ mode clock src0 0x00 0x14 PWMperi- odLSB pwm per7 pwm per6 pwm per5 pwm per4 pwm per3 pwm per2 pwm per1 pwm per0 0x00 0x15 PWMperi- odMSB 0 0 0 pwm per12 pwm per11 pwm per10 pwm per9 pwm per8 0x00 0x16 PWM1delLSB pwm1 del7 pwm1 del6 pwm1 del5 pwm1 del4 pwm1 del3 pwm1 del2 pwm1 del1 pwm1 del0 0x00 0x17 PWM1delMSB 0 0 0 0 pwm1 del11 pwm1 del10 pwm1 del9 pwm1 del8 0x00 0x18 PWM2delLSB pwm2 del7 pwm2 del6 pwm2 del5 pwm2 del4 pwm2 del3 pwm2 del2 pwm2 del1 pwm2 del0 0x00 0x19 PWM2delMSB 0 0 0 0 pwm2 del11 pwm2 del10 pwm2 del9 pwm2 del8 0x00 NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 46 of 52 05-Feb-2019 0x1A PWM3delLSB pwm3 del7 pwm3 del6 pwm3 del5 pwm3 del4 pwm3 del3 pwm3 del2 pwm3 del1 pwm3 del0 0x00 0x1B PWM3delMSB 0 0 0 0 pwm3 del11 pwm3 del10 pwm3 del9 pwm3 del8 0x00 0x1C PWM4delLSB pwm4 del7 pwm4 del6 pwm4 del5 pwm4 del4 pwm4 del3 pwm4 del2 pwm4 del1 pwm4 del0 0x00 0x1D PWM4delMSB 0 0 0 0 pwm4 del11 pwm4 del10 pwm4 del9 pwm4 del8 0x00 0x1E PWM5delLSB pwm5 del7 pwm5 del6 pwm5 del5 pwm5 del4 pwm5 del3 pwm5 del2 pwm5 del1 pwm5 del0 0x00 0x1F PWM5delMSB 0 0 0 0 pwm5 del11 pwm5 del10 pwm5 del9 pwm5 del8 0x00 0x20 PWM6delLSB pwm6 del7 pwm6 del6 pwm6 del5 pwm6 del4 pwm6 del3 pwm6 del2 pwm6 del1 pwm6 del0 0x00 0x21 PWM6delMSB 0 0 0 0 pwm6 del11 pwm6 del10 pwm6 del9 pwm6 del8 0x00 0x22 PWM7delLSB pwm7 del7 pwm7 del6 pwm7 del5 pwm7 del4 pwm7 del3 pwm7 del2 pwm7 del1 pwm7 del0 0x00 0x23 PWM7delMSB 0 0 0 0 pwm7 del11 pwm7 del10 pwm7 del9 pwm7 del8 0x00 0x24 PWM8delLSB pwm8 del7 pwm8 del6 pwm8 del5 pwm8 del4 pwm8 del3 pwm8 del2 pwm8 del1 pwm8 del0 0x00 0x25 PWM8delMSB 0 0 0 0 pwm8 del11 pwm8 del10 pwm8 del9 pwm8 del8 0x00 0x26 PWM9delLSB pwm9 del7 pwm9 del6 pwm9 del5 pwm9 del4 pwm9 del3 pwm9 del2 pwm9 del1 pwm9 del0 0x00 0x27 PWM9delMSB 0 0 0 0 pwm9 del11 pwm9 del10 pwm9 del9 pwm9 del8 0x00 0x28 PWM 10delLSB pwm10 del7 pwm10 del6 pwm10 del5 pwm10 del4 pwm10 del3 pwm10 del2 pwm10 del1 pwm10 del0 0x00 0x29 PW10delMSB 0 0 0 0 pwm10 del11 pwm10 del10 pwm10 del9 pwm10 del8 0x00 0x2A PWM 11delLSB pwm11 del7 pwm11 del6 pwm11 del5 pwm11 del4 pwm11 del3 pwm11 del2 pwm11 del1 pwm11 del0 0x00 0x2B PWM 11delMSB 0 0 0 0 pwm11 del11 pwm11 del10 pwm11 del9 pwm11 del8 0x00 0x2C PWM 12delLSB pwm12 del7 pwm12 del6 pwm12 del5 pwm12 del4 pwm12 del3 pwm12 del2 pwm12 del1 pwm12 del0 0x00 0x2D PW12delMSB 0 0 0 0 pwm12 del11 pwm12 del10 pwm12 del9 pwm12 del8 0x00 0x2E PWM 13delLSB pwm13 del7 pwm13 del6 pwm13 del5 pwm13 del4 pwm13 del3 pwm13 del2 pwm13 del1 pwm13 del0 0x00 0x2F PW13delMSB 0 0 0 0 pwm13 del11 pwm13 del10 pwm13 del9 pwm13 del8 0x00 NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 47 of 52 05-Feb-2019 0x30 PWM 14delLSB pwm14 del7 pwm14 del6 pwm14 del5 pwm14 del4 pwm14 del3 pwm14 del2 pwm14 del1 pwm14 del0 0x00 0x31 PWM- 14delMSB 0 0 0 0 pwm14 del11 pwm14 del10 pwm14 del9 pwm14 del8 0x00 0x32 PWM 15delLSB pwm15 del7 pwm15 del6 pwm15 del5 pwm15 del4 pwm15 del3 pwm15 del2 pwm15 del1 pwm15 del0 0x00 0x33 PWM- 15delMSB 0 0 0 0 pwm15 del11 pwm15 del10 pwm15 del9 pwm15 del8 0x00 0x34 PWM 16delLSB pwm16 del7 pwm16 del6 pwm16 del5 pwm16 del4 pwm16 del3 pwm16 del2 pwm16 del1 pwm16 del0 0x00 0x35 PWM- 16delMSB 0 0 0 0 pwm16 del11 pwm16 del10 pwm16 del9 pwm16 del8 0x00 0x36 LOCKUN- LOCK Magic Byte 0x00 0x37 PWM1htLSB pwm1 ht7 pwm1 ht6 pwm1 ht5 pwm1 ht4 pwm1 ht3 pwm1 ht2 pwm1 ht1 pwm1 ht0 0x00 0x38 PWM1htMSB 0 0 0 0 pwm1 ht11 pwm1 ht10 pwm1 ht9 pwm1 ht8 0x00 0x39 PWM2htLSB ht pwm2 ht6 pwm2 ht5 pwm2 ht4 pwm2 ht3 pwm2 ht2 pwm2 ht1 pwm2 ht0 0x00 0x3A PWM2htMSB 0 0 0 0 pwm2 ht11 pwm2 ht10 pwm2 ht9 pwm2 ht8 0x00 0x3B PWM3htLSB pwm3 ht7 pwm3 ht6 pwm3 ht5 pwm3 ht4 pwm3 ht3 pwm3 ht2 pwm3 ht1 pwm3 ht0 0x00 0x3C PWM3htMSB 0 0 0 0 pwm3 ht11 pwm3 ht10 pwm3 ht9 pwm3 ht8 0x00 0x3D PWM4htLSB pwm4 ht7 pwm4 ht6 pwm4 ht5 pwm4 ht4 pwm4 ht3 pwm4 ht2 pwm4 ht1 pwm4 ht0 0x00 0x3E PWM4htMSB 0 0 0 0 pwm4 ht11 pwm4 ht10 pwm4 ht9 pwm4 ht8 0x00 0x3F PWM5htLSB pwm5 ht7 pwm5 ht6 pwm5 ht5 pwm5 ht4 pwm5 ht3 pwm5 ht2 pwm5 ht1 pwm5 ht0 0x00 0x40 PWM5htMSB 0 0 0 0 pwm5 ht11 pwm5 ht10 pwm5 ht9 pwm5 ht8 0x00 0x41 PWM6htLSB pwm6 ht7 pwm6 ht6 pwm6 ht5 pwm6 ht4 pwm6 ht3 pwm6 ht2 pwm6 ht1 pwm6 ht0 0x00 0x42 PWM6htMSB 0 0 0 0 pwm6 ht11 pwm6 ht10 pwm6 ht9 pwm6 ht8 0x00 0x43 PWM7htLSB pwm7 ht7 pwm7 ht6 pwm7 ht5 pwm7 ht4 pwm7 ht3 pwm7 ht2 pwm7 ht1 pwm7 ht0 0x00 0x44 PWM7htMSB 0 0 0 0 pwm7 ht11 pwm7 ht10 pwm7 ht9 pwm7 ht8 0x00 0x45 PWM8htLSB pwm8 ht7 pwm8 ht6 pwm8 ht5 pwm8 ht4 pwm8 ht3 pwm8 ht2 pwm8 ht1 pwm8 ht0 0x00 0x46 PWM8htMSB 0 0 0 0 pwm8 ht11 pwm8 ht10 pwm8 ht9 pwm8 ht8 0x00 NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 48 of 52 05-Feb-2019 0x47 PWM9htLSB pwm9 ht7 pwm9 ht6 pwm9 ht5 pwm9 ht4 pwm9 ht3 pwm9 ht2 pwm9 ht1 pwm9 ht0 0x00 0x48 PWM9htMSB 0 0 0 0 pwm9 ht11 pwm9 ht10 pwm9 ht9 pwm9 ht8 0x00 0x49 PWM10htLSB pwm10 ht7 pwm10 ht6 pwm10 ht5 pwm10 ht4 pwm10 ht3 pwm10 ht2 pwm10 ht1 pwm10 ht0 0x00 0x4A PWM10htMSB 0 0 0 0 pwm10 ht11 pwm10 ht10 pwm10 ht9 pwm10 ht8 0x00 0x4B PWM11htLSB pwm11 ht7 pwm11 ht6 pwm11 ht5 pwm11 ht4 pwm11 ht3 pwm11 ht2 pwm11 ht1 pwm11 ht0 0x00 0x4C PWM11htMSB 0 0 0 0 pwm11 ht11 pwm11 ht10 pwm11 ht9 pwm11 ht8 0x00 0x4D PWM12htLSB pwm12 ht7 pwm12 ht6 pwm12 ht5 pwm12 ht4 pwm12 ht3 pwm12 ht2 pwm12 ht1 pwm12 ht0 0x00 0x4E PWM12htMSB 0 0 0 0 pwm12 ht11 pwm12 ht10 pwm12 ht9 pwm12 ht8 0x00 0x4F PWM13htLSB pwm13 ht7 pwm13 ht6 pwm13 ht5 pwm13 ht4 pwm13 ht3 pwm13 ht2 pwm13 ht1 pwm13 ht0 0x00 0x50 PWM13htMSB 0 0 0 0 pwm13 ht11 pwm13 ht10 pwm13 ht9 pwm13 ht8 0x00 0x51 PWM14htLSB pwm14 ht7 pwm14 ht6 pwm14 ht5 pwm14 ht4 pwm14 ht3 pwm14 ht2 pwm14 ht1 pwm14 ht0 0x00 0x52 PWM14htMSB 0 0 0 0 pwm14 ht11 pwm14 ht10 pwm14 ht9 pwm14 ht8 0x00 0x53 PWM15htLSB pwm15 ht7 pwm15 ht6 pwm15 ht5 pwm15 ht4 pwm15 ht3 pwm15 ht2 pwm15 ht1 pwm15 ht0 0x00 0x54 PWM15htMSB 0 0 0 0 pwm15 ht11 pwm15 ht10 pwm15 ht9 pwm15 ht8 0x00 0x55 PWM16htLSB pwm16 ht7 pwm16 ht6 pwm16 ht5 pwm16 ht4 pwm16 ht3 pwm16 ht2 pwm16 ht1 pwm16 ht0 0x00 0x56 PWM16htMSB 0 0 0 0 pwm16 ht11 pwm16 ht10 pwm16 ht9 pwm16 ht8 0x00 0x57 ASICIDLSB asic_id0 rev. nr. 0x00 0x58 ASICIDMSB asic_id2 asic_id1 0x00 0x59 Not used 0x00 0x60 STATUS no_sync stat ot stat open short_bist vcnt underflow short2 short1 power_ good 0x00 0x61 PLLmultiMSB PLL Multi15 PLL Multi14 PLL Multi13 PLL Multi12 PLL Multi11 PLL Multi10 PLL Multi9 PLL Multi8 0x00 0x62 PLLmultiLSB PLL Multi7 PLL Multi6 PLL Multi5 PLL Multi4 PLL Multi3 PLL Multi2 PLL Multi1 PLL Multi0 0x00 0x63 SHORT_ BIST_CTRL1 0 0 0 bist _retrial bist _steptime autooff_ BIST bist_wait 0x02 0x64 SHORT_BIST_ MAXSTEP bist maxstep7 bist maxstep6 bist maxstep5 bist maxstep4 bist maxstep3 bist maxstep2 bist maxstep1 bist maxstep0 0xFF 0x65 SHORT_ BIST_CTRL2 0 0 comp _retrial autotoff _comp comp_level 0x0A NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 49 of 52 05-Feb-2019 0x6C CompReg_1 Comp Reg8 Comp Reg7 Comp Reg6 Comp Reg5 Comp Reg4 Comp Reg3 Comp Reg2 Comp Reg1 0x00 0x6D CompReg_2 Comp Reg16 Comp Reg15 Comp Reg14 Comp Reg13 Comp Reg12 Comp Reg11 Comp Reg10 Comp Reg9 0x00 Note 1. Addresses from 0x66 to 0x6b and above 0x6d are for factory test only. DO NOT WRITE! Table 6: Shows an overview of the Register Map NOT RECOMMENDED FOR NEW DESIGNS

10 Physical Dimensions

Figure 10.1 : QFN-48 package outline drawing NOT RECOMMENDED FOR NEW DESIGNS

16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 51 of 52 05-Feb-2019 Part Number Ordering Code Options Package Description AS3820A AS3820A-ZQFT 16 Channel White LED Controller for LCD Backlight 48-Pin QFN Tape & Reel1 AS3820E AS3820E-ZQFT 16 Channel White LED Controller for LCD Backlight Direct PWM Mode Activated 48-Pin QFN Tape & Reel1 Note 1. Tape & Reel packing quantity is 4,000/reel. Minimum packing quantity is 4,000. Note 2. Additional features and options may be available; contact Dialog Semiconductor. NOT RECOMMENDED FOR NEW DESIGNS

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any information source outside of Dialog Semiconductor. Dialog Semiconductor reserves the right to change without notice the information published in this document, including without limitation the specification and the design of the related semiconductor products, software and applications. Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further testing or modification. Unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and Dialog Semiconductor excludes all liability in this respect. Customer notes that nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications referred to in this document. Such license must be separately sought by customer with Dialog Semiconductor. All use of Dialog Semiconductor products, software and applications referred to in this document are subject to Dialog Semiconductor’s Standard Terms and Conditions of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated. Dialog and the Dialog logo are trademarks of Dialog Semiconductor plc or its subsidiaries. All other product or service names are the property of their respective owners. © 2019 Dialog Semiconductor. All rights reserved. RoHS Compliance Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request. Contacting Dialog Semiconductor United Kingdom (Headquarters) Dialog Semiconductor (UK) LTD Phone: +44 1793 757700 Germany Dialog Semiconductor GmbH Phone: +49 7021 805-0 The Netherlands Dialog Semiconductor B.V. Phone: +31 73 640 8822 Email info_pcbg@diasemi.com North America Dialog Semiconductor Inc. Phone: +1 408 845 8500 Japan Dialog Semiconductor K. K. Phone: +81 3 5769 5100 Taiwan Dialog Semiconductor Taiwan Phone: +886 281 786 222 Web site: www.dialog-semiconductor.com Hong Kong Dialog Semiconductor Hong Kong Phone: +852 2607 4271 Korea Dialog Semiconductor Korea Phone: +82 2 3469 8200 China (Shenzhen) Dialog Semiconductor China Phone: +86 755 2981 3669 China (Shanghai) Dialog Semiconductor China Phone: +86 21 5424 9058 AS3812 16-Channel White LED Controller for LCD Backlight Rev. 1.1Datasheet © 2019 Dialog Semiconductorwww.dialog-semiconductor.com 52 of 52 05-Feb-2019 NOT RECOMMENDED FOR NEW DESIGNS

Selected Specification

Dialog Semiconductor AS3820 overview.

Summary

16-Channel White LED Controller for LCD Backlight

Description

16-Channel White LED Controller for LCD Backlight

Source title AS3820 Datasheet(PDF) - Dialog Semiconductor

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