AS3677 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 68
Technical content
The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com
1 General Description
other Li+ battery powered devices. Dynamic Backlight Control - DBC) input. over the -30ºC to +85ºC temperature range. Figure 1. Function Diagram
2 Key Features
3 Applications
Figure 2. Application Circuit AS3677
4 Pinout
4.1 Pin Assignments
Figure 3. Pin Assignments (Top View)
4.2 Pin Description
Table 1. Pin Description B3 VBAT Positive supply pad - Connect to battery.
D2 CLK Digital input - Clock input for serial interface.
5 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability.
6 Electrical Characteristics
Table 2. Absolute Maximum Ratings Table 3. General Operating Conditions; typical values are at VBAT=3.7V and 25ºC ISTANDBY Standby Mode Current Current consumption in standby mode.
7 Typical Operating Characteristics
Measured at VBAT=3.7V and TAMB=25ºC unless otherwise specified. Figure 4. DCDC Efficiency vs. Load Current Figure 5. Charge Pump: Efficiency vs. VBAT Figure 6. Charge Pump: Battery current vs. VBAT Figure 7. Current Sink CURR1 vs. V(CURRx) Figure 8. Current Sink RGB1 vs. V(CURRx) Figure 9. LDO Output Voltage VANA vs. Code
Figure 10. LDO Output Voltage VANA vs. Load Figure 11. Charge Pump input and output ripple
8 Detailed Description
8.1 LDO
sensor. Stability is guaranteed with ceramic output capacitors of 100nF ±20% (X5R). The LDO is off by default after start-up. Figure 12. LDO Block Diagram
8.1.1 LDO Registers
Table 4. Electrical Characteristics Table 5. Reg control Register current sinks, the Step Up DC/DC Converter, and low-power mode.
0 LDO is switched off
1 LDO is switched on
8.2 Step Up DC/DC Converter
The Step Up DC/DC Converter is a high-efficiency current mode PWM regulator, providing output voltage up to e.g. 25V/50mA. A constant switching-frequency results in a low noise on the supply and output voltages. Figure 13. Step Up DCDC Converter Internal Block Diagram Table 6. LDO Voltage Register This register sets the output voltage (VANA) for the LDO. Controls LDO voltage selection. Table 7. Step Up DC/DC Converter Parameters
converter. The total startup time for an output voltage of e.g. 26V is less than 2ms.
8.2.1 Feedback Selection
Register DCDC control1 and DCDC control2 selects the type of feedback for the Step Up DC/DC Converter. current at the feedback path can be supported. (unregulated) paths or enable the register bit step_up_fb_auto.
8.2.2 Over voltage Protection
and afterwards step_up_on=1. The voltage rating of the external components must be chosen to fit to the software setting of step_up_vmax2.
- It is recommended to leave step_up_fb_auto=1 (default) all the times.
- If the voltage is the DCDC overvoltage protection is chosen above the voltage ratings of the external com-
ponents, permanent damage might result. Table 7. Step Up DC/DC Converter Parameters (Continued)
8.2.3 PCB Layout Hints
ensures that local high-frequency currents will not flow to the battery.
8.2.4 Step up Registers
Table 8. Reg control Register Table 9. DCDC control1 Register This register controls the Step Up DC/DC Converter.
01 MHz
01 CURR1 feedback enabled
10 CURR2 feedback enabled
11 CURR6 feedback enabled
Table 10. DCDC control2 Register
0 Accurate output voltage, more ripple
1 Elevated output voltage, less ripple
8.3 Charge Pump
The Charge Pump uses the external flying capacitor C4 to generate output voltages higher than the battery voltage.
- battery current = output current.
Note: The connections of the external capacitors C4 and C5 should be kept as short as possible.
0 Normal current limit
0 No overvoltage triggered
1 Overvoltage triggered; this bit is automatically
pump (currX_on_cp must be 0). Table 11. Charge Pump External Components Table 10. DCDC control2 Register (Continued)
The maximum voltage on the flying capacitor C4 is VBAT.
8.3.1 Charge Pump Mode Switching
higher mode is selected after the debounce time. Table 12. Charge Pump Characteristics
Figure 14. Automatic Mode Switching
8.3.2 Soft Start
charge pump on and also at each switching condition. This precaution reduces electromagnetic radiation significantly.
8.3.3 Unused Charge Pump
should be left open and keep register cp_on and cp_auto_on at 0 (default value).
8.3.4 Charge Pump Registers
Table 13. Reg control Register This register controls the Charge Pump.
0 Set Charge Pump into 1:1 mode (off state) unless
1 Enable manual or automatic mode switching
Table 14. CP control Register
01 M H z
10 Manual Mode switching; register cp_mode defines
0 Mode switching debounce timer is always 240µs
0 Charge Pump is switched on/off with cp_on
Table 15. CP mode Switch1 Register Table 16. CP mode Switch2 Register Table 17. Curr low voltage status1 Register
8.4 Current Sinks
The AS3677 contains three general purpose current sinks intended to control backlight LEDs. uration) see Feedback Selection on page 11. Table 18. Curr low voltage status2 Register Table 19. Current Sink Function Overview
Figure 15. Internal processing of the different signals
8.4.1 Unused Current Sinks
Unused current sinks can be left open or used as ADC inputs (see Analog-to-Digital Converter on page 50).
8.4.2 High Voltage Current Sinks CURR1, CURR2, CURR6
The high voltage current sinks have a resolution of 8 bits. Table 20. HV Current Sinks Characteristics Table 21. Curr1 current Register This register controls the High voltage current sink current. Table 22. Curr2 current Register This register controls the High voltage current sink current.
Table 23. Curr6 current Register This register controls the High voltage current sink current. Table 24. curr12 control Register Table 25. curr rgb control Register This register select the mode of the current sinks CURR6.
8.4.3 Current Sinks RGB1, RGB2, RGB3
These current sinks have a resolution of 8 bits and can sink up to 25.5mA. Table 26. Current Sinks RGB1, RGB2, RGB3 Parameters Table 27. curr rgb control Register
8.4.4 LED Pattern Generator
each bit). The pattern itself can be started every second, every 2nd, 3rd up to 7th second3. 0 and their programmed current. on the pattern (set register cp_auto_on on page 16=1) to reduce the overall current consumption. Table 28. Rgb1 current Register This register controls the RGB current sink current. Table 29. Rgb2 current Register This register controls the RGB current sink current. Table 30. Rgb3 current Register This register controls the RGB current sink current.
- All times can be extended by a factor of 8 by setting pattern_slow=1 (this result in a delay of up to 56s)
With the AS3677 smooth fade-in and fade-out effects can be automatically generated. Figure 19. Soft dimming example Waveform for CURR30-32 Figure 20. Soft dimming example Waveform for CURR30-32 Table 31. Pattern data0...Pattern data3 Registers This registers contains the pattern data for the current sinks.
- Update any of the pattern register only if none of the current sources is connected to the pattern generator
0 R/W Pattern data0
Table 32. Pattern control Register
0 Pattern generator directly control current
Table 33. Gpio current Register Table 34. Pattern End Register
- pattern_end toggles whenever the AS3677 is in active mode (see Section 8.11 Operating Modes on page 58)
even if no pattern data has been setup. Table 35. LED Pattern timing
8.4.5 PWM Generator
the current sinks and therefore depending on its duty cycle change the brightness of an attached LED.
- Even by setting 000 for pattern delay, there is a small delay before the new patterns starts.
currX_adder must not exceed 255). dimming 0). This can be used to identify the exact time, when up/down dimming is finished. Table 36. PWM Dimming Table
Table 37. Pwm control Register 01b logarithmic up dimming (codes are increased).
Table 38. Pwm code Register This register controls the Pwm code. Table 39. Adder Current 1 Register Table 40. Adder Current 2 Register Table 41. Adder Current 3 Register
8.4.6 ALS - Ambient Light Sensing
cut-off frequencies adjustable from 0.25Hz to 32Hz (amb_filter_up and amb_filter_down). This filtered signal can be readout from the register amb_result<7:0>. Table 42. Adder Enable 2 Register
0 Normal Operation of the current source
Table 43. Adder Enable 1 Register
- adc_select=02h (select ALS/GPIO1 input)
The calculations are done every 1ms resulting in a flicker-free 1000Hz update rate of the current sources. Note: The ADC is switched off between conversion to save power.
- This allows a step response to a small change in the input signal (e.g. for keyboard backlight).
Table 44. ALS Parameters
Figure 24. Ambient Light Sensor and Interrupt Logic internal circuit Table 45. ALS control Register
0 Group output is enabled (S/H = sampling)
1 Groups outputs on hold (S/H = hold)
Table 46. ALS filter Register Table 47. ALS offset Register Table 45. ALS control Register (Continued)
Table 48. ALS result Register Table 49. ALS curr12 group Register
00 None - no ambient light sensor control
01 Group 1
10 Group 2
11 Group 3
Table 50. ALS rgb group Register
Table 51. ALS group 1 Y0 Register Table 52. ALS group 1 Y3 Register Table 53. ALS group 1 X1 Register Table 54. ALS group 1 K1 Register Table 55. ALS group 1 X2 Register Table 56. ALS group 1 K2 Register Table 50. ALS rgb group Register (Continued)
Table 57. ALS group 2 Y0 Register Table 58. ALS group 2 Y3 Register Table 59. ALS group 2 X1 Register Table 60. ALS group 2 K1 Register Table 61. ALS group 2 X2 Register Table 62. ALS group 2 K2 Register Table 63. ALS group 3 Y0 Register Table 64. ALS group 3 Y3 Register
Table 65. ALS group 3 X1 Register Table 66. ALS group 3 K1 Register Table 67. ALS group 3 X2 Register Table 68. ALS group 3 K2 Register Table 69. ALS group output 1 Register Table 70. ALS group output 2 Register Table 71. ALS group output 3 Register Table 72. ALS range high interrupt threshold Register
8.4.7 DLS(=DBC) - Dynamic Luminance Scaling Input
pensate for a reduced brightness backlight.
- Digital DLS Mode - selected by dls_analog=0: The input signal from pins DLS1 and DLS2 are controlling the
source with the configured current. This operating mode is compatible to the AS3676 processing of DLS.
- Analog DLS Mode - selected by dls_analog=1: In this operating mode, the input signals form DLS1 and DLS2
Table 73. ALS range low interrupt threshold Register Table 74. Interrupt Status Register
- Read - self clear. The register automatically clears it content after readout. This avoids any lost interrupts.
in noise sensitive systems - especially if the connection to the LED used long wires. at very low current operation). RGB1, RGB2 and RGB3 can only use ‘digital’ DLS - the register dls_analog does have no influence.
- The input signal from pins DLS1 and DLS2 are feed into the digital filter. A logic ‘L’ is converted into ‘0.000’ and
a logic ‘H’ is converted into ‘1.000’.
- The digital filter processes this signal. The filter itself is implemented as a 4th order low pass filter with fixed
coefficients. Its 3dB cut-off frequency is set to fDLS_FILTER.
- The output signal (fixed comma binary 8 bit signal) is multiplied by the individual current setting.
- From this 8 x 8 multiplication (16bit result), the 8 MSBs are used.
This value is converted with a current DAC into a current, which controls the LED.
8.4.8 Unused DLS Input Pins
The pins DLS1 and DLS2 should be connected to VSS if not used.
8.4.9 DLS Internal Processing
Table 75. DLS Input Parameters
1.38 VBAT V
Figure 25. DLS (Dynamic Luminance Scaling) internal circuit shown for a single current sink Table 76. DLS mode control1 Register
0 RGB1 current sink is not combined with DLS
11 RGB1 current sink is combined with DLS (only
0 RGB2 current sink is not combined with DLS
11 RGB2 current sink is combined with DLS (only
0 RGB3 current sink is not combined with DLS
11 RGB3 current sink is combined with DLS (only
- When this bit is set, do not use the internal PWM generator for this current source at the same time.
Table 77. DLS mode control2 Register
0 CURR1 current sink is not combined with DLS
11 CURR1 current sink is combined with DLS
0 CURR2 current sink is not combined with DLS
11 CURR2 current sink is combined with DLS
0 CURR2 uses DLS1 as input
1 CURR2 uses DLS2 as input
0 CURR6 uses DLS1 as input
1 CURR6 uses DLS2 as input
0 CURR6 current sink is not combined with DLS
1 CURR6 current sink is combined with DLS
- When this bit is set, do not use the internal PWM generator for this current source at the same time.
Table 76. DLS mode control1 Register (Continued)
8.5 General Purpo se Input / Output
Table 78. GPIO Pin Function Summary
Figure 26. GPIOs and VANA Blockdiagram
8.5.1 Unused GPIO and digital Input Pins
to VSS, INT can be left open.
8.5.2 GPIO and Digital Inputs Characteristics
Table 79. GPIO and digital inputs DC Characteristics
8.5.3 GPIO Registers
1.38 VANA V
- Limited by LDO driving capability - see LDO on page 9
Table 80. GPIO output 2 Register This register controls GPIO3 outputs. of any other bit setting e.g., gpio1_mode Table 82. Table 81. GPIO signal 2 Register This register controls GPIO3 outputs.
Table 82. GPIO control Register This register controls GPIO3 and GPIO31 pin functions.
00 Input only
01 Output (push and pull)
10 Output (open drain, only push; only NMOS is
11 Output (open drain, only pull; only PMOS is
00 None
01 Pulldown
10 Pullup
11 ADC input (gpio1_mode = XX); recommended
11 ADC input (gpio2_mode = XX); recommended
Table 83. GPIO control 3 Register This register enables low current mode for GPIO3s.
11 ADC input (gpio3_mode = XX); recommended
Table 84. GPIO driving cap Register This register enables low current mode for GPIO3s.
1 Iout /4
Table 83. GPIO control 3 Register (Continued) This register enables low current mode for GPIO3s.
8.6 LED Test
Figure 27. LED Function Testing can then be disabled (to avoid unnecessary currents).
8.6.1 Function Testing for single LE Ds connected to the Charge Pump
Table 85. Function Testing for LEDs connected to the Charge Pump
2 Switch on the current sink for the LED to be tested
3 Measure with the ADC the voltage on CPOUT Reg 26h ≤ 95h (adc_select=CPOUT,start ADC)
8.6.2 Function Testing example for LEDs connected to the DCDC
8.7 Analog-to-Digital Converter
4 Measure with the ADC the voltage on the switched
5 Switch off the current sink for the LED to be tested Reg 02h ≤ 00h (rgb1_mode = off)
7 Do the same procedure for the next LED starting
8 Switch off the charge pump
Table 86. Function Testing procedure for LEDs connected to the DCDC
3 Set step_up_vmax to fit the external components
4 Switch on the DCDC converter Reg 00h ≤ 08h
5 Wait 2ms (dcdc startup time and some margin)
6 Measure the voltage on CURR1 Reg 26h ≤ 98h (adc_select=CURR1, start ADC;
8 Switch off current sink CURR1 Reg 01h ≤ 00h (curr1_mode=off)
9 Repeat whole procedure for each used LED string
Table 87. ADC Input Ranges, Compliances and Resolution
Table 88. ADC Parameters Table 89. ADC_MSB result Register 6:0 adc_result_msb N/A R ADC results register.
0 Result is ready
1 Conversion is running
Table 90. ADC_LSB result Register Table 91. ADC_control Register 7 start_conversion N/A W Writing a 1 into this bit starts one ADC conversion cycle.
- See Table Table 87 for ADC ranges and resolution.
Table 89. ADC_MSB result Register (Continued)
Figure 28. ADC Circuit
8.8 Power-On Reset
The internal reset is forced if VBAT is low or if both interface pins (CLK, DATA) are low for more than tPOR_DEB (typ. 100ms)5. Then device enters shutdown mode. For details see section Operating Modes on page 58. register contents are set to default. Access by serial interface is possible once the reset thresholds are exceeded.
Figure 29. Zero Power Device Wakeup block diagram
8.8.1 Reset control register
8.9 Temperature Supervision
disabled and the ov_temp flag is set. After decreasing the temperature by THYST operation is resumed. Table 92. Power On Reset Parameters Table 93. Overtemp control Register This register reads and resets the overtemperature flag. Enable Shutdown mode and serial interface reset.
The ov_temp flag can only be reset by first writing a 1 and then a 0 to the register bit rst_ov_temp. Bit ov_temp_on = 1 activates temperature supervision Table 95. It is recommend to leave this bit set (default state).
8.10 Serial Interface
Figure 30. Serial interface block diagram Table 94. Overtemperature Detection Table 95. Overtemp control Register This register reads and resets the overtemperature flag. Activates/deactivates device temperature supervision.
1 Temperature supervision is enabled
The clock line CLK is never held low by the AS3677 (as the AS3677 does not use clock stretching of the bus). 39340011.pdf, Version 2.1, January 2000 for standard and fast mode (no high speed mode).
8.10.1 Serial Interface Features
8.10.2 Device Address Selection
Figure 31. Complete Serial Data Transfer Table 96. Serial Interface Voltages and Timings
Figure 34. Serial Interface Random Read direction after the data transfer from the master. condition is followed by the device-write address and the word address. responds to the data byte with a NOT ACKNOWLEDGE, and issues a STOP condition on the bus. Figure 35. Serial Interface Sequential Read Sequential Read is the extended form of Random Read, as multiple register-data bytes are subsequently transferred. last data byte and subsequently generate the STOP condition. Figure 36. Serial Interface Current Address Read be responded to with an ACKNOWLEDGE from the master.
8.11 Operating Modes
Figure 37. Startup and Operating Mode Selection
9 Register Map
Table 98. Registermap
1 AAh 00h amb_group1
2 ABh 00h amb_group2
3 ACh 00h amb_group3
10.1 External Components
10.2 Layout Recommendations
- GND Planes: Connect the VSS pins (B4, B5) to the low noise GND-plane.
the star point of the low noise GND plane. Do not connect VSS (B4, B5) directly to VSS_DCDC (A4).
- Supplies: The pins VBAT (B3) and VBAT_CP (A3) can be connected directly together. Put a blocking Cap
- DCDC: Put L1, D1, C1 and C2 close together and also close to the pins SW (A5) and VSS_DCDC (A4).
- LDO: Put C3 close to pin VANA (C1)
Table 99. External Components List
- in 1/100 inch (unless otherwise specified)
Figure 38. WL-CSP25 2.2x2.2x0.6mm 5x5 Balls Package Drawing Figure 39. WL-CSP25 2.2x2.2x0.6mm 5x5 Balls Detail Dimensions The coplanarity of the balls is 40µm.
11.1 Tape & Reel Information
Figure 40. Tape & Reel Dimensions
330.0 REF
102.0 REF
The devices are available as the standard products shown in Table 100. Table 100. Ordering Information
www.austriamicrosystems.com/AS3677 1v3-1 67 - 67 AS3677 Datasheet - Ordering Information Copyrights Copyright © 1997-2011, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami- crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 Schloss Premstaetten A-8141 Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact ams AG Technical content still valid