AS3643 AMSCO

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Technical content

The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30

8141 Unterpremstaetten, Austria

Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com

1 General Description

ate in flash / torch / assist (=video) light modes. hardware automatic shutdown if SCL=0 for 100ms. ting down of the device once the system shuts down. over the -30ºC to +85ºC temperature range. Figure 1. Typical Operating Circuit

2 Key Features

3 Applications

4 Pinout

Figure 2. Pin Assignments (Top View) Table 1. Pin Description for AS3643

5 Absolute Maximum Ratings

Table 3. Absolute Maximum Ratings

  1. Depending on actual PCB layout and PCB used measured on demoboard; for peak power dissipation during
  2. PDERATE derating factor changes the total continuous power dissipation (PT) if the ambient temperature is not
  3. Pins LED_OUT1 connected to LED_OUT2 and capacitor CVOUT connected to VOUT1/2 and GND; both GND
  4. Measured on AS3643 Demoboard.

6 Electrical Characteristics

+25ºC, unless otherwise specified. Table 4. Electrical Characteristics

1.26 V VIN V

0.7 VVIN V

Table 4. Electrical Characteristics (Continued)

  1. To improve efficiency at low output currents, the active part of the internal switching transistor PMOS is reduced

improves overall efficiency at low output currents.

  1. Due to slope compensation of the current limit, ILIMIT changes with duty cycle.
  2. The logic input levels VIH and VIL allow for 1.2V or 1.8V supplied driving circuit
  3. A pulldown current of 36µA is equal to a pulldown resistor of 42k at 1.5V
  4. After this period, the first clock pulse is generated.
  5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the

SCL signal) to bridge the undefined region of the falling edge of SCL.

  1. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then

tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

Figure 3. I2C mode Timing Diagram

7 Typical Operating Characteristics

Figure 4. DCDC Efficiency vs. VVIN Figure 5. Application Efficiency (PLED/PVIN) vs. VVIN Figure 6. Battery Current vs. VVIN Figure 7. Efficiency at low currents (300mA) Figure 8. ILED Startup (ILED_OUT=1.0A) Figure 9. IVIN, ILED Startup (ILED_OUT=800mA)

8 Detailed Description

in standby mode, the device automatically enters shutdown mode by keeping SCL low for more than tTIMEOUT1. LED_OUT1/2) it includes several protection and safety functions. Figure 16. Internal circuit Diagram order for the DCDC to return to regulation2.

  1. Following registers are reset to their default value if the timeout expires: out_on=0, ext_torch_on=00,

mode_setting=00, const_v_mode=0.

  1. The actual value of the LED current setting can be readout by the register led_current_actual (see page

26) to allow the camera processor to adopt to the actual operating conditions.

verter can switch into a 1MHz operating mode and maximum duty cycle to improve efficiency for this load condition3. The DCDC converter returns back to its normal 4MHz operating frequency when load or supply conditions change. (see page 26)=0. In this case pulseskip will be used. Figure 17. Internal circuit of 4MHz/1Mhz selection Note: For simplicity Figure 17 shows only a single current sink. mode_setting=00 and ext_torch_on=00. the DCDC converter is stopped, the current sources are disabled and the bit fault_ovp (see page 25) is set6.

  1. Efficiency compared to a 4M Hz only DCDC converter forced to operate with minimum duty cycle.
  2. Applies for all faults except TXMASK event occurred
  3. If overvoltage is reached, but none of the low_vds comparator(s) triggers, VOUT1/2 is still regulated below
  4. In constant voltage mode (5V generation, register bit const_v_mode=1) this fault is disabled.

abled and the bit fault_led_short (see page 25) is set. Figure 18. Short LED detection automatically re-enabled8 once the junction temperature drops below TOVTEMP-TOVTEMPHYST. a TXMASK event happened (pin TXMASK/TORCH=1), the fault register bit fault_txmask (see page 25) is set. fault_timeout is set after the flash has been finished. registers are set to their default state.

  1. To avoid errors in short LED detection for LEDs with a high leakage current
  2. In constant voltage mode ( const_v_mode=1) the DCDC will not be automatically re-enabled.

Figure 19. Device Shutdown and Wakeup the I2C bus. Therefore no additional action is required to leave the shutdown mode and start I2C communication. The purpose of this circuit is an additional security mechanism. automatically enters shutdown. rent consumption for standby mode is identical to shutdown mode.

Table 5. Operating Mode and current settings

  1. SCL low for tTIMEOUT and operating mode is indicator, assist or flash mode then shutdown mode is entered.
  2. The MSB bit of this register not used to protect the LED; therefore the maximum assist / torch light current = half
  3. The low current mode is a general purpose PWM mode to drive less current through the LED in average, but

LSBs of led_current are used the maximum current is limited to 1/4 of the maximum flash current.

by ext_torch_on=01), the flash current is reduced to flash_txmask_current if TXMASK/TORCH=1. reduced to flash_txmask_current if vin_low_v_shutdown=0. current is 8µs/LSB current change. During the flash pulse the actual used current can be readout by the register led_current_actual. Figure 20. Low Voltage current Reduction Internal Circuit

www.austriamicrosystems.com/AS3643 1.5-4 18 - 33 AS3643 Datasheet, Confidential - Detailed Description I2C Serial Data Bus The AS3643 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The AS3643 operates as a slave on the I2C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The AS3643 works in both modes. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 27): Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy Both data and clock lines remain HIGH. Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. ams AG Technical content still valid

Figure 27. Data Transfer on I2C Serial Bus

  1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the

byte. Data is transferred with the most significant bit (MSB) first.

  1. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave

released. Data is transferred with the most significant bit (MSB) first.

  1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each

write bit, the master transmits a register address to the AS3643. This sets the register pointer on the AS3643. The master may then transmit zero or more bytes of data, with the AS3643 acknowledging each byte received. to terminate the data write.

  1. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode.

address, which is 0110000, followed by the direction bit (R/W), which, for a read, is 1.

10 After receiving and

  1. The address for writing to the AS3643 is 60h = 01100000b

Table 6. ChipID Register Table 7. Current Set1 Register

Table 9. TXMask Register

  1. The MSB bit of this register not used to protect the LED; therefore the maximum current = half the maximum

Table 10. Low Voltage Register

0 Normal operation defined by mode_setting

Table 11. Flash Timer Register

  1. Internal calculation for codes above 80h: flash timeout [ms] = (flash_timeout-127) * 8 + 256 [ms]

Table 12. Control Register

  1. The MSB bit of this register not used to protect the LED; therefore the maximum assist light current = half the

Table 13. Strobe Signalling Register

0 STROBE input is edge sensitive

1 STROBE input is level sensitive

0 STROBE input disabled

1 STROBE input enabled

Table 14. Fault Register

1 Flash timeout exceeded

1 Junction temperature limit has been exceeded

1 A shorted LED is detected (pin LED_OUT1/2)

1 An overvoltage condition is detected (pin VOUT)

  1. R/sC = Read, self clear; after readout the register is automatically cleared

Table 15. PWM and Indicator Register

0 Pulseskip operation is allowed for all modes -

Table 17. Minimum LED Current Register

  1. As the internal change of this register is asynchronous to the readout, it is recommended to readout the register

after the flash pulse. The register will store the minimum current through the LED after e.g. a previous flash. This current can be used for a subsequent flash pulse for a safe operating range.

  1. This register is only set if an actual current reduction happens (fault_uvlo (see page 25)=1) otherwise

Table 18. Actual LED Current Register

  1. As the internal change of this register is asynchronous to the readout, it is recommended to readout the register

twice and compare the results.

Table 21. Register Map 1

9 Application Information

capacitors are required for input decoupling and should be located as close to the device as is practical. supply voltage. Larger capacitor values (C) may be used without limitations. Add a smaller capacitor in parallel to the input pin VIN (e.g. Murata GRM155R61C104, >50nF @ 3V, 0402 size). Table 22. Recommended Input Capacitor Table 23. Recommended Output Capacitor

  1. Use only for VLED < 3.75V

very low DC resistance (DCR) to reduce the I2R power losses - high DCR values will reduce efficiency. If a different inductor is chosen, ensure similar DCR values and at least0.6µH inductance at ILIMIT. Table 24. Recommended Inductor

  1. Do not exceed maximum ISATURATION - can be ensured by setting coil_peak (will limit LED current)
  2. Flash cycle limit: 150ms on, 500ms off; repeat maximum 50 times.(if used with default coil_peak=0b (2A))
  3. Set current limit to 2A ()coil_peak=10b) - can limit maximum output current.

Figure 33. WL-CSP13 Marking Figure 34. WL-CSP13 Package Dimensions The coplanarity of the balls is 40µm.

The devices are available as the standard products shown in Table 25. Note: All products are RoHS compliant and austriamicrosystems green. Table 25. Ordering Information

www.austriamicrosystems.com/AS3643 1.5-4 33 - 33 AS3643 Datasheet, Confidential - Ordering Information Copyrights Copyright © 1997-2012, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami- crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 Schloss Premstaetten A-8141 Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact ams AG Technical content still valid