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- Manufacturer or author: Provided By digicamel.com
- PDF pages: 51
Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pin Assignments
- 4.1 Pin Descriptions
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 7 Typical Operating Characteristics
- 8 Detailed Description
- 8.1 Audio Line Input
- 8.1.1 Gain Stage
- 8.1.2 Parameter
- 8.2 Microphone Input
- 8.2.1 Gain Stage & Limiter
- 8.2.2 Supply
- 8.2.3 Parameter
- 8.3 Headphone Output
- 8.3.1 Input Multiplexer
- 8.3.2 No-Pop Function
- 8.3.3 No-Clip Function
- 8.3.4 Over-Current Protection
- 8.3.5 Parameter
- 8.4 Operational Amplifier
- 8.4.1 Parameter
- 8.5 SYSTEM
- 8.5.1 Power Up/Down Conditions
- 8.5.2 Start-up Sequence
- 8.5.3 Mode Switching
- 8.5.4 Status Indication
- 8.6 VNEG Charge Pump
- 8.6.1 Parameter
- 8.7 OTP Memory & Internal Registers
- 8.7.1 Register & OTP Memory Configuration
- 8.7.2 OTP Fuse Burning
- 8.8.1 Protocol
- 8.8.2 Parameter
- 9 Register Description
- 10 Application Information
- 11 Package Drawings and Markings
- 12 Ordering Information
Low Power Ambient Noise-Ca ncelling Speaker Driver www.austriamicrosystems.com Revision 1.02 1 - 51
1 General Description
The AS3400/10/30 are speaker driver with Ambient Noise Cancelling function for handsets, headphones or ear pieces. It is intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise. The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures. An internal OTP-ROM can be optionally used to store the microphones gain calibration settings. The AS3400/10/30 can be used in different configurations for best trade-off of noise cancellation, required filtering functions and mechanical designs. The simpler feed-forward topology is used to effectively reduce low frequency background noise. The feed-back topology with either 1 or 2 filtering stages can be used to reduce noise for a larger frequency range, and to even implement transfer functions like speaker equalization, Baxandall equalization, high/low shelving filter and to set a predefined loop bandwidth. The filter loop is optimized by the user for specific handset electrical and mechanical designs by dimensioning simple R, C components. Most handset implementations will make use of a single noise detecting microphone. Two microphones could be used to allow for increased flexibility of their location in the handset mechanical design. Using the bridged mode allows to even drive high impedance headsets.
2 Key Features
128 gain steps @ 0.375dB and MUTE with AGC Differential, low noise microphone amplifier Single ended or differential mode Improved supply for electret microphone MIC gain OTP programmable High Efficiency Headphone Amplifier 2x34mW, 0.1% THD @ 16Ω, 1.5V supply, 100dB SNR Bridged mode for e.g. 300Ω loads Click and pop less start-up and mode switching Line Input Volume control via serial interface or volume pin 64 steps @ 0.75dB and MUTE, pop-free gain setting Single ended stereo or mono differential mode ANC processing Feed-forward cancellation Feed-back cancellation with filter loop transfer function definable via simple RC components Simple in production SW calibration 12-30dB noise reduction (headset dependent) 10-2000Hz wide frequency active noise attenuation (headset dependent) Monitor Function For assisted hearing, i.e. to monitor announcements Fixed (OTP prog.) ambient sound amplification to compensate headphone passive attenuation Volume controlled ambient sound amplification mixed with fixed (OTP prog.) attenuation of LineIn Incremental Functions ANC with or without music on the receiving path Improved dynamic range playback OTP ROM for automatic trimming during production (4 times programbable) Performance Parameter 5/3.8mA @ 1.5V stereo/mono ANC; <1µA quiescent Extended PSRR for 217Hz Interfaces 2-wire serial control mode & volume inputs Calibration via Line-In or 2-wire serial interface (patent pending) Single cell or fixed 1.0-1.8V supply with internal CP Package AS3400, AS3410 QFN24 [4x4mm] 0.5mm pitch AS3430 QFN32 [5.x5mm] 0.5mm pitch
3 Applications
The devices are ideal for Ear pieces, Headsets, Hands-Free Kits, Mobile Phones, and Voice Communicating Devices.
4 Pin Assignments
Note: Pin assignment may change in preliminary data sheets. Figure 5. Pin Assignments (T op View)
24 QMICL
23 VNEG
22 CPN
21 GND
20 CPP
19 VBAT
32 QOP1L
31 IOP2L
30 QOP2L
29 VNEG
28 CPN
27 GND
26 CPP
4.1 Pin Descriptions
Note: Pin description may change in preliminary data sheets. Table 1. Pin Description for AS3400 AS3410 AS3430
5 Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
- Depending on actual PCB layout and PCB used
6 Electrical Characteristics
Table 3. Electrical Characteristics
7 Typical Operating Characteristics
VBAT = +1.5V, TA = +25ºC, unless otherwise specified. Figure 6. LIN to HPH: THD+N vs. Output Power Figure 7. VNEG Charge Pump
8 Detailed Description
This section provides a detailed description of the device related components.
8.1 Audio Line Input
The chip features one line input. The blocks can work in mono differential or in stereo single ended mode. eventually given input capacitors.
8.1.1 Gain Stage
The Line In gain stage is designed to have 63 gain steps of 0.75dB with a max gain of 0dB plus MUTE. VOL pin with an ADC converted VOL voltage or UP/DN buttons. In monitor mode, the gain stage can be set to an fixed default attenuation level for reducing the loudness of the music. Figure 12. Line Inputs
8.1.2 Parameter
VBAT=1.5V, TA= 25ºC, unless otherwise specified. Table 4. Line Input Parameter
8.2 Microphone Input
Figure 13. Microphone Input
8.2.1 Gain Stage & Limiter
The Mic GainStage has programmable Gain within -6dB…+41.625dB in 128 steps of 0.375dB. A limiter automatically attenuates high input signals. The AGC has 127 steps with 0.375dB with a dynamic range of the full gain stage. In monitor mode, the gain stage can be set to an fixed (normally higher) gain level or be controlled by the VOL pin.
8.2.2 Supply
the direct battery voltage cannot be used for mic-supply. There are 2 modes. Table 4. Line Input Parameter (Continued)
8.2.3 Parameter
VBAT=1.5V, TA= 25ºC unless otherwise specified. Table 5. Microphone Input Parameter
8.3 Headphone Output
mode the left output is carrying the inverted signal of the right output shown in Figure 15. Figure 14. Headphone Output Single Ended Mode Figure 15. Headphone Output Differential Mode
8.3.1 Input Multiplexer
ANC by only using the line-input gain stage with no other signal on the multiplexer. For the monitor mode, the setting of this input multiplexer can be changed to another source, normally to the microphone.
8.3.2 No-Pop Function
The No-Pop startup of the headphone stage takes 60ms to 120ms dependent on the supply voltage.
8.3.3 No-Clip Function
The headphone output stage gets monitored by comparator stages which detect if the output signal starts to clip. signal with constant amplitude.
8.3.4 Over-Current Protection
8.3.5 Parameter
VBAT=1.5V, TA= 25ºC, unless otherwise specified.
8.4 Operational Amplifier
amplifier stage to perform feed-back ANC or any other additional needed filtering. Figure 16. Operational Amplifiers Table 6. Headphone Output Parameter
8.4.1 Parameter
VBAT=1.5V, TA= 25ºC, unless otherwise specified. Table 7. Headphone Output Parameter
8.5 SYSTEM
The system block handles the power up and power down sequencing, as well as, the mode switching.
8.5.1 Power Up/Down Conditions
8.5.2 Start-up Sequence
The start-up sequence depends on the used mode. In stand-alone mode the sequence runs automatically, in I2C mode the sequence runs till a defined state and waits then for an I2C command. enable bits for headphone, microphone, etc have to be set manually. Figure 17. Stand-Alone Mode Start-Up Sequence Table 8. Power UP Conditions
2 I2C start In I2C mode, a I2C start condition turns on the device
Table 9. Power DOWN Conditions
3 Low Battery Power down if VBAT is lower than the supervisor off-threshold
Figure 18. I2C Mode Start-Up Sequence The total start-up time (inlcuding fade-in of the gain stages) can be reduced from 900ms to 600ms by OTP setting.
8.5.3 Mode Switching
When the chip is in stand-alone mode (no I2C control), the mode can be switched with different levels on the MODE pin. In I2C mode, the monitor mode can be activated be setting the corresponding bit in the system register. Table 10. Operation Modes multiplexer can be set to a different (normally to MIC) source.
8.5.4 Status Indication
off, by setting the PWM to 0%, 25%, 50% or 100% duty cycle of a 50kHz signal. If LOW_BAT is active, ILED switches to blinking with 1Hz, 50% duty cycle and 50% current setting.
8.6 VNEG Charge Pump
audio related blocks. This allows a true-ground headphone output with no more need of external dc-decoupling capacitors.
8.6.1 Parameter
VBAT=1.5V, TA= 25ºC, unless otherwise specified.
8.7 OTP Memory & Internal Registers
gain making it possible to change the gain 3 times for re-calibration or other purposes. When the chip is controlled by a microcontroller via I2C, the OTP memory don’t has to be used.
8.7.1 Register & OTP Memory Configuration
Figure 19 is showing the principal register interaction. Figure 19. Register Access Table 11. Headphone Output Parameter
www.austriamicrosystems.com Revision 1.02 22 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Detailed Description Registers 0x8, 0x9, 0xA, 0xB, 0xC and 0x21 have only effect when the corresponding “REG_ON” bit is set, otherwise the chip operates with the OTP Register settings which are loaded from the OTP fuses at every start-up. All registers settings can be changed several times, but will loose the content on power off. When using the I2C mode, the chip configuration has to be loaded from the microcontroller after every start-up. In stand alone mode the OTP fuses have to be programmed for a permanent change of the chip configuration. A single OTP cell can be programmed only once. Per default, the cell is “0”; a programmed cell will contain a “1”. While it is not possible to reset a programmed bit from “1” to “0”, multiple OTP writes are possible, but only additional unprogrammed “0”-bits can be programmed to “1”. Independent of the OTP programming, it is possible to overwrite the OTP register temporarily with an OTP write command at any time. This setting will be cleared and overwritten with the hard programmed OTP settings at each power-up sequence or by a LOAD operation. The OTP memory can be accessed in the following ways: LOAD Operation. The LOAD operation reads the OTP fuses and loads the contents into the OTP register. A LOAD operation is automatically executed after each power-on-reset. WRITE Operation. The WRITE operation allows a temporary modification of the OTP register. It does not program the OTP. This operation can be invoked multiple times and will remain set while the chip is supplied with power and while the OTP register is not modified with another WRITE or LOAD operation. READ Operation. The READ operation reads the contents of the OTP register, for example to verify a WRITE command or to read the OTP memory after a LOAD command. BURN Operation. The BURN operation programs the contents of the OTP register permanently into the OTP fuses. Don’t use old or nearly empty batteries for burning the fuses. Attention: If you once burn the OTP_LOCK bit, no further programming, e.g. setting additional “0” to “1”, of the OTP can be done. For production, the OTP_LOCK bit must be set to avoid an unwanted change of the OTP content during the livetime of the product.
8.7.2 OTP Fuse Burning
In most stand alone applications, the I2C pins are not accessible. Burning the fuses can be done by switching the line inputs into a special mode to access the chip by I2C over the line input connections. This allows trimming of the microphone gain with no openings in the final housing and so no influence to the acoustic of the headset. This mode is called “Application Trimm” mode, or short “APT”. (Patent Pending) During the application trimm mode LINR has to provide the clock, while LINL has to provide the data for the I2C communication. Please note that the OTP register cannot be accessed directly but have to be enabled before a read or write access. This is independent whether you access the OTP register via the normal I2C pins or in application trimm mode via LINL and LINR. Please refer to the detailed register description to get more information on how the registers can be accessed. To achieve a proper burning of the fuses, the negative supply has to be buffered by applying an external negative supply during burning. This voltage can also be applied to the LINL terminal. An internal switch is connecting LINL and VNEG during the fuse burning. LINR has to provide the clock for burning the fuses. The below flow chart shows the principle steps of the OTP burning process. The application trimm mode can only be entered at a specific timing during the start-up sequence. The device offers the possibility to change microphone gain settings 3 times by using alternative registers. The selection which register set is being used to set the microphone gain is done by the “lock” bits of the corresponding registers. A more detailed description of the individual steps is available in an application note.
Figure 20. OTP Burning Process There is an I2C slave block implemented to have access to 64 byte of setting information.
8.8.1 Protocol
Table 12. 2-Wire Serial Symbol Definition
8.8.2 Parameter
Figure 26. 2-Wire Serial Timing VBAT >=1.4V1, TA=25ºC, unless otherwise specified. Table 13. 2-Wire Serial Parameter
- Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters.
www.austriamicrosystems.com Revision 1.02 27 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Register Description
9 Register Description
T able 14. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 Audio Registers 00-07h reserved 08h MIC_L MIC_MODE 0: StereoSingleEnd 1: MonoDiff MICL_VOL<6:0> 09h MIC_R MIC_REG_ON 0: use reg 30h & 31h 1: use reg 08h & 09h MICR_VOL<6:0> 0Ah LINE_IN LIN_REG_ON 0: use reg 33h and VOL pin 1: use reg 0Ah LIN_MODE 0: StereoSingleEnd 1: MonoDiff LIN_VOL<5:0> 0: MUTE; 0Bh GP_OP_L HP_MUX<1:0> 0: MIC; 1: OP1; 2: OP2; 3: open OP2L<3:0> 0: OP2L inverting mode; OP2L_ON OP1L_ON 0Ch GP_OP_R OP_REG_ON 0: use reg 34h 1: use reg 0Bh & 0Ch HP_MODE 0: StereoSingleEnd 1: MonoDiff OP2R<3:0> 0: OP2R inverting mode; OP2R_ON OP1R_ON 0Dh-0Fh reserved 18h-1Fh reserved System Register 20h SYSTEM Design_Version<3:0> 0100 REG3 F_ON MONITOR_ON CONT_PWRUP PWR_HOLD 21h PWR_SET PWR_REG_ON 0: - 1: use reg 21h ILED<1:0> 0: OFF; 1: 25%; 2: 50%; 3: 100% HP_ON MIC_ON LIN_ON MICS_CP_ON MICS_ON LOW_BAT PWRUP_ COMPLETE 22h-2Fh reserved
www.austriamicrosystems.com Revision 1.02 28 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Register Description OTP Register 10h ANC_L2 TEST_BIT_5 MICL_VOL_OTP2<6:0> 11h ANC_R2 ALT1_LOCK MICR_VOL_OTP2<6:0> 12h ANC_L3 TEST_BIT_6 MICL_VOL_OTP3<6:0> 13h ANC_R3 ALT2_LOCK MICR_VOL_OTP3<6:0> 14h ANC_L4 TEST_BIT_7 MICL_VOL_OTP4<6:0> 15h ANC_R4 ALT3_LOCK MICR_VOL_OTP4<6:0> 16h MICS_CNTR LowBat + 100mV 17h PWRUP SEQ_LOCK FAST_START<4:0> 0: ~900ms; 0Eh: ~600ms LIN_AGC_OFF MIC_AGC_OFF 30h ANC_L TEST_BIT_1 MICL_VOL_OTP<6:0> 31h ANC_R TEST_BIT_2 MICR_VOL_OTP<6:0> 32h MIC_MON MON_MODE 0: fixed volume 1: adj. volume MIC_MON_OTP<6:0> 33h AUDIO_SET VOL_PIN_OFF VOL_PIN_ MODE 0: potentiometer 1: up/down button LIN_MODE_ OTP 0: StereoSingleEnd 1: MonoDiff MIC_MODE_ OTP 0: StereoSingleEnd 1: MonoDiff HP_MODE_ OTP 0: StereoSingleEnd 1: MonoDiff LIN_MON_ATTEN<2:0> 0: no attenuation; 7: MUTE 34h GP_OP HP_MUX_OTP<1:0> 0: MIC; 1: OP1; 2: OP2; 3: - OP2_OTP<3:0> 0: OP2 inverting mode; OP2_ON_OTP OP1_ON_OTP 35h OTP_SYS MAIN_LOCK 0: write reg 30h.. 35h 1: lock reg 30h..35h TEST_BIT_3 MON_HP_MUX<1:0> 0: MIC; 1: OP1; 2: OP2; 3: - ILED_OTP<1:0> 0: OFF; 1: 25%; 2: 50%; 3: 100% MICS_CP_OFF I2C_MODE 3Eh CONFIG_1 EXTBURNCLK 3Fh CONFIG_2 TM34 BURNSW TM_REG34-35 TM_REG30-33 OTP_MODE<1:0> 0: READ; 1: LOAD; 2: WRITE; 3: BURN T able 14. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0
Table 15. MIC_L Register
7 MIC_MODE 0 R/W Selects the microphone input mode
Table 16. MIC_R Register 7 MIC_REG_ON 0 R/W Defines which register s are used for the microphone settings.
Table 17. LINE_IN Register 0Ah. This register is reset at POR. 7 LIN_REG_ON 0 R/W Defines which source is used for the line input settings.
6 LIN_MODE 0 R/W Selects the line input mode
Table 18. GP_OP_L Register
1 OP2L_ON 0 R/W Enables left OP 2
0 OP1L_ON 0 R/W Enables left OP 1
Table 19. GP_OP_R Register 7 OP_REG_ON 0 R/W Defines which register is used for the opamp and HP settings.
6 HP_MODE 0 R/W Selects the line input mode
1 OP2R_ON 0 R/W Enables right OP 2
0 OP1R_ON 0 R/W Enables right OP 1
Table 20. SYSTEM Register This register is reset at a POR.
3 TESTREG_ON 0 R/W 0: normal operation
2 MONITOR_ON 0 R/W Enables the monitor mode
1 CONT_PWRUP 0 R/W Continues the automatic power-up sequence when using the I2C mode
0 PWR_HOLD 1 R/W 0: power up hold is cleared and AFE will power down
Table 21. PWR_SET Register 7 PWR_REG_ON 0 R/W Defines which register is used for the power settings.
6 LOW_BAT x R VBAT supervisor status
5 PWRUP_COMPLETE x R Power-Up sequencer status
Table 22. ANC_L2 Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 TEST_BIT_5 1 R for testing purpose only
Table 23. ANC_R2 Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 ALT1_LOCK 0 R/W 0: additional bits can be fused inside register 10h & 11h
Table 24. ANC_L3 Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 TEST_BIT_6 1 R for testing purpose only
Table 25. ANC_R3 Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 ALT2_LOCK 0 R/W 0: additional bits can be fused inside register 12h & 13h
Table 26. ANC_L4 Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 TEST_BIT_7 1 R for testing purpose only
Table 27. ANC_R4 Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 ALT3_LOCK 0 R/W 0: additional bits can be fused inside register 14h & 15h
Table 28. MICS_CNTR Register
3 LowBat 0 R/W 0: default LowBat value
Table 29. PWRUP_CNTR Register Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 SEQ_LOCK 0 R/W 0: additional bits can be fused inside register 16h & 17h
1 LIN_AGC_OFF 0 R/W 0: Line Input AGC enabled
0 MIC_AGC_OFF 0 R/W 0:Microphone Input AGC enabled
Table 30. ANC_L Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 TEST_BIT_1 1 R for testing purpose only
Table 31. ANC_R Register writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 TEST_BIT_2 1 R for testing purpose only
Table 32. MIC_MON Register
7 MON_MODE 0 R/W 0: monitor mode is working with fixed microphone gain
Table 33. AUDIO_SET Register 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 VOL_PIN_OFF 0 R/W 0: VOL pin is enabled
6 VOL_PIN_MODE 0 R/W 0: VOL pin is in potentiometer mode
000 R/W Volume settings for line input during monitor mode, adjustable in 7 steps of
Table 34. GP_OP Register POR and gets loaded with the OTP fuse contents.
1 OP2_ON 0 R/W 0: OP2 is switched off
0 OPL_ON 0 R/W 0: OP1 is switched off
Table 35. OTP_SYS Register by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
7 MAIN_LOCK 0 R/W 0: additional bits can be fused inside the OTP
6 TEST_BIT_3 1 R for testing purpose only
00 R/W Multiplexes the analog audio signal to HP amp in monitor mode
1 MICS_CP_OFF 0 R/W 0: MICS charge pump is enabled
Table 36. CONFIG_1 Register Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Table 37. CONFIG_2 Register first. This register is reset at POR and gets loaded with the OTP fuse contents.
5 TM34 0 n/a This Register defines the Register bank selection for Register
4 BURNSW 0 n/a 0: BURN switch from LINL to VNEG is disabled
3 TM_REG34-35 0 n/a 0: test mode for Register 34h-35h disabled
2 TM_REG30-33 0 n/a 0: test mode for Register 30h-33h disabled
Figure 27. AS3410 High Performance Application in Bridged Mode for High Impedance Headsets output to get 24mW output power per channel. Also the microphone inputs can be used in differential mode to reduce the noise level. Figure 28. AS3400 Feed-Forward ANC Block Diagram
Figure 29. AS3430 on Music Player with ANC
Figure 30. AS3410 Feed-Forward Application Example
Figure 31. AS3430 Feed-back Application Example
Figure 32. AS3400 Mode Differential Feed Forward Application Example
Figure 33. QFN Marking Table 38. Package Code AYWWZZZ
Figure 34. AS3400, AS3410, 24-pin QFN 0.5mm Pitch
Figure 35. AS3430 32-pin QFN 0.5mm Pitch
www.austriamicrosystems.com Revision 1.02 49 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Revision History
Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 0.1 19.1.2010 pkm initial release 0.2 29.1.2010 pkm updated block diagrams and application schematics 1.0 27.10.2010 hgt update to new datasheet template 1.01 11.11.2010 hgt updated package drawings, QFN markings and operating temperature range 1.02 24.11.2010 hgt inserted register description for MIC_R and updated register table overview
The devices are available as the standard products shown in Table 39. Note: All products are RoHS compliant and austriamicrosystems green. Table 39. Ordering Information
www.austriamicrosystems.com Revision 1.02 51 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Copyrights Copyrights Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact