AS1538_1 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 20
Technical content
1 General Description
and for applications requiring isolation. Figure 1. Block Diagram
2 Key Features
3 Applications
analog-to-digital conversion application.
4 Pinout
Figure 2. Pin Assignments (Top View) Table 1. Pin Descriptions
96 G N D Analog Ground
16 15 +V DD Power Supply Input. 2.7 to 5.25V.
10 REFIN/OUT
15 SDA
12 A05CH4
14 SCL
11 COM
5 Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings Solid State Surface Mount Devices”.
www.austriamicrosystems.com Revision 1.03 4 - 20 AS1538/AS1540 Data Sheet - Electrical Characteristics
6 Electrical Characteristics
Electrical Characteristics
Table 3. Electrical Characteristics
- Guaranteed by design and characterized on sample base.
- THD measure out to 5th harmonic.
Table 4. Timing Characteristics
Figure 3. Timing Diagram
- Guaranteed by design and characterized on sample base.
7 Typical Operating Characteristics
Figure 8. Offset Error vs. Temperature Figure 9. Offset Matching vs. Temperature
8 Detailed Description
redistribution which inherently includes a sample-and- hold function. ing conversions or being addressed, the A/D converter-core and internal clock are powered off. Figure 22. Simplified I/O Diagram Figure 23. Reference circuit
for a 0V to +2.5V analog input. are made via the open-drain I/O pins SCL and SDA. Figure 24. Bus Protocol
- Data transfer may be initiated only when the bus is not busy.
while the clock line is HIGH will be interpreted as control signals.
- Bus Not Busy. Data and clock lines remain HIGH.
for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. 2C bus specifications a high-speed mode (3.4MHz clock rate) is defined.
Channel selection for the AS1538/AS1540 is made using a command byte (see Command Byte on page 12). Table 5. Powerdown Mode Bit Settings 0 0 Powerdown between A/D converter conversions. 0 1 Internal reference off and A/D converter on. 1 0 Internal reference on and A/D converter off. 1 1 Internal reference on and A/D converter on. Table 6. Channel Selection Bit Settings
- For the 4-channel AS1540 only combinations of CH0:CH3 applies.
9 Application Information
is valid, the AS1538/AS1540 will return an ACK. AS1540 once a conversion has been initiated as described in Initiating a Conversion. LSB. Byte 0 is sent first, followed by Byte 1. Figure 27. Data Word Figure 28 illustrates the interaction between the master and the slave AS1538/AS1540. and no extra delay should be included. Figure 28. Read Sequence
www.austriamicrosystems.com Revision 1.03 16 - 20 AS1538/AS1540 Data Sheet - Application Information When using the internal reference: 1. Bit PD1 off the command byte must always be set to logic 1 for each sample conversion that is issued by the sequence, as shown in Figure 28 on page 14. 2. In order to achieve 12-bit accuracy conversion when using the internal reference, the internal reference set- tling time must be considered. If bit PD1 has been set to logic 0 while using the AS1538/AS1540, then the settling time must be reconsidered after PD1 is set to logic 1 (i.e., whenever the internal reference is turned on after it has been turned off, the set- tling time must be long enough to get 12-bit accuracy conversion). 3. When the internal reference is off, it is not turned on until both the first command byte with PD1 = 1 is sent and then a STOP condition or repeated START condition is issued. (The actual turn-on time occurs once the STOP or repeated START condition is issued.) Any command byte with PD1 = 1 issued after the internal reference is turned on serves only to keep the internal reference on. Otherwise, the internal reference would be turned off by any command byte with PD1 = 0. The example in Figure 29 can be generalized for a conversion cycle by simply swapping the timing of the conversion cycle. Note: If an external reference is used, PD1 must be set to 0, and the external reference must be settled. The typical sequence in Figure 28 on page 14 or Figure 29 on page 15 can then be used. Layout For optimum performance, care should be taken with the physical layout of the AS1538/AS1540 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conver- sion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. - Power to the AS1538/AS1540 should be clean and well-bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1 to 10µF capacitor may also be needed if the impedance of the con- nection between +VDD and the power supply is high. - The AS1538/AS1540 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. - While high-frequency noise can be filtered out, voltage variation due to line frequency (50 or 60Hz) can be difficult to remove. - The GND pin should be connected to a clean ground point. In many cases, this will be the analog ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. - The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. Note: For additional information download the evaluation board application note on our website.
Figure 30. TSSOP-16 Package
- All dimensions are in millimeters; angles in degrees.
- Dimensioning and tolerancing per ASME Y14.5M – 1994.
- Dimension D does not include mold flash, protrusions, or gate
- Dimension E1 does not include interlead flash or protrusion.
- Dimension b does not include dambar protrusion. Allowable
located on the lower radius of the foot.
- Terminal numbers are for reference only.
- Datums A and B to be determined at datum plane H.
- Dimensions D and E1 are to be determined at datum plane H.
- This dimension applies only to variations with an even number
- Cross section A-A to be determined at 0.10 to 0.25mm from
Figure 31. TQFN 4x4 16-pin Package
- Dimensioning and tolerancing conform to ASME Y14.5M-1994.
- All dimensions are in millimeters, angle is in degrees.
- N is the total number of terminals.
- Terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of ter-
either a mold, embedded metal or mark feature.
- Dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip.
- ND refers to the maximum number of terminals on D side.
- Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals.
The device is available as the standard products shown in Table 7. Table 7. Ordering Information
www.austriamicrosystems.com Revision 1.03 20 - 20 AS1538/AS1540 Data Sheet Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austria- microsystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current informa- tion. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact