AS1536 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 21
Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pinout
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 7 Typical Operating Characteristics
- 8 Detailed Description
- 9 Application Information
- 10 Package Drawings and Markings
- 11 Ordering Information
1 General Description
ered analog-data collection devices. economic and highly-reliable A/D conversion solution. AS1536 features an internal 2.5V reference. REF, including the positive supply range. power consumption at slower throughput rates. clock for increased flexibility. Figure 1. Block Diagram
2 Key Features
3 Applications
sumption and single-supply requirements.
4 Pinout
Figure 2. Pin Assignments (Top View) Table 1. Pin Descriptions 2A I N Sampling Analog Input. 0V to VREF range.
3 SHDNN
operational with this pin high or floating. external reference. See also pin 4. reference output for the AS1536; bypass this pin with a 4.7µF capacitor. minimum of 0.1µF when using an external reference. See also pin 3. 6D O U T Serial Data Output. Data changes state at SCLK’s falling edge. Note: This pin is high-impedance when pin CSN is high. 7C S N Active-Low Chip Select. The falling edge of this pin initiates a conversion. Note: When this pin is high, DOUT is high-impedance. 8S C L K Serial Clock Input. This pin clocks data out at rates up to 2.1MHz.
5 Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings Solid State Surface Mount Devices”.
6 Electrical Characteristics
reference; VREF = 2.5V applied to REF; TAMB = TMIN to TMAX (unless otherwise specified). Table 3. Electrical Characteristics
- Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale
range and offset have been calibrated.
- Achievable with standard timing (see Figure 25 on page 14).
- Sample tested at 0.1% AQL.
- External load should not change during conversion for specified accuracy.
- Guaranteed by design; not subject to production testing.
FS(VDDMIN) - VFS(VDDMAX)] with external reference. Table 3. Electrical Characteristics (Continued)
7 Typical Operating Characteristics
VDD = 3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CLOAD = 50pF, TAMB = +25ºC (unless otherwise specified). Figure 5. Integral Nonlinearity vs. Digital Output Code Fi gure 6. Differential Nonlinearity vs. Digital Output Code Figure 7. FFT @ 1kHz Figure 8. FFT @ 10kHz Figure 9. ENOB vs. VREF Figure 10. ENOB vs. Input Signal Frequency
8 Detailed Description
mat (see Timing and Control on page 13). capacitor is needed for the track/hold circuit. The devices convert analog input signals in the 0V to VREF range in 13.7µs (includes track/hold acquisition time). SCLK, CSN, and DOUT) and provides a simple microprocessor interface. Figure 23. Operational Diagram Figure 24. Equivalent Input Circuit
www.austriamicrosystems.com Revision 1.01 13 - 22 AS1536/AS1537 Datasheet - Detailed Description The devices’ input tracking circuitry has a 2.5MHz small-signal bandwidth, thus it is possible to under-sample (digitize high-speed transient events) and measure periodic signals with bandwidths exceeding the devices’ sampling rate. Note: Anti-aliasing filtering should be used to avoid aliasing of unwanted high-frequency signals into the bandwidth of interest. Input Protection Internal protection diodes clamp the analog input to VDD and GND, allowing the input to swing from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the input must not exceed VDD by more than 50mV, or be lower than GND by 50mV. Note: If the analog input exceeds the supply by 50mV, limit the input current to 2mA. Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitors. During acquisition, the analog input at pin AIN charges capacitor CHOLD (see Figure 24 on page 12). Bringing CSN low ends the acquisition interval and the charge on CHOLD represent the sampled input voltage. In hold mode, the T/H switches are opened thus the input is disconnected from the capacitor CHOLD. During this mode the successive approximation is performed which in turn forms a digital representation of the analog input signal. At the end of the conversion, the input side of the in meantime discharged CHOLD switches back to AIN, and CHOLD charges to the input signal again. The maximum time for the T/H to acquire a signal (tACQ) is a function of how quickly its input capacitance is charged. tACQ increases proportionally to the input signal’s impedance, and at higher impedances more time must be allowed between conversions. tACQ is also the minimum time needed for the signal to be acquired, and is calculated by: tACQ = 10(RS + RIN) x 21pF (EQ 1) Where: RIN = 4.5kΩ RS = the input signal’s source impedance. tACQ is never less than 1.5µs. Source impedances < 1kΩ do not significantly affect the AC performance of the devices. Note: Higher source impedances can be used if a 0.01µF capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the devices’ input signal bandwidth. External Clock The AS1536/AS1537 do not require an external clock for analog-to-digital data conversion. This allows the micropro- cessor to read back the conversion results at any clock rate from up to 2.1MHz at any time. The clock duty cycle is unrestricted if each clock phase is at least 200ns. Note: The external clock must not be run while a conversion is in progress. Timing and Control Conversion-start and data-read operations are controlled by digital inputs CSN and SCLK. Refer to Figures 25 - 27 (see page 14) for graphical timing and control information. The falling edge on pin CSN initiates a conversion sequence: 1. The T/H stage holds the voltage at pin AIN, and the A/D conversion begins. 2. Pin DOUT changes from high-impedance to logic-low. SCLK must be kept low during the conversion. 3. The internal SAR stores the data during the conversion process. 4. Pin DOUT going high indicates the conversion process has completed. 5. The rising edge of pin DOUT can be used as a framing signal. 6. SCLK shifts the data out of this register any time after the conversion is complete. 7. DOUT transitions on the falling edge of pin SCLK. 8. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 12 data bits and one leading high-bit 13 falling clock edges are needed to shift out these bits, respectively.
Figure 30. Supply Current vs. Sampling Rate Figure 31. Powerup Time vs. Time in Shutdown which allows the use of an external reference (see External Reference on page 16). VDD voltage range to achieve specified accuracy. The minimum input impedance is 18kΩ for DC currents. Note: To use an external reference with the AS1536, disable the internal reference by letting pin SHDNN float. higher output impedance or is noisy, bypass it close to pin REF with a 4.7µF capacitor.
9 Application Information
capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the initialization time is 10µs after the power supplies have stabilized. Note: A/D conversions must not be started during initialization of the AS1536/AS1537. sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0). Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time.
- Put the microprocessor’s serial interface into master mode (so that it generates the serial clock).
- Select a clock frequency up to 2.1MHz.
- Keeping SCLK low, pull CSN low via one of the microprocessor’s general-purpose I/O lines.
- Monitor DOUT for its rising edge to determine the EOC, or wait the maximum conversion time specified before acti-
- Activate SCLK for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the conversion.
SCLK to DOUT valid timing characteristic. Data can be clocked into the microprocessor on the rising edge of SCLK.
- CSN should be pulled high at or after the 13th falling clock edge. If CSN remains low, trailing zeros are clocked out
- With CSN = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CSN low. If a
before starting a new conversion. Note: CSN must be held low until all data bits are clocked out.
- Data can be output in two bytes or continuously (see Figure 34 on page 18). The bytes contain the result of the con-
version padded with one leading 1, two sub-bits, and trailing 0s. set SPI control registers CPOL = 0 and CPHA = 0. Figure 32. SPI Serial Interface Connections
Figure 38. 8-pin SOIC-150 Package
- Lead coplanarity should be 0 to 0.10mm (.004”) max.
- Package surface finishing:
(2.1) Top: matte (charmilles #18-30). (2.2) All sides: matte (charmilles #18-30). (2.3) Bottom: smooth or matte (charmilles #18-30).
- All dimensions exclusive of mold flash, and end flash from the pack-
age body shall not exceed 0.24mm (0.10”) per side (D).
- Details of pin #1 identifier are optional but must be located within
The devices are available as the standard products shown in Table 5. All devices are RoHS compliant and free of halogene substances. Table 5. Ordering Information
www.austriamicrosystems.com Revision 1.01 22 - 22 AS1536/AS1537 Datasheet Copyrights Copyright © 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austria- microsystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current informa- tion. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact-us