AS1530_1 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 29
Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pinout
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 7 Typical Operating Characteristics
- 8 Detailed Description
- 9 Application Information
- 10 Package Drawings and Markings
- 11 Ordering Information
1 General Description
ically designed to operate with single-supply devices. sor and data-acquisition devices. highly-flexible and configurable. lower power consumption at slower throughput rates. SPI, QSPI-, and Microwire-compatible serial interface. The devices are available in a 20-pin TSSOP package. Figure 1. Block Diagram and Pin Assignments
2 Key Features
3 Applications
low power-consumption requirements.
20 VDD1
19 VDD2
18 SCLK
17 CSN
16 DIN
15 SSTRB
14 DOUT
13 GND
12 REFADJ
11 REF
4 Pinout
Figure 2. Pin Assignments (Top View) Table 1. Pin Descriptions 1:8 CH0:CH7 Analog Sampling Inputs. These eight pins serve as analog sampling inputs. 9C O M Common Analog Inputs. Tie this pin to ground in single-ended mode.
10 V DD3 Positive Supply Voltage
external reference mode, disable the internal buffer by pulling pin REFADJ to VDD1.
13 GND Analog and Digital Ground
clocked out. SSTRB is high impedance when CSN is high. 16 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK. 17 CSN Active-Low Chip Select. Data will not be clocked into pin DIN unless CSN is low. When CSN is high, pins DOUT and SSTRB are high impedance. to set the conversion speed. Note: The duty cycle must be between 40 and 60%.
19 V DD2 Positive Supply Voltage
20 V DD1 Positive Supply Voltage
5 Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings Solid State Surface Mount Devices”.
6 Electrical Characteristics
Table 3. AS1530 Electrical Characteristics
- Tested at VDD1 = VDD2 = VDD3 = +5V, COM = GND, bit RANGE (page 15) = 1, single-ended input mode.
- Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
- Ground on channel; sinewave applied to all off channels.
- Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
- The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to V
- External load should not change during conversion for specified accuracy. Guaranteed specification of 4mV/mA
is a result of production test limitations.
- AS1530/AS1531 performance is limited by the device noise floor, typically 300µVp-p.
Table 3. AS1530 Electrical Characteristics (Continued)
- Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) = VDD3(MIN) to VDD1(MAX) = VDD2(MAX) =
specifications beyond the limits, contact austriamicrosystems, AG.
- AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz
- SCLK = DIN = GND, CSN = VDD2.
Table 4. AS1531 Electrical Characteristics
- Tested at VDD1 = VDD2 = VDD3 = +3V; COM = GND; bit RANGE (page 15) = 1, single-ended input mode.
Table 4. AS1531 Electrical Characteristics (Continued)
- Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
- Ground on channel; sinewave applied to all off channels.
- Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
- The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1.
- External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA
is a result of production test limitations.
- AS1530/AS1531 performance is limited by the device noise floor, typically 300µVp-p.
- Electrical characteristics are guaranteed from V
specifications beyond the limits, contact austriamicrosystems, AG.
- AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 4.8MHz
- SCLK = DIN = GND, CSN = VDD2.
Table 5. AS1530 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +4.5 to +5.5V; TAMB = TMIN to TMAX (unless otherwise specified). Table 6. AS1531 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +2.7 to +3.6V; TAMB = TMIN to TMAX (unless otherwise specified).
7 Typical Operating Characteristics
Same conditions as stated in Electrical Characteristics on page 5. Figure 5. INL vs. Digital Output Code Figure 6. DNL vs. Digital Output Code Figure 7. FFT @ 10kHz; RANGE = 1, MODE = 1 F igure 8. FFT @ 75kHz; RANGE = 0, MODE = 1 Figure 9. ENOB vs. VREF; 1st Order 300kHz Figure 10. ENOB vs. Input Signal Frequency; 1st
8 Detailed Description
Figure 20. Equivalent Input Circuit inputs must not exceed VDD1 by more than 50mV or be lower than GND by 50mV. Note: If the analog input exceeds 50mV beyond the supply voltage, do not allow the input current to exceed 2mA. bit control byte has been shifted in. RS = the source impedance of the input signal. Note: Source impedances below 2kΩ do not significantly affect the AC performance of the devices.
DIN and SCLK pins. The control register format is shown in Table 7 and the function of the bits are defined in Table 8. ! The first logic 1 bit clocked into pin DIN after bit 6 of a conversion in progress is clocked out of pin DOUT. the devices can operate is 16 clocks per conversion (with CSN held low between conversions). Table 7. Control Byte Format Table 8. Bit Descriptions 7 START The first logic 1 bit after CSN goes low signifies the start of a control byte. the conversion (see Table 10 and Table 11).
3 RANGE
This bit selects the analog input range of the AS1530/AS1531. 0 = The analog input range extends from -VREF/2 to +VREF/2. 1= The analog input range extends from 0V to VREF.
2 MODE
This bit in conjunction with bit RANGE changes the analog input configuration. Table 9. Analog Input Configuration 8-Channel Single-Ended 1 1 Binary AIN+ from 0 to VREF. fully differential input signal.
ently to the input channels (CH0:CH7 and COM). Note: In single-ended mode pin COM should be connected to GND pin. Table 10. Input Channel Selection for MODE = 1 Table 11. Input Channel Selection for MODE = 0
Figure 26. Two’s Complement Transfer Function for Fi gure 27. Two’s Complement Transfer Function for The power mode is selected using bits PD1 and PD0 of the 8-bit control byte. rates achievable in full power-down mode see Full Power-Down Mode on page 20.
- Circuit operation between conversions; during conversion all circuits are fully powered up.
The selected power-down mode (as shown in Table 12) is initiated after an analog-to-digital conversion is completed. dant on the values of the capacitance of REF and REFADJ). (dependant on the values of the capacitance of REF and REFADJ). Table 12. Software Controlled Power Modes
can further reduce power consumption. This is achieved by using the sequence shown in Figure 30 on page 21. sumption up to the full sampling rate. Figure 30. Full Power-Down Timing Waveforms (AS1531) Figure 31. Average Supply Current vs. Sampling Rate (AS1531, FULLPD, and External Reference) The AS1530/AS1531 can operate with the internal or an external reference. decoupling capacitor is needed at pin REF.
1 Channel
input impedance is typically 17kΩ. Figure 32 shows a possible arrangement. Figure 32. Reference Adjust Circuit disabled by connecting pin REFADJ to pin VDD. The input resistance is typically 15kΩ. as close to pin REF as possible. Note: Using the REFADJ input makes buffering the external reference unnecessary.
www.austriamicrosystems.com Revision 1.02 23 - 29 AS1530/AS1531 Data Sheet - Application Information
9 Application Information
When power is first applied to the AS1530/AS1531 internal power-on reset circuitry sets the devices for normal opera- tion. At this point, the devices can perform data conversions with CSN held low. Note: The device requires 10µs after the power supplies stabilize; no conversions should be initiated during this time. The digital output at pin DOUT will be all 0s until an analog-to-digital conversion is initiated. Serial Interface The AS1530/AS1531 fully support SPI, QSPI, and Microwire interfaces. For SPI, select the correct clock polarity and sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0). Note: Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the circuit shown in Figure 33 on page 24, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the AS1530/AS1531, and two more 8-bit transfers to clock out the 12-bit conversion result). Serial Interface Configuration The following steps describe how to configure the serial interface: 1. Confirm that the CPU serial interface is in master mode (so the CPU generates the serial clock). 2. Choose a clock frequency from 500kHz to 6.4MHz (AS1530) or 4.8MHz (AS1531). 3. Set up the control byte and call it TB1. TB1 should be in the format 1XXXXXXX binary, where the Xs indicate the selected channel, conversion mode, and power mode. 4. Use a general-purpose I/O line on the CPU to pull CSN low. 5. Transmit TB1 and simultaneously receive a byte (RB1). Ignore this byte. 6. Transmit a byte of all zeros ($00 h) and simultaneously receive byte RB2. 7. Transmit a byte of all zeros ($00h) and simultaneously receive byte RB3. 8. Pull CSN high. Bytes RB2 and RB3 (see Figure 21 on page 17) contain the results of the conversion, padded with three leading zeros and one trailing zero. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive track/hold droop, make sure the total conversion time does not exceed 120µs.
In order to quickly evaluate the analog performance of the AS1530/AS1531, use the circuit shown in Figure 35. Figure 35. Evaluation Circuit Diagram of bits from DOUT. A total of 16 clock cycles is required per conversion. Note: All SSTRB and DOUT output transitions occur 25ns (typ) after the rising edge of SCLK.
The AS1530/AS1531 require proper layout and design procedures for optimum performance. ! Use printed circuit boards; wirewrap boards should not be used. ! Analog and digital traces should be separate and should not run parallel to each other (especially clock traces). ! Digital traces should not run beneath the AS1530/AS1531. low impedance and as short as possible for noise-free operation. Ω resistor can be connected as a low-pass filter to attenuate supply noise (see Figure 36). Figure 36. Recommended GND Design
Figure 37. 20-pin TSSOP Package
- All dimensions are in millimeters; angles in degrees.
- Dimensioning and tolerancing per ASME Y14.5M – 1994.
- Dimension D does not include mold flash, protrusions, or gate
- Dimension E1 does not include interlead flash or protrusion.
- Dimension b does not include dambar protrusion. Allowable
located on the lower radius of the foot.
- Terminal numbers are for reference only.
- Datums A and B to be determined at datum plane H.
- Dimensions D and E1 are to be determined at datum plane H.
- This dimension applies only to variations with an even number
- Cross section A-A to be determined at 0.10 to 0.25mm from
The devices are available as the standard products shown in Table 13. Table 13. Ordering Information
www.austriamicrosystems.com Revision 1.02 29 - 29 AS1530/AS1531 Data Sheet Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact