AS1364_04 AMSCO
Document overview
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Technical content
The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com
1 General Description
perfectly suited for battery-operated portable applications. 100kHz) or 45µVRMS (10Hz to 1MHz) output voltage noise.
2 Key Features
3 Applications
Figure 1. AS1364 - Typical Application Diagram
4 Pin Assignments
Figure 2. Pin Assignments (T op View)
4.1 Pin Descriptions
Table 2. Pin Descriptions Note: Open-Drain POK Output. POK remains low while VOUT is below the POK threshold. Connect a 100k pull-up resistor from this pin to OUT to obtain an output voltage (see Figure 1). 0.1µA. In shutdown, the POK output is low and OUT high impedance.
7 SET/BYP
Bypass Pin. Connect a 10nF capacitor from this pin to OUT to improve PSRR and noise performance. Substrate Connect to PCB metal area for heatsink purposes. May be left open or connected to common ground.
5 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Hermetic Solid State Surface Mount Devices”.
6 Electrical Characteristics
specified). Typical values are at TAMB = +25ºC. Table 4. Electrical Characteristics
- Guaranteed by production test of load regulation and line regulation.
- Dropout voltage is defined as VIN - VOUT, when VOUT is 100mV below the value of VOUT measured for VIN = (VOUT(NOM) + 500mV).
Since the minimum input voltage is 2.0V, this specification is only valid when VOUT(NOM) > 2.0V. Table 4. Electrical Characteristics (Continued)
7 Typical Operating Characteristics
VIN = VOUT(NOM) + 0.5V, CIN = COUT = 4.7µF, TAMB = 25°C (unless otherwise specified). Figure 7. Quiescent Current vs. VIN Figure 8. Quiescent Current vs. IOUT
8 Detailed Description
Figure 16. AS1364 - Block Diagram element, and output voltage variations with loading are absorbed by the low output impedance of the regulator. When in shutdown, a 5k discharge path is connected between the output terminal and ground.
8.1 Output Voltage Selection
(see Ordering Information on page 18). therefore increasing efficiency. Note: Up to 125k is acceptable for R2. If the SET pin is connected to GND without a resistor, 3.3V will be set as output voltage. Figure 17. Adjustable Output Voltage Typical Application
8.2 Shutdown
(typ). For normal device operation pin EN must be connected to IN. During shutdown, POK goes low. When in shutdown, a 5k (typ) discharge path is connected between the output pin and ground.
8.3 Power-OK
POK can be used as a power-on-reset (POR) signal to a microcontroller or can drive an external LED to indicate a power failure condition. Note: POK is low during shutdown.
9 Application Information
9.1 Dropout Voltage
regulator defines the useful “end of life” of the battery before replacement or re-charge is required. Figure 18. Graphical Representation of Dropout Voltage regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential.
9.2 Efficiency
9.3 Power Dissipation
9.4 Junction Temperature
manufacturer), and adjustment of the case to ambient heat path (CAºC/W) by manipulation of the PCB copper area adjacent to the IC position. Figure 19. Package Physical Arrangements Figure 20. Steady State Heat Flow Equivalent Circuit
Datasheet - Application Information www.austriamicrosystems.com Revision 1.8 13 - 19 Total Thermal Path Resistance: (EQ 8) Junction Temperature (TJºC) is determined by: ºC (EQ 9)
9.5 Explanation of St eady State Specifications
9.5.1 Line Regulation
Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain of the error amplifier. More generally: Line Regulation = and is a pure number In practise, line regulation is referred to the regulator output voltage in terms of % / VOUT. This is particularly useful when the same regulator is available with numerous output voltage trim options. Line Regulation = % / V (EQ 10)
9.5.2 Load Regulation
Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output resistance of the regulator. More generally: Load Regulation = and is units of ohms ( )( EQ 11) In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is available with numerous output voltage trim options. Load Regulation = % / mA (EQ 12)
9.5.3 Setting Accuracy
Accuracy of the final output voltage is determined by the accuracy of the ratio of R1 and R2, the reference accuracy and the input offset voltage of the error amplifier. When the regulator is supplied pre-trimmed, the output voltage accuracy is fully defined in the output voltage specification. When the regulator has a SET terminal, the output voltage may be adjusted externally. In this case, the tolerance of the external resistor network must be incorporated into the final accuracy calculation. Generally: (EQ 13) The reference tolerance is given both at 25ºC and over the full operating temperature range.
9.5.4 Total Accuracy
Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally: T otal % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation % (EQ 14) RJA RJC RCS RSA++= VOUT VIN VOUT VIN VOUT VOUT IOUT VOUT IOUT VOUT ams AG Technical content still valid
Datasheet - Application Information www.austriamicrosystems.com Revision 1.8 14 - 19
9.6 Explanation of Dynamic Specifications
9.6.1 Power Supply Rejection Ratio (PSRR)
Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low quiescent current conditions. Generally: PSSR = dB using lower case to indicate AC values (EQ 15) Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally.
9.6.2 Output Capacitor ESR
The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown either by a plot of stable ESR versus load current, or a limit statement in the datasheet. Some ceramic capacitors exhibit large capacitance and ESR variations with temperature. Z5U and Y5V capacitors may be required to ensure stability at temperatures below TAMB = -10ºC. With X7R or X5R capacitors, a 4.7µF capacitor should be sufficient at all operating temperatures. Larger output capacitor values (10µF max) help to reduce noise and improve load transient-response, stability and power-supply rejection.
9.6.3 Input Capacitor
An input capacitor at VIN is required for stability. It is recommended that a 4.7µF capacitor be connected between the AS1364 power supply input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a distance of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
9.6.4 Noise
The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will produce system problems.
9.6.5 Transient Response
The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally: Units are Volts, Amps, Ohms. (EQ 16) Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Remember to keep the ESR within stability recommendations when reducing ESR by adding multiple parallel output capacitors. After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change. This drift is approx. linear in time and sums with the ESR contribution to make a total transient variation at the output of: Units are Volts, Seconds, Farads, Ohms. (EQ 17) Where: C LOAD is output capacitor T = Propagation delay of the LDO This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load current step produces 50mV output drop if the LDO response is 1usec and the load cap is 1µF. There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification discussed above. 20Log VOUT VIN VTRANSIENT IOUTPUT RESR= VTRANSIENT IOUTPUT= RESR T CLOAD ams AG Technical content still valid
www.austriamicrosystems.com Revision 1.8 15 - 19 AS1364 Datasheet - Application Information
9.6.6 Turn On Time
This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator Min and Max limits. Shutdown reduces the quiescent current to very low, mostly leakage values (<1µA).
9.6.7 Thermal Protection
To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device. Die temperature is measured, and when a 170ºC (AS1364) threshold is reached, the device enters shutdown. When the die cools sufficiently, the device will restart (assuming input voltage exists and the device is enabled). Hysteresis of 20ºC prevents low frequency oscillation between start- up and shutdown around the temperature threshold. ams AG Technical content still valid
The device is available in an 8-pin TDFN 3x3mm package. Figure 21. 8-pin TDFN 3x3mm Package
- Figure 21 is shown for illustration only.
- All dimensions are in millimeters; angles in degrees.
- Dimensioning and tolerancing conform to ASME Y14.5 M-1994.
- N is the total number of terminals.
- The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95-1, SPP-012. Details of terminal #1 identifier are
optional, but must be located within the zone indicated. The terminal #1 identifier may be either a mold or marked feature.
- Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
- ND refers to the maximum number of terminals on side D.
- Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals
Datasheet - Package Drawings and Markings www.austriamicrosystems.com Revision 1.8 17 - 19
Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description - - - Initial revisions
1.5 Sep 2011
Changes made across document 1.6 18 Nov, 2011 1.7 12 Dec, 2011 Updated equations in Power Dissipation section 1.8 03 Apr, 2012 Corrected Figure 1, Figure 16, Figure 17 ams AG Technical content still valid
The device is available as the standard products shown in Table 5. Note: All products are RoHS compliant. Table 5. Ordering Information
Datasheet - Ordering Information www.austriamicrosystems.com Revision 1.8 19 - 19 Copyrights Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact ams AG Technical content still valid