AS1361_1 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 15
Technical content
1 General Description
capacitance ceramic capacitors. the output voltage is within regulation. rent consumption drops below 500nA. The devices are available in a TSOT23 6-pin package. Figure 1. Typical Application Circuit
2 Key Features
3 Applications
Table 1. Standard Products
4 Pinout
Figure 2. Pin Assignments (Top View) Table 2. Pin Descriptions 1I N Unregulated Input Supply. 3 SHDNN Shutdown. Pull this pin low to disable the LDO. voltage is within regulation.
5 BYPASS
Note: This pin is shorted to GND in shutdown mode. Capacitor Selection and Regulator Stability on page 12 for more details.
5 Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings State Surface Mount Devices”.
6 Electrical Characteristics
ues are at TAMB = +25ºC. Limits 100% tested at +25ºC. Limits over operating temperature range guaranteed by design. Table 4. Electrical Characteristics
- Dropout is defined as VIN - VOUT when VOUT is 100mV below the value of VOUT for VIN = VOUT + 0.5V.
- Time needed for VOUT to reach 90% of final value.
SQC (Statistical Quality Control) methods. Table 4. Electrical Characteristics (Continued)
7 Typical Operating Characteristics
VIN = VOUT + 0.5V, CIN = COUT = 1µF, CBYPASS = 10nF, TAMB = 25°C (unless otherwise specified). Figure 3. Output Voltage vs. Input Voltage Figur e 4. Output Voltage Accuracy vs. Load Current Output Voltage Deviation (%) . Figure 5. Output Voltage Accuracy vs. Temperature Figure 6. Dropout Voltage vs. Load Current Output Voltage Deviation (%) . Figure 7. Dropout Voltage vs. Output Voltage
www.austriamicrosystems.com Revision 1.03 9 - 15 AS1361/AS1362 Datasheet - Detailed Description
8 Detailed Description
The AS1361/AS1362 are ultra-low-noise, low-dropout, low-quiescent current linear-regulators specifically designed for space-limited applications. The devices are available with preset output voltages from 1.5 to 4.5V in 50mV increments. These devices can supply loads up to 150/300mA. As shown in Figure 18, the AS1361/AS1362 consist of an inte- grated bandgap core and noise bypass circuitry, error amplifier, P-channel MOSFET pass transistor, and internal feed- back voltage-divider. The output voltage is fed back through an internal resistor voltage-divider connected to pin OUT. An external bypass capacitor connected to pin BYPASS reduces noise at the output. Additional blocks include a current limiter, thermal sensor, and shutdown logic. Internal Voltage Reference The 1.25V bandgap reference is connected to the error amplifier’s inverting input. The error amplifier compares this reference with the feedback voltage and amplifies the difference. If the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled low. This allows more current to pass to the output and increases the output voltage. If the feedback voltage is too high, the pass transistor gate is pulled high, allowing less current to pass to the output. Internal P-Channel Pass Transistor The AS1361/AS1362 feature a 0.5Ω (typ) P-channel MOSFET pass transistor, which provides several advantages over similar designs using a PNP pass transistor, including prolonged battery life. The P-channel MOSFET does not require a base driver, thus quiescent current is dramatically reduced. The AS1361/AS1362 LDOs do not exhibit prob- lems associated with typical PNP-based LDOs, and consume only 40µA of quiescent current in light load and 220µA in dropout (see Typical Operating Characteristics on page 6). Output Voltage The AS1361/AS1362 deliver preset output voltages from 1.5 to 4.5V, in 50mV increments (see Ordering Information on page 14). Shutdown The AS1361/AS1362 feature a low-power shutdown mode that reduces quiescent current to <200nA. Driving SHDNN low disables the internal voltage reference, error amplifier, gate-drive circuitry, and P-channel MOSFET pass transistor (see Figure 18), and the device output enters a high-impedance state. Note: For normal operation connect pin SHDNN to pin IN.
Figure 18. AS1361/AS1362 - Block Diagram age goes out of regulation (e.g. during dropout, current limit, or thermal shutdown) pin POK goes low. down to VIN = 1V. A capacitor to GND may be added to generate a POR delay. help minimize current consumption; a 100kΩ resistor is perfect for most applications (see Figure 1 on page 1). tor’s gate voltage, thus limiting the device output current to 270mA (AS1361) and 510mA (AS1362). indefinitely without causing damage to the device. do not exceed the absolute maximum junction temperature rating of +150ºC. temperature difference between the die junction and TAMB, and airflow rate.
1.25 Reference
www.austriamicrosystems.com Revision 1.03 11 - 15 AS1361/AS1362 Datasheet - Detailed Description The maximum power dissipation is calculated: PDMAX = (TJ - TAMB)/(θJC + θCA)( E Q 2 ) Where: TJ - TAMB is the temperature difference between the AS1361/AS1362 die junction and the surrounding air; θJC is the thermal resistance of the package; θCA is the thermal resistance through the PC board/copper traces/other materials to the surrounding air. Note: Pin GND of the AS1361/AS1362 provides the electrical connection to system ground and also serves as a heat sink. Connect pin GND to the system ground using a large pad or ground plane. Noise Reduction The AS1361/AS1362 noise bypass circuitry dramatically reduces output noise, exhibiting 9µVRMS of output voltage noise with CBYPASS = 0.01µF and COUT = 1µF. Use an external 0.01µF bypass capacitor between pin BYPASS and pin OUT (see Figure 1 on page 1). Note: Startup time is minimized by internal power-on circuitry which pre-charges CBYPASS.
www.austriamicrosystems.com Revision 1.03 12 - 15 AS1361/AS1362 Datasheet - Application Information
9 Application Information
Capacitor Selection and Regulator Stability For normal operation, use a 1µF capacitor at pin IN and a 1µF capacitor at pin OUT. Larger input capacitor values and lower ESR provide better noise rejection and line-transient response. Reduce output noise and improve load-transient response, stability, and power-supply rejection by using large output capacitors. Note: Some ceramic dielectrics exhibit large capacitance and ESR variation with temperature. With dielectrics such as Z5U and Y5V, it may be necessary to use a 2.2µF or larger output capacitor to ensure stability at tempera- tures below -10°C. With X7R or X5R dielectrics, 1µF is sufficient at all operating temperatures. Bypass Capacitor Use a 0.01µF bypass capacitor at pin BYPASS for low-output voltage noise reduction. The leakage current going into pin BYPASS should be less than 10nA. Increasing the capacitance slightly decreases the output noise. Values above 0.1µF and below 0.001µF are not recommended. Noise, PSRR, and Transient Response The AS1361/AS1362 are designed to deliver ultra-low noise and high PSRR, as well as low dropout and low quiescent currents in battery-powered systems. The power-supply rejection is 92dB at 1kHz and 62dB at 100kHz. (see PSRR vs. Frequency; IOUT = 10mA on page 7). When operating from sources other than batteries, improved supply-noise rejection and transient response can be achieved by increasing the values of the input and output capacitors, and through passive filtering techniques. The Figure 16 and Figure 14 on page 8 show the AS1361/AS1362 line- and load-transient responses. Dropout Voltage The AS1361/AS1362 minimum dropout voltage determines the lowest usable supply voltage. In battery-powered sys- tems, this determines the useful end-of-life battery voltage. Since the AS1361/AS1362 use a P-channel MOSFET pass transistor, the dropout voltage is a function of drain-to- source on-resistance (RDS(ON)) multiplied by ILOAD (see Figure 6 on page 6).
The devices are available in a TSOT23 6-pin package. Figure 19. TSOT23 6-pin Package
- Dimensioning and tolerancing conform to ASME Y14.5M - 1994.
- Dimensions are in millimeters.
- Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall
trusion shall not exceed 0.15mm per side. Dimensions D and E1 are determined at datum H.
- The package top can be smaller than the package bottom. Dimensions D and E1 are determined at the outer-
The devices are available as the standard products shown in Table 5. Note: All products are RoHS compliant and Pb-free. Table 5. Ordering Information
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