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Technical content
The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com
1 General Description
with low-cost, small-capacitance ceramic capacitors. The devices are available as the standard products listed in Table 1. to maintain extremely low quiescent current (40µA). rejection-ratio of better than 80dB (up to 10kHz). The devices are available in a TSOT23 5-pin package. Figure 1. Typical Application Circuit
2 Key Features
3 Applications
audio devices, and any other portable, battery-powered application.
4 Pin Assignments
Figure 2. Pin Assignments (T op View)
4.1 Pin Descriptions
Table 2. Pin Descriptions 1I N Unregulated Input Supply. 2G N D Ground. Provides the electrical connection to system ground and also serves as a heat sink. Connect pin GND to the system ground using a large pad or ground plane. 3 SHDNN Shutdown. Pull this pin low to disable the LDO. 4 BYPASS Noise Bypass for Low-Noise Operation. Connect a 10nF capacitor from this pin to OUT. Note: This pin is shorted to GND in shutdown mode. 5O U T Regulated Output Voltage. Bypass this pin with a capacitor to GND.
4 BYPASS
5 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings be paid to thermal dissipation during board design. Hermetic Solid State Surface Mount Devices”.
6 Electrical Characteristics
VIN = VOUT +0.5V, CIN = 1µF, COUT = 1µF, CBYPASS = 10nF, TAMB = -40 to +85ºC (unless otherwise specified). Typical values are at TAMB = +25ºC. Table 4. Electrical Characteristics
- Dropout is defined as V IN - VOUT when VOUT is 100mV below the value of VOUT for VIN = VOUT + 0.5V
- Time needed for V OUT to reach 90% of final value
7 Typical Operating Characteristics
VIN = VOUT + 0.5V, CIN = COUT = 1µF, CBYPASS = 10nF , TAMB = 25°C (unless otherwise specified). Figure 3. Output Voltage vs. Input Voltage Figure 4. Output Voltage Accuracy vs. Load Current Output Voltage Deviation (%) . Figure 5. Output Voltage Accuracy vs. T emperature Figure 6. Dropout Voltage vs. Load Current Output Voltage Deviation (%) . Figure 7. Dropout Voltage vs. Output Voltage Figure 8. Ground Pin Current vs. Input Voltage
8 Detailed Description
applications. The devices are available with preset output voltages from 1.5V to 4.5V in 50mV increments. noise bypass circuitry, error amplifier, P-channel MOSFET pass transistor, and internal feedback voltage-divider. MOSFET as the control element. A stable voltage reference (REF in Figure 18) is compared with an attenuated sample of the output voltage. series element and output voltage variations with loading are absorbed by the low output impedance of the regulator. The AS1358 / AS1359 deliver preset output voltages from 1.5V to 4.5V, in 50mV increments (see Ordering Information on page 15). include a current limiter, thermal sensor, and shutdown logic. Figure 18. AS1358 / AS1359 Block Diagram
1.25 Reference and
9 Application Information
9.1 Dropout Voltage
regulator defines the useful “end of life” of the battery before replacement or re-charge is required. Figure 19. Graphical Representation of Dropout Voltage regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential.
9.2 Efficiency
9.3 Power Dissipation
9.4 Junction Temperature
manufacturer), and adjustment of the case to ambient heat path (CAºC/W) by manipulation of the PCB copper area adjacent to the IC position. Figure 20. Package Physical Arrangements Figure 21. Steady State Heat Flow Equivalent Circuit
www.austriamicrosystems.com Revision 1.5 11 - 16 AS1358 / AS1359 Datasheet - Application Information Total Thermal Path Resistance: (EQ 6) Junction Temperature (TJºC) is determined by: ºC (EQ 7)
9.5 Explanation of St eady State Specifications
9.5.1 Line Regulation
Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain of the error amplifier. More generally: Line Regulation = and is a pure number (EQ 8) In practise, line regulation is referred to the regulator output voltage in terms of % / VOUT. This is particularly useful when the same regulator is available with numerous output voltage trim options. Line Regulation = % / V (EQ 9)
9.5.2 Load Regulation
Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output resistance of the regulator. More generally: Load Regulation = and is units of ohms ( )( EQ 10) In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is available with numerous output voltage trim options. Load Regulation = % / mA (EQ 11)
9.5.3 Setting Accuracy
The regulator is supplied pre-trimmed, so that the output voltage accuracy is fully defined in the output voltage specification.
9.5.4 Total Accuracy
Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally: T otal % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation % (EQ 12)
9.6 Explanation of Dynamic Specifications
9.6.1 Power Supply Rejection Ratio (PSRR)
Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low quiescent current conditions. Generally: PSSR = dB using lower case to indicate AC values (EQ 13) Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally. RJA RJC RCS RSA++= VOUT VIN VOUT VIN VOUT VOUT IOUT VOUT IOUT VOUT 20Log VOUT VIN ams AG Technical content still valid
www.austriamicrosystems.com Revision 1.5 12 - 16 AS1358 / AS1359 Datasheet - Application Information
9.6.2 Output Capacitor ESR
The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown either by a plot of stable ESR versus load current, or a limit statement in the datasheet. Some ceramic capacitors exhibit large capacitance and ESR variations with temperature. Z5U and Y5V capacitors may be required to ensure stability at temperatures below TAMB = -10ºC. With X7R or X5R capacitors, a 1.0µF capacitor should be sufficient at all operating temperatures. Larger output capacitor values (2.2µF max) help to reduce noise and improve load transient-response, stability and power-supply rejection.
9.6.3 Input Capacitor
An input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the AS1358 / AS1359 power supply input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a distance of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
9.6.4 Noise
The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will produce system problems. The AS1358/9 architecture provides enhance noise reduction when an external 10nF capacitor is connected between Bypass and Output pins, and 1µF connected as the output capacitor. The leakage current going into the BYPASS pin should be less than 10nA. Increasing the capacitance slightly decreases the output noise. Values above 0.1µF and below 0.001µF are not recommended.
9.6.5 Transient Response
The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally: Units are Volts, Amps, Ohms. (EQ 14) Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Remember to keep the ESR within stability recommendations when reducing ESR by adding multiple parallel output capacitors. After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change. This drift is approximately linear in time and sums with the ESR contribution to make a total transient variation at the output of: Units are Volts, Seconds, Farads, Ohms. (EQ 15) Where: C LOAD is output capacitor T = Propagation delay of the LDO This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load current step produces 50mV output drop if the LDO response is 1usec and the load cap is 1µF. There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification discussed above.
9.6.6 Turn On Time
This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator Min and Max limits. Shutdown reduces the quiescent current to very low, mostly leakage values (<1µA).
9.6.7 Thermal Protection
To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device. Die temperature is measured, and when a 160ºC threshold is reached, the device enters shutdown. When the die cools sufficiently, the device will restart (assuming input voltage exists and the device is enabled). Hysteresis of 15ºC prevents low frequency oscillation between start-up and shutdown around the temperature threshold. VTRANSIENT IOUTPUT RESR= VTRANSIENT IOUTPUT= RESR T CLOAD ams AG Technical content still valid
The devices are available in a TSOT23 5-pin package. Figure 22. TSOT23 5-pin Package
- Dimensioning and tolerancing conform to ASME Y14.5M - 1994.
- Dimensions are in millimeters.
- Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0.15mm per
sions D and E1 are determined at datum H.
- The package top can be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic
body and the bottom. D and E1 are determined at datum H.
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Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 1.4 - afe Initial revisions 1.5 13 Jun, 2012 ams AG Technical content still valid
The devices are available as the standard products shown in Table 5. Note: All products are RoHS compliant and Pb-free. Table 5. Ordering Information
www.austriamicrosystems.com Revision 1.5 16 - 16 AS1358 / AS1359 Datasheet - Ordering Information Copyrights Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact ams AG Technical content still valid