AS1324_13 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 21
Technical content
1 General Description
buck converter available in adjustable- and fixed-voltage versions. AS1324 perfect for any single Li-Ion battery-powered application. The AS1324 is available in a 5-pin TSOT-23 package. Figure 1. Typical Application Diagram – High Efficiency Step
2 Key Features
3 Applications
space-limited application with low power-consumption requirements.
5 V OUT
4 V IN
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
4.1 Pin Descriptions
impedance, drawing <1µA supply current. Note: This pin should not be left floating. synchronous power MOSFET switches. Input Supply Voltage . This pin must be closely decoupled to GND with a ≥ 4.7µF ceramic capacitor. Connect to any supply voltage between 2.7 to 5.5V.
5 VFB
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5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. T able 3. Absolute Maximum Ratings Parameter Min Max Units Comments VIN to GND -0.3 6 V SW, EN, FB to GND -0.3 VIN + 0.3 V Thermal Resistance Θ JA 207.4 ºC/W on PCB ESD 2 kV HBM MIL-Std. 883E 3015.7 methods Latch-Up -100 +100 mA JEDEC 78 Operating Temperature Range -40 +85 ºC Storage Temperature Range -65 +125 ºC Package Body Temperature +260 ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). Junction Temperature 125 ºC Junction temperature (TJ) is calculated from the ambient temperature (TAMB ) and power dissipation (PD) as: TJ = TAMB + (PD)(207.4ºC/W) (EQ 1) Moisture Sensitive Level 1 Represents an unlimited fl oor life time
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6 Electrical Characteristics
VIN = EN = 3.6V, VOUT < VIN - 0.5V, TAMB = -40 to +85°C, typ. values @ TAMB = +25ºC (unless otherwise specified) . Note: All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. T able 4. Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units VIN Input Voltage Range 2.7 5.5 V IQ Quiescent Current Powersave Mode; VFB = 0.62V or VOUT = 103%, IOUT = 0mA, TAMB = +25ºC 30 35 µA ISHDN Shutdown Current Shutdown Mode; V EN = 0V, TAMB = +25ºC 0.1 1 Regulation VFB Regulated Feedback Voltage 1 1. The device is tested in a proprietary test mode where VFB is connected to the output of the error amplifier. AS1324, IOUT = 100mA 0.585 0.6 0.615 V ΔVFB Reference Voltage Line Regulation VIN = 2.7V to 5.5V 0.1 1 %/V IVFB Feedback Current TAMB = +25ºC -30 30 nA VOUT Regulated Output Voltage AS1324-AD, IOUT = 100mA 2 2. Please see Feedback Resistor Selection on page 13 for resistor values. VFB V AS1324-12, IOUT = 100mA 1.164 1.20 1.236 AS1324-15, IOUT = 100mA 1.455 1.50 1.545 AS1324-18, IOUT = 100mA 1.746 1.80 1.854 ΔVOUT Output Voltage Line Regulation VIN = 2.7 to 5.5V 0.1 1 %/V VLOADREG Output Voltage Load Regulation IOUT = 0 to 100mA 0.02 %/mA DC-DC Switches IPK Peak Inductor Current VIN = 3V, VFB = 0.5V or VOUT = 90%, TAMB = 25ºC 0.5 0.75 1 A RPFET P-Channel FET R DS(ON) ILSW = 100mA 0.4 Ω RNFET N-Channel FET R DS(ON) ILSW = -100mA 0.35 Ω ILSW SW Leakage V EN = 0V, VSW = 0V or 5V ±0.01 ±1 µA Control Inputs VEN EN Threshold 0.3 1 1.5 V IEN EN Leakage Current ±0.01 ±1 µA Oscillator fOSC Oscillator Frequency VFB = 0.6V or VOUT = 100% 1.2 1.5 1.8 MHz VFB = 0V or VOUT = 0V, TAMB = 25ºC 115 kHz
7 Typical Operating Characteristics
Parts used for measurement: 4.7µH (MOS6020-472) Inductor, 10µF (GRM188R60J106ME47) CIN and COUT .
8 Detailed Description
MOSFET switches and is available in adjustable- and fixed-output voltage versions. Figure 21. AS1324 - Block Diagram
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8.1 Main Control Loop
During PWM operation the converters use a 1.5MHz fixed-frequency, current-mode control scheme. Basis of the current-mode PWM controller is an open-loop, multiple input comparator that compares the error-amp voltage feedback signal against the sum of the amplified current-sense signal and the slope-compensation ramp. At the beginning of each clock cycle, the internal high-side PMOS turns on until the PWM comparator trips. During this time the current in the inductor ramps up, sourcing current to the output and storing energy in the inductor’s magnetic field. When the PMOS turns off, the internal low-side NMOS turns on. Now the inductor releases the stored energy while the current ramps down, still providing current to the output. The output capacitor stores charge when the inductor current exceeds the load and discharges when the inductor current is lower than the load. Under overload conditions, when the inductor current exceeds the current limit, the high-side PMOS is turned off and the low-side NMOS remains on until the next clock cycle. When the PMOS is off, the NMOS is turned on until the inductor current starts to reverse (as indicated by the current reversal comparator (IRCMP)), or the next clock cycle begins. The IRCMP detects the zero crossing. The peak inductor current (IPK ) is controlled by the error amplifier. When IOUT increases, VFB decreases slightly relative to the internal 0.6V reference, causing the error amplifier’s output voltage to increase until the average inductor current matches the new load current. The over-voltage detection comparator (OVDET) guards against transient overshoots by turning the main switch off and keeping it off until the transient is removed.
8.2 Powersave Operation
The AS1324 uses an automatic powersave mode where the peak inductor current (IPK ) is set to approximately 200mA while independent of the output load. In powersave mode, load current is supplied solely from the output capacitor. As the output voltage drops, the error amplifier output rises above the powersave threshold signaling to switch into PWM fixed frequency mode and turn the PMOS on. This process repeats at a rate determined by the load demand. Each burst event can last from a few cycles at light loads to almost continuous cycling (with short sleep intervals) at moderate loads. In between bursts, the power MOSFETs are turned off, as is any unneeded circuitry, reducing quiescent current to 30µA.
8.3 Short-Circuit Protection
In cases where the AS1324 output is shorted to ground, the oscillator frequency (fOSC ) is reduced to 1/13 the nominal frequency ( ≅ 115kHz). This frequency reduction ensures that the inductor current has more time to decay, thus preventing runaway conditions. fOSC will progressively increase to 1.5MHz when VFB /VOUT > 0V.
8.4 Shutdown
Connecting EN to GND or logic low places the AS1324 in shutdown mode and reduces the supply current to 0.1µA. In shutdown the control circuitry and the internal NMOS and PMOS turn off and SW becomes high impedance disconnecting the input from the output. The output capacitance and load current determine the voltage decay rate. For normal operation connect EN to VIN or logic high. Note: Pin EN should not be left floating.
9 Application Information
and DVD players, PDA’s and palmtop computers and any other handheld instruments. Figure 22. Single Li-Ion 1.2V/600mA Regulator for High-Efficiency Figure 23. 5V Input to 3.3V/600mA Buck Regulator Figure 24. Single Li-Ion 1.5V/600mA Regulator for High-Efficiency
Figure 25. Single Li-Ion 1.8V/600mA Regulator for Low Output Ripple
9.1 External Component Selection
9.2 Inductor Selection
higher inductance and increases with higher VIN or VOUT . current will rise above the calculated value during heavy load transients. The recommended starting point for setting ripple current is ΔIL = 240mA (40% of 600mA). The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. current rating fitting to the maximum switch current limit of the converter. Note: For highest efficiency, a low DC-resistance inductor is recommended. and lower output current capability.
- The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
- Additional losses in the conductor from the skin effect (current displacement at high frequencies)
- Magnetic field losses of the neighboring windings (proximity effect)
Figure 26. Efficiency Comparison of Different Inductors, VIN = 2.7V, VOUT = 1.8V and 1.2V
9.3 Output Capacitor Selection
output voltage ripple low ESR ceramic capacitors are recommended. X7R or X5R dielectric output capacitor are recommended. operation, ceramic capacitors can be used to achieve very low output ripple and accommodate small circuit size.
9.4 Input Capacitor Selection
even significant deviations only provide negligible affects. The input capacitor can be increased without any limit for better input voltage filtering. Take care when using small ceramic input capacitors. instability, or could even damage the part by exceeding the maximum ratings.
9.4.1 Ceramic Input and Output Capacitors
capacitance over temperature, become resistive at high frequencies and therefore should not be used. capacity or a capacitance with a higher rated voltage is used.
9.5 Feedback Resistor Selection
voltage sensing and adjustment. Figure 27. Setting the AS1324 Output Voltage higher resistance of R 1 and R 2 will result in a lower leakage current at the output. It is recommended to keep VIN 500mV higher than VOUT .
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9.6 Efficiency
The efficiency of a switching regulator is equivalent to: Efficiency = (POUT /PIN )100% (EQ 8) For optimum design, an analysis of the AS1324 is needed to determine efficiency limitations and to determine design changes for improved efficiency. Efficiency can be expressed as: Efficiency = 100% – (L 1 + L 2 + L 3 + ...) (EQ 9) Where: L 1, L 2, L 3, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, those four main sources should be considered for efficiency calculation:
9.6.1 Input Voltage Quiescent Current Losses
The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN , even at no load. The VIN quiescent current loss dominates the efficiency loss at very low load currents.
9.6.2 I²R Losses
Most of the efficiency loss at medium to high load currents are attributed to I²R loss, and are calculated from the resistances of the internal switches (R SW) and the external inductor (R L). In continuous mode, the average output current flowing through inductor L is split between the internal switches. Therefore, the series resistance looking into the SW pin is a function of both NMOS & PMOS R DS(ON) as well as the duty cycle (DC) and can be calculated as follows: RSW = (RDS(ON)PMOS )(DC) + (RDS(ON)NMOS )(1 – DC) (EQ 10) The RDS(ON) for both MOSFETs can be obtained from the Electrical Characteristics on page 4 . Thus, to obtain I²R losses calculate as follows: I²R losses = I OUT ²(R SW + R L) (EQ 11)
9.6.3 Switching Losses
The switching current is the sum of the control currents and the MOSFET driver. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. If a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode: IGC = f(Q PMOS + Q NMOS ) (EQ 12) Where: Q PMOS and Q NMOS are the gate charges of the internal MOSFET switches. The losses of the gate charges are proportional to V IN and thus their effects will be more visible at higher supply voltages.
9.6.4 Other Losses
Basic losses in the design of a system should also be considered. Internal battery resistances and copper trace can account for additional efficiency degradations in battery operated systems. By making sure that C IN has adequate charge storage and very low ESR at the given switching frequency, the internal battery and fuse resistance losses can be minimized. CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss.
9.7 Thermal Shutdown
Due to its high-efficiency design, the AS1324 will not dissipate much heat in most applications. However, in applications where the AS1324 is running at high ambient temperature, uses a low supply voltage, and runs with high duty cycles (such as in dropout) the heat dissipated may exceed the maximum junction temperature of the device. As soon as the junction temperature reaches approximately 150ºC the AS1324 goes in thermal shutdown. In this mode the internal PMOS & NMOS switch are turned off. The device will power up again, as soon as the temperature falls below +145°C again.
9.8 Checking Transient Response
The main loop response can be evaluated by examining the load transient response. Switching regulators normally take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equivalent to: VDROP = ΔIOUT x ESR (EQ 13) Where: ESR is the effective series resistance of C OUT . ΔIOUT also begins to charge or discharge COUT , which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady-state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem.
9.9 Design Example
600mA (max) but most of the time the device will require only 2mA (standby mode current). Figure 28. Design Example Therefore, a standard 2.2µH inductor should be used for this design.
9.10 Layout Considerations
The AS1324 requires proper layout and design techniques for optimum performance. The power traces (GND, SW, and VIN ) should be kept as short, direct, and wide as is practical. should be avoided to minimize the output voltage ripple and to maintain the stability of the regulator. The resistive divider (R 1/R 2) must be connected between the positive plate of COUT and ground. Switching node SW should be kept far away from the sensitive VFB node. The negative plates of CIN and COUT should be kept as close to each other as is practical. A starpoint to Ground is recommended. Figure 29. AS1324 Basic PCB Layout Figure 30. AS1324 Basic Diagram
The device is available in an 5-pin TSOT-23 package. Figure 33. 5-pin TSOT-23 Package
Figure 34. 5-pin TSOT-23 Marking
www.ams.com/DC-DC_Step-Up/AS1324 Revision 1.06 20 - 21 AS1324 Datasheet The device is available as the following standard versions. Note: All products are RoHS compliant. Buy our products or get free samples online at ICdirect: http://www.ams.com/ICdirect Technical Support is found at http://www.ams.com/Technical-Support For further information and requests, please contact us mailto:sales@ams.com or find your local distributor at http://www.ams.com/distributor ams T able 7. Ordering Information Ordering Code Marking Output Description Delivery Form Package AS1324-BTTT-AD ASKR adjustable 1.5MHz, 600mA Synchronous DC/DC Converter Tape and Reel 5-pin TSOT-23 AS1324-BTTT-12 ASKT 1.2V 1.5MHz, 600mA Synchronous DC/DC Converter Tape and Reel 5-pin TSOT-23 AS1324-BTTT-15 ASKU 1.5V 1.5MHz, 600mA Synchronous DC/DC Converter Tape and Reel 5-pin TSOT-23 AS1324-BTTT-18 ASKS 1.8V 1.5MHz, 600mA Synchronous DC/DC Converter Tape and Reel 5-pin TSOT-23
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