AS1312 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 20
Technical content
1 General Description
The AS1312 is an ultra low IQ hysteretic step-up DC-DC converter. 50mV steps from +2.5V to 5.0V. the internal operating blocks are turned off in order to save power. provided that the output is in regulation. working as Power-OK when LBI is connected to GND. Figure 1. AS1312 - Typical Application Diagram
2 Key Features
3 Applications
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
4.1 Pin Descriptions
GND, LBO is working as Power Output OK. A3 3 LX External Inductor Connector. B4 5 REF Reference Pin. Connect a 100nF ceramic capacitor to this pin. B3 6 LBO Low Battery Comparator Output . Open-drain output. Enable Pin . Logic controlled shutdown input. 0 = Shutdown; shutdown current <100nA. to achieve an optimal thermal performance.
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5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. T able 2. Absolute Maximum Ratings Parameter Min Max Units Comments Electrical Parameters VIN, VOUT, EN, LBI, LBO to GND -0.3 +7 V LX, REF to GND -0.3 V OUT + 0.3 V Input Current (latch-up immunity) -100 100 mA Norm: JED EC 78 Electrostatic Discharge Electrostatic Discharge HBM ±2 kV Norm: MIL 883 E meth od 3015 Temperature Ranges and Storage Conditions Thermal Resistance θJA TDFN 60 ºC/W Junction-to-ambient thermal resistance is very dependent on application and board-layout. In situations where high maximum power dissipation exists, special attention must be paid to thermal dissipation during board design. WL-CSP 97 Junction Temperature +125 ºC Storage Temperature Range -55 +150 ºC for 8-pin (2x2) TDFN -55 +125 ºC for 8-pin WL-CSP Package Body Temperature +260 ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020“Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). Humidity non-condensing 5 85 % Moisture Sensitive Level 1 Represents a maximum floo r life time of unlimited
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6 Electrical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed by production tests or SQC (Statistical Quality Control) methods. V IN = 1.5V, C1 = C2 = 22µF , CREF = 100nF , Typical values are at TAMB = +25ºC. Unless otherwise specified. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. T able 3. Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units TAMB Operating Temperature Range -40 85 °C TJ Operating Junction Temperature Range -40 125 °C Input VIN Input Voltage Range 0.7 5.0 V Minimum Startup Voltage T AMB = +25°C 0.9 V Regulation VOUT Output Voltage Range 2.5 5.0 V Output Voltage Tolerance ILOAD = 0mA to 10mA, TAMB = +25°C -2 +2 % ILOAD = 0mA to 10mA -4 +4 % ILOAD = 0mA to 30mA, TAMB = -20°C to +60°C -2 +2 % VOUT Lockout Threshold 1 Rising Edge 2.45 V Operating Current IQ Quiescent Current VIN VOUT = 1.02xVOUTNOM , REF = 0.99xVOUTNOM , TAMB = +25°C 100 nA Quiescent Current VOUT VOUT = 5V, No load, TAMB = +25°C 0.7 1 1.3 µA ISHDN Shutdown Current T AMB = +25ºC 100 nA Switches RON NMOS VOUT = 5V 0.4 Ω PMOS 0.45 Ω NMOS maximum on-time 3.3 4.0 4.6 µs IPEAK Peak current limit 400 mA Zero crossing current 5 20 35 mA Enable, Reference VENH EN input voltage ‘high’ 0.7 V VENL EN input voltage ‘low’ 0.1 V IEN EN input bias current EN = 5V, T AMB = +25°C 100 nA IREF REF input bias current REF = 0.99xV OUTNOM , TAMB = +25°C 100 nA Low Battery & Power-OK VLBI LBI threshold Falling edge 0.57 0.6 0.63 V LBI hysteresis 25 mV ILBI LBI leakage current LBI ≤ VIN or VOUT (which ever is higher), TAMB = +25°C 100 nA VLBO LBO voltage low
2 ILBO = 1mA 5 20 mV
www.ams.com/DC-DC_Step-Up Revision 1.12 5 - 20 AS1312 Datasheet - E l e c t r i ca l C h a ra c t e r i s t i c s ILBO LBO leakage current T AMB = +25°C 100 nA Power-OK threshold LBI = 0V, Falling Edge 87 91 95 % Thermal Protection Thermal shutdown 3 10°C Hysteresis 150 °C 1. The regulator is in startup mode until this voltage is reached. Caution: Do not apply full load current until the device output > 2.5V 2. LBO goes low in startup mode as well as during no rmal operation if, (i) The voltage at the LBI pin is higher than LBI threshold. (ii) The voltage at the LBI pin is below 0.1V (connected to GND) and VOUT is below 92.5% of its nominal value. 3. Further switching is inhibited. T able 3. Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units
7 Typical Operating Characteristics
VOUT = 5.0V, TAMB = +25°C, unless otherwise specified. Figure 3. Efficiency vs. Output Current Figure 4. Efficiency vs. Output Current Figure 5. Efficiency vs. Input Voltage Figure 6. M aximum Output Current vs. Input Voltage Figure 7. Start-up Voltage vs. Output Current Figur e 8. Output Voltage Ripple; VIN = 2V, Rload = 100 Ω
8 Detailed Description
8.1 Hysteretic Boost Converter
determined by external component (inductor and capacitors) and also the loading on the output. value of VOUT (0.99 x VOUT ). Inductor current is monitored by the control loop, ensuring that operation is always dis-continuous. offered as a guide to changing the passive components to more closely match the end requirement.
8.1.1 Input Loop Timing
independent of input voltage changes. As a result, no line regulation exists. Figure 9. Simplified Boost DCDC Architecture
Figure 10. Simplified Voltage and Current Waveforms threshold (0.99xVOUT ), the output is assumed to be in regulation and no further switching occurs.
8.1.2 Inductor Choice Example
For the AS1312 V IN_MIN = 0.9V, V OUT_MAX = 3.3V, (EQ 5) gives Ton=2.66T OFF . Let the maximum operating on-time = 1µs. LMAX = 1.875µH. The nearest preferred value is 2.2µH. This value provides the maximum energy storage for the chosen fixed on-time limit at the minimum VIN .
www.ams.com/DC-DC_Step-Up Revision 1.12 9 - 20 AS1312 Datasheet - D e t a i l e d D e s c r i p t i o n Energy stored during the on time is given by: Joules (Region A in Figure 10 ) (EQ 6) If the overall time period (T ON + T OFF ) is T, the power taken from the input is: Watts (EQ 7) Assume output power is 0.8 P IN to establish an initial value of operating period T. TWAIT is determined by the time taken for the output voltage to fall to 0.99xV OUT . The longer the wait time, the lower will be the supply current of the converter. Longer wait times require increased output capacitance. Choose T WAIT = 10% T as a minimum starting point for maximum energy transfer. For very low power load applications, choose T WAIT ≥ 50% T.
8.1.3 Output Loop Timing
The output loop consists of the main inductor, P-channel synchronous switch (or diode if fitted), output capacitor and load. When the input loop is interrupted, the voltage on the LX pin rises (Lenz’s Law). At the same time a comparator enables the synchronous switch, and energy stored in the inductor is transferred to the output capacitor and load. Inductor peak current supports the load and replenishes the charge lost from the output capacitor. The magnitude of the current from the inductor is monitored, and as it approaches zero, the synchronous switch is turned off. No switching action continues until the output voltage falls below the output reference point (0.99 x VOUT ). Output power is composed of the dc component (Region C in Figure 10 ): PREGION_C = (EQ 8) Output power is also composed of the inductor component (Region B in Figure 10 ), neglecting efficiency loss: PREGION_B = (EQ 9) Total power delivered to the load is the sum of (EQ 8) and (EQ 9) : (EQ 10) From (EQ 3) (using nominal values) peak current is given by: (EQ 11) Substituting (EQ 11) into (EQ 10) and re-arranging: (EQ 12) 0.9T incorporates a wait time T WAIT = 10% T Output power in terms of regulated output voltage and load resistance is: (EQ 13) Combining (EQ 12) and (EQ 13) : (EQ 14) Symbol η reflects total energy loss between input and output and is approximately 0.8 for these calculations. Use (EQ 14) to plot duty cycle (T ON /T) changes for various output loadings and changes to VIN . E 0,5 L I PK ( ) 2= P IN 0,5 L I PK ( ) 2 V IN IPK 0,5 L I PK ( ) 2 P TOTAL V IN IPK IPK TON V IN P TOTAL V 2 IN TON P OUT V 2 OUT R LOAD V 2 OUT R LOAD IN TON
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8.1.4 Input Capacitor Selection
The input capacitor supports the triangular current during the on-time of the power switch, and maintains a broadly constant input voltage during this time. The capacitance value is obtained from choosing a ripple voltage during the on-time of the power switch. Additionally, ripple voltage is generated by the equivalent series resistance (ESR) of the capacitor. For worst case, use maximum peak current values from the datasheet. (EQ 15) Using T ON = 1µs, and I PEAK = 400mA (typ), and V RIPPLE = 50mV, EQ 15 yields: CIN = 8.0µF Nearest preferred would be 10µF. (EQ 16) Typically, the ripple due to ESR is not dominant. ESR for the recommended capacitors (Murata GMR), ESR = 5m Ω to 10m Ω . For the AS1312, maximum peak current is 400mA. Ripple due to ESR is 2.0mV to 4.0mV. Ripple at the input propagates through the common supply connections, and if too high in value can cause problems elsewhere in the system. The input capacitance is an important component to get right.
8.1.5 Output Capacitor Selection
The output capacitor supports the triangular current during the off-time of the power switch (inductor discharge period), and also the load current during the wait time (Region D in Figure 10 ) and on-time (Region A in Figure 10 ) of the power switch. (EQ 17) Note: There is also a ripple component due to the equivalent series resistance (ESR) of the capacitor.
8.2 Summary
User Application Defines: VIN min, VIN max, VOUT min, VOUT max, I LOAD min, I LOAD max Inductor Selection: Select Max on-time = 0.5µs to 3µs for AS1312. Use (EQ 3) to calculate inductor value. Use (EQ 5) to determine off-time. Use (EQ 6) to check that power delivery matches load requirements assume 70% conversion efficiency. Use (EQ 13) to find overall timing period value of T at min V IN and max V OUT for maximum load conditions. Input Capacitor Selection: Choose a ripple value and use (EQ 14) to find the value. Output Capacitor Selection: Determine T WAIT via (EQ 6) or (EQ 13) , and use (EQ 16) to find the value. C IN IPEAK TON V RIPPLE ESR PK ESR RIPPLE PK RIV =__ NOM OUT WAIT ON LOAD OUT V TTIC _) 99 . 01 (
9 Application Information
The AS1312 is available with fixed output voltages from 2.5V to 5.0V in 50mV steps. Figure 11. AS1312 - Block Diagram
9.1 AS1312 Features
The part is in shutdown mode while the voltage at pin EN is below 0.1V and is active when the voltage is higher than 0.7V. Note: EN can be driven above VIN or VOUT , as long as it is limited to less than 5.0V. During shutdown VOUT is going to 0V and no current from the input source is running through the device. If the input voltage is higher than the output voltage (and the AS1312 is enabled) the supply voltage is connected to the load through the device. To guarantee a proper function of the AS1312 it is not allowed that the supply exceeds the maximum allowed input voltage (5.0V).
9.1.1 Power-OK and Low-Battery-Detect Functionality
- The voltage at the LBI pin is below LBI threshold (0.6V). This can be used to monitor the battery voltage.
- LBI pin is connected to GND and V OUT is below 92.5% of its nominal value. LBO works as a power-OK signal in this case.
with no additional external components. GND may be added to generate a power-on-reset delay. To obtain a logic-level output, connect a pull-up resistor R 3 from pin LBO to pin VOUT . Figure 12. Typical Application with adjustable Battery Monitoring Figure 13. Typical Application with LBO working as Power-OK
9.1.2 Thermal Shutdown
junction temperature exceeds 150°C. To resume the normal operation the temperature has to drop below 140°C. recommended to use multiple vias in the printed circuit board. It’s also recommended to solder the Exposed Pad (pin 9) to the GND plane. Note: Continuing operation in thermal overload conditions may damage the device and is considered bad practice.
9.2 Component Selection
value, low profile inductors and tiny external ceramic capacitors.
9.3 Inductor Selection
500mA current rating and < 500m Ω DCR is recommended.
9.4 Capacitor Selection
for a list of capacitors for input and output capacitor selection. On the pin REF a 100nF capacitor with an Insulation resistance >1G Ω is recommended. Table 5. Recommended Input and Output Capacitors
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9.5 Layout Considerations
Relatively high peak currents of 400mA (typ) circulate during normal operation of the AS1312. Long printed circuit tracks can generate additional ripple and noise that mask correct operation and prove difficult to “de-bug” during production testing. Referring to Figure 1, the input loop formed by C1, VIN and GND pins should be minimized. Similarly, the output loop formed by C2, VOUT and GND should also be minimized. Ideally both loops should connect to GND in a “star” fashion. Finally, it is important to return CREF to the GND pin directly.
The device is available in a 8-pin (2x2) TDFN and 8-pin WL-CSP package. Figure 14. 8-pin (2x2) TDFNMarking Figure 15. 8-pin WL-CSP Marking
Figure 16. 8-pin (2x2) TDFN Drawings and Dimensions
- Dimensioning & tolerancing conform to ASME Y14.5M-1994 .
- All dimensions are in millimeters. Angles are in degrees.
- Coplanarity applies to the exposed heat slug as well as the terminal.
- Radius on terminal is optional.
- N is the total number of terminals.
Figure 17. 8-pin WL-CSP Drawings and Dimensions
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Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 1.0 afe Initial revision 1.5
26 Mar, 2012 Updated Detailed Description and Application Information sections
1.6 1.7 27 Apr, 2012 Detailed Description section updated 1.8 19 Jul, 2012 Added info on Thermal resistance, conditions for Output Voltage Tolerance. Updated ordering table. 1.9 10 Aug, 2012 Updated storage temp values for WL-CSP 1.10 17 Aug, 2012 Updated (EQ 17) 1.11 14 Sep, 2012 Updated conditions for ‘Output Voltage Tolerance’ parameter (see page 4) 1.12 14 Oct, 2013 tka Update Green & ROHS logo, update ordering information
www.ams.com/DC-DC_Step-Up Revision 1.12 19 - 20 AS1312 Datasheet - O r d e r i n g I n f o r m a t i o n The device is available as the standard products listed below. T able 8. Ordering Information Ordering Code Marking VOUT Description Delivery Form Package AS1312-BTDT-50 BE 5.0V Ultra Low Quiescent Current, Hysteretic DC-DC Step-Up Converter Tape and Reel 8-pin (2x2) TDFN AS1312-BTDT-33 BX 3.3V Tape and Reel 8-pin (2x2) TDFN AS1312-BWLT-50 BF 5.0V Tape and Reel 8-pin WL-CSP AS1312-BWLT-45 BQ 4.5V Tape and Reel 8-pin WL-CSP AS1312 1. Non-standard devices from 2.5V to 5.0V are availa ble in 50mV steps. For more information and inquiries contact http://www.ams.com/contact All products are RoHS compliant and ams green. Buy our products or get free samples online at www.ams.com/ICdirect Technical Support is available at www.ams.com/Technical-Support For further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor tbd xx Tape and Reel tbd
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