AS1160 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 29
Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pinout
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 7 Typical Operating Characteristics AS1160
- 8 Typical Operating Characteristics AS1161
- 9 Timing Diagrams
- 10 Detailed Description
- 11 Application Information
- 12 Package Drawings and Markings
- 13 Ordering Information
1 General Description
single high-speed LVDS serial data stream with clock. data bus with recovered parallel clock. and Test Mode Select, Test Clock, and Test Reset). deserializer to be verified at-speed. to-data skew are eliminated. Figure 1. Block Diagrams
2 Key Features
3 Applications
workswitches and routers or backplane interconnect.
4 Pinout
Figure 2. AS1160 Pin Assignments (Top View) Table 1. AS1160 Pin Descriptions active edge for strobing of DINx data. DO+ + Serial Data Output. Non-inverting Bus LVDS differential output. DO- - Serial Data Output. Inverting Bus LVDS differential output. outputs are in tri-state condition. outputs and puts the device into low power sleep mode. TCLK Transmit Clock. LVTTL level input. Input for 20MHz to 66MHz system clock. asserted. SYNC1 and SYNC2 pins are combined through an OR gate. DVDD +3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry. DGND Digital Circuit Ground. GND reference point for the digital part of the AS1160. transient basis. Both supplys should be decoupled by a capacitor of typically 10nF. AGND Analog Ground (PLL and Analog Circuits). N/C No Connection. Leave open-circuit, do not connect these pins.
Figure 3. AS1161 Pin Assignments (Top View) Table 2. AS1161 Pin Descriptions ROUT0:ROUT9 Data Output. ±4mA CMOS level outputs. active edge for strobing of ROUT0:ROUT9 data. REFCLK Reference Clock Input. LVTTL level input. Input for 20MHz - 66MHz system clock. RI+ + Serial Data Input. Non-inverting Bus LVDS differential input. RI- - Serial Data Input. Inverting Bus LVDS differential input. the outputs and puts the device into low power sleep mode. transient basis. Both supplys should be decoupled by a capacitor of typically 10nF. AGND Analog Ground (PLL and Analog Circuits). N/C No Connection. Leave open-circuit, do not connect these pins.
5 Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings Solid State Surface Mount Devices”.
6 Electrical Characteristics
VDD = 3.3V (unless otherwise specified). Table 4. Electrical Characteristics Table 5. Serializer Timing Requirements for TCLK Table 6. Serializer Switching Characteristics1
SQC (Statistical Quality Control) methods.
- Guaranteed by simulation and characterization.
- For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK
PATs). The derserializer should be initialized using either tDSR1 or tDSR2. mode. SYNCPATs should be sent to the device before initiating either condition. RI-) conditions change from not receiving data to receiving SYNCPATs.
- tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream
before bit errors occur. The deserializer noise margin is guaranteed by design using statistical analysis. Table 10. Scan Circuitry Timing Requirements
25 MHz
Table 9. Deserializer Switching Characteristics1
7 Typical Operating Characteristics AS1160
Figure 4. Supply Current vs Supply Voltage Figure 5. Power-Down Current vs Supply Voltage Figure 6. Supply Current vs Clock Frequency Figure 7. Supply Current vs Temperature Figure 8. Power-Down Current vs. Temperature Fi gure 9. Deterministic Jitter vs. Temperature Deterministic Jitter (Pk-Pk) (ps) .
8 Typical Operating Characteristics AS1161
Figure 10. Supply Current vs Supply Voltage Figure 11. Power-Down Current vs Supply Voltage Figure 12. Supply Current vs Clock Frequency Figure 13. Supply Current vs Temperature Figure 14. Power-Down Current vs. Temperature
9 Timing Diagrams
Figure 15. JTAG Timing Diagram Figure 16. Worst-Case Serializer ICC Test Pattern Figure 17. Worst-Case Deserializer ICC Test Pattern
Figure 32. Definition of Deterministic Jitter (tDJIT) Figure 33. Receiver Bus LVDS Input Skew Margin tSW is the setup and hold time (internal data sampling window). tDJIT is the serializer output bit position jitter as a result of jitter on TCLK. tRNM is the receiver noise time margin. Figure 34. Data Transfer Mode, VOD Diagram (VOD = DO+ - DO-)
0 Differential
www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 19 - 29 AS1160/AS1161 Datasheet - Detailed Description
10 Detailed Description
The serializer/deserializer chipset transfers 10 parallel LVTTL data bits over a serial Bus LVDS link up to 660Mbps at clock speeds from 20MHz to 66MHz. For the serializer, an on-board PLL serializes the input data and inserts two control bits (start & stop bit) into the data stream. The deserializer uses a separate reference clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and then deserialize the data. The deserializer monitors the incoming clock information, determines lock status and asserts the LOCKN output high when loss of lock occurs. Note: The chipset is also capable of driving data over unshielded twisted pair cable. The chipset has three active states of operation: - Initialization - Data Transfer - Resynchronization The chipset also has two passive states: - Powerdown - Tri-State Note: There are also test modes for JTAG access and at-speed BIST (built-in-self-test). Initialization Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of the serializer and deserializer PLLs to local clocks, which may be the same or separate. Afterwards, synchronization of the deserializer to the serializer occurs. 1. When VDD is applied and reaches a stable value between +3.0V and +3.6V, the PWDNN of the serializer has to stay low for at least 50µs to ensure proper operation (see Figure 23 on page 14), the respective output enter tri-state. After PWDNN is high the PLL in the serializer begins locking to a local clock. When VDD is applied to the deserializer, the respective outputs enter tri-state and an on-chip power-on circuitry disables internal circuitry. When VDD reaches VDDOK (2.5V) the PLL in the deserializer begins locking to a local clock. For the serializer, the local clock is the transmited clock (TCLK) provided by the source ASIC or other device. For the deserializer, a local clock must be applied to pin REFCLK that can be provided by any source. The serializer outputs remain in tri-state while the PLL locks to the TCLK. After locking to TCLK, the serializer is now ready to send data or SYNCPATs (SYNC patterns), depending on the levels of the SYNC1 and SYNC2 inputs or a data stream. The SYNCPAT sent by the serializer consists of six ones and six zeros switching at the input clock rate. Note that the deserializer LOCKN output will remain high while its PLL locks to the incoming data or to SYNCPATs on the input. 2. The deserializer PLL must synchronize to the serializer to complete initialization. The deserializer will lock to non-repetitive data patterns. However, the transmission of SYNCPATs enables the deserializer to lock to the serializer signal within a specified time (see Figure 24 on page 14). The application determines control of pins SYNC1 and SYNC2. A direct feedback loop from the LOCKN pin is mandatory (see Figure 36 on page 23). In all cases the serializer stops sending SYNCPATs after both SYNC inputs return low. When the deserializer detects edge transitions at the bus LVDS input, it will attempt to lock to the embedded clock information. When the deserializer locks to the bus LVDS clock, the LOCKN output will go low. When LOCKN is low, the deserializer outputs represent incoming bus LVDS data.
DIN0:DIN9 is ignored regardless of clock edge. After determining which clock edge to use a start and stop bit, appended internally, frame the data bits in the register. times the TCLK frequency. For example, if TCLK is 66MHz, the serial rate is 66 x 12 = 792 mega bits per second. limited multiple deserializers. The outputs transmit data when DEN, PWDNN are high and SYNC1, SYNC2 are low. Note: When DEN is driven low, the serializer output pins will enter tri-state. Figure 35. Multidrop Configuration OUT0:ROUT9 data is valid when LOCKN is low, otherwise ROUT0:ROUT9 is invalid. input gates (15pF load) with a 66MHz clock.
www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 21 - 29 AS1160/AS1161 Datasheet - Detailed Description Resynchronization When the deserializer PLL locks to the embedded clock edge, the deserializer LOCKN pin asserts a low. If the deseri- alizer loses lock, pin LOCKN output will go high and the outputs (including RCLK) will enter tri-state. The user’s system monitors the pin LOCKN to detect a loss of synchronization. Upon detection, the system can arrange to pulse the serializer SYNC1 or SYNC2 pin to resynchronize. Multiple resynchronization approaches are possible. It is mandatory to provide a feedback loop using pin LOCKN to control the SYNC request of the serializer (SYNC1 or SYNC2). Two SYNC pins are provided for multiple control in a multi-drop application. Sending SYNCPATs for resynchronization is desirable when lock times within a specific time are critical. Powerdown The low-power powerdown mode can be used while no data transfer is taking place. The serializer and deserializer use the powerdown mode to reduce power consumption by: - The deserializer enters powerdown when pins PWDNN and REN are low. - The serializer enters powerdown when pin PWDNN is driven low. In powerdown, the PLL stops and the outputs enter tri-state, which disables load current and reduces supply current to the µA range. Note: To exit powerdown, drive pin PWDNN high. Before valid data exchanges between the serializer and deserializer, the devices must re-initialized and resynchro- nized to each other. Initialization of the serializer takes a maximum of 400 TCLK cycles. The deserializer will initialize and assert LOCKN high until lock to the Bus LVDS clock occurs. Tri-State The serializer enters tri-state when pin DEN is driven low. This puts both driver output pins (DO+ and DO-) into tri- state. When DEN is driven high, the serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWDNN, TCKR/FN). When pin REN is driven low, the deserializer enters tri-state. Consequently, the receiver output pins (ROUT0:ROUT9) and RCLK will enter tri-state. The LOCKN output remains active, reflecting the state of the PLL.
itor should be closest to the pin. transmit data. Phase locking occurs when the deserializer locks to incoming data or when the serializer sends patterns. except for the specific case of loss of lock during transmission (see Lock Loss Recovery on page 23). Table 11. Deserializer Truth Table
- Active indicates the RCLK will be running if the deserializer is locked. The timing of RCLK with respect to
- Active indicates the LOCKN output will reflect the state of the deserializer with regard to the selected data
Figure 36. Typical Application stream and the deserializer LOCKN pin goes low, at least three previous data cycles should be suspect for bit errors. The deserializer can re-lock to the incoming data stream by making the serializer re-send SYNCPATs. As all BLVDS devices the AS1161 is hot pluggable but you have to follow some rules. Note: When removing the device, the pin groups should be removed in reverse order from insertion.
sible is the best method to ensure signal integrity. output signals are separated. mode in the twisted pair is rejected by the differential receiver. placed as close together as possible. provides a +1.2V common mode range at the receiver inputs. Figure 37. Double-Terminated Point-to-Point ure 35 on page 20), through a PCB trace or through twisted pair cable (see Figure 37). one termination the reflections and the differential signal swing are larger compared to a double termination.
Instructions supported by the AS1160/AS1161 and its respective operational binary codes are shown in Table 12. device. SAMPLE/PRELOAD also allows the device to shift data into the boundary scantest data register through TDI. test data register. This allows data to pass from TDI to TDO without affecting the device’s normal operation. Implemented at LVDS levels as a go/no-go test (e.g. missing cables). The AS1160/AS1161 ID code is provided to the TDO output. An at-system-speed interconnect test instruction. It is executed in approximately 33mS (@ 66MHz system speed). that the BER (bit-error-rate) is better than 10-7. with some multi-drop devices. Table 12. Instruction Codes Table 13. 32bit ID Code
The device is available in an CTBGA 49-bumps package. Figure 40. CTBGA 49-bumps Package
The devices are available as the standard products shown in Table 14. Note: All products are RoHS compliant and Pb-free. Table 14. Ordering Information
www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 29 - 29 AS1160/AS1161 Datasheet Copyrights Copyright © 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact