AS1154_V2 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 16
Technical content
1 General Description
(400MHz) over controlled impedance media of approximately 100Ω. separating the LVTTL/LVCMOS inputs and LVDS outputs. operation from -40°C to +85°C. Figure 1. AS1154 - Block Diagram
2 Key Features
3 Applications
4 Pinout
Figure 2. Pin Assignments (T op View) Table 1. Pin Descriptions 1V C C Power Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
5 Absolute Maximum Ratings
absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings
- Depending on actual PCB layout and PCB used.
- P DERATE derating factor changes the total continuous power dissipation (PT) if the ambient temperature is not 70ºC. Therefore for e.g.
6 Electrical Characteristics
- Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD.
- Guaranteed by correlation data.
- All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality
Table 3. DC Electrical Characteristics
7 Typical Operating Characteristics
Figure 3. Transition Time vs. VCC Figure 4. Transition Time vs. T emperature Figure 5. Differential Pulse Skew vs. VCC Figure 6. Pulse Skew vs. T emperature Differential Pulse Skew (ps) . Diff. Propagation Delay (ns) . Diff. Propagation Delay (ns) .
www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Revision 1.02 9 - 16 AS1154 Datasheet - Detailed Description
8 Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication stan- dards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The AS1154 is an 800Mbps dual differential LVDS driver that is designed for high-speed, point-to-point, low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The AS1154 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This current steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are short-circuit cur- rent limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the AS1154 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver (AS1157, AS1158). Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the AS1154 produces an output voltage of 370mV when driving a 100Ω load. Termination Because the AS1154 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The AS1154 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may range between 90 and132Ω, depending on the characteristic impedance of the transmission medium.
9 Applications
Figure 19. Typical Application Circuit smaller valued capacitor closest to pin VCC. Input trace characteristics can adversely affect the performance of the AS1154. Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each other. Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices. constant distance between the differential traces to avoid irregularities in differential impedance. Avoid 90° turns (use two 45° turns). Minimize the number of vias to further prevent impedance irregularities. Table 5. Function T able
Supported transmission media include printed circuit board traces, backplanes, and cables. Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches. anced cables pick up noise as common mode, which is rejected by the LVDS receiver. Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. The device should be placed as close to the interface connector as possible to minimize LVDS trace length. Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 20. Driver Propagation Delay and Transition Time Waveforms
0 Differential
Figure 23. 8-pin SOIC Marking Table 6. Packaging Code AYWWRZZ
Figure 24. 8-pin SOIC Package
The devices are available as the standard products shown in Table 7. Note: All products are RoHS compliant. Table 7. Ordering Information
www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Revision 1.02 16 - 16 AS1154 Datasheet Copyrights Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact