AS1153_V2 AMSCO
Document overview
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Technical content
1 General Description
resistor when used in a point-to-point connection. open, undriven and terminated, or undriven and shorted. separating the LVDS inputs and LVCMOS outputs. The devices are available in a 8-pin SOIC package. Figure 1. AS1153, AS1157 - Block Diagram
2 Key Features
3 Applications
4 Pinout and Packaging
Figure 2. Pin Assignments (T op View) Table 1. Pin Descriptions 8V C C Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
5 Absolute Maximum Ratings
absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings
6 Electrical Characteristics
2.4V - |VID/2|,TAMB = -40°C to +85ºC. Typical values are at VCC = +3.3V, TAMB = +25ºC (unless otherwise specified). Table 3. DC Electrical Characteristics
- Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH,
- Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
- AC parameters are guaranteed by design and characterization.
- CL includes scope probe and test jig capacitance.
- tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
- tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same device.
- tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated conditions at the same
VCC and within 5ºC of each other.
- tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated conditions.
- fMAX generator output conditions:
Table 4. AC Electrical Characteristics
7 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 10pF , TAMB = +25ºC, unless otherwise noted. Figure 3. Supply Current vs. Frequency Figure 4. Supply Current vs. Temperature Figure 7. Output Low Voltage vs. VCC Figure 8. Output High Voltage vs. VCC Differential Output Voltage (mV) .
8 Detailed Description
from 100mV to 1V within an input voltage range of 0 to 2.4V. common mode effect of coupled noise, can be tolerated. dards, resulting in higher data rates, reduced power consumption and EMI emissions, and less susceptibility to noise. The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground. The devices contain an integrated Failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or undriven and shorted. circuit pulls both inputs above VCC - 0.3V, activating the Failsafe circuit and thus forcing the device output high. Figure 18. Failsafe Input Circuit
9 Applications
Figure 19. Typical Application Circuit smaller valued capacitor closest to pin VCC. Input trace characteristics can adversely affect the performance of the AS1153, AS1157. this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running differential traces close together. Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices. constant distance between the differential traces to avoid irregularities in differential impedance. Avoid 90° turns (use two 45° turns). Minimize the number of vias to further prevent impedance irregularities. Table 5. Function T able
Supported transmission media include printed circuit board traces, backplanes, and cables. Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches. anced cables pick up noise as common mode, which is rejected by the LVDS receiver. Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections, and reduce EMI. the characteristic impedance of the transmission medium. Use 1% surface-mount resistors. The device should be placed as close to the interface connector as possible to minimize LVDS trace length. Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 20. Propagation Delay and Transition Time T est Circuit
- 50Ω required for pulse generator.
to account for internal termination resistor.
Figure 21. Propagation Delay and Transition Time Waveforms
Figure 22. 8-pin SOIC Marking Table 6. Packaging Code xxxx
Figure 23. 8-pin SOIC Package Diagram
The devices are available as the standard products shown in Table 7. Note: All products are RoHS compliant. Table 7. Ordering Information
www.austriamicrosystems.com/Interfaces-LVDS/AS1153 Revision 1.02 16 - 16 AS1153, AS1157 Datasheet Copyrights Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact