AS1153 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 15
Technical content
1 General Description
rates and reduced EMI emissions. media are PCB traces, backplanes, and cables. AS1153/57 are dual LVDS receivers. in a point-to-point connection. The devices are available in a 8-pin SOIC package. Figure 1. Block Diagrams
2 Key Features
3 Applications
4 Pinout and Packaging
Figure 2. AS1153/55 and AS1157/58 Pin Assignments (Top View) Table 1. AS1153/55 and AS1157/58 Pin Descriptions
11 I N 1 - Inverting Differential Receiver Input
22 I N 1 + Noninverting Differential Receiver Input
55 G N D Ground
77 O U T 1 LVCMOS/LVTTL Receiver Output
88 V CC
5 Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
6 Electrical Characteristics
2.4V - |VID/2|,TAMB = -40 to +85ºC. Typical values are at VCC = +3.3V, TAMB = +25ºC (unless otherwise specified). Table 3. DC Electrical Characteristics
- Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced
to ground except VTH, VTL, and VID.
- Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
- AC parameters are guaranteed by design and characterization.
- CL includes scope probe and test jig capacitance.
- tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
- tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other chan-
- tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions at the same VCC and within 5ºC of each other.
- tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated
- fMAX generator output conditions:
Table 4. AC Electrical Characteristics
7 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 10pF, TAMB = +25ºC, unless otherwise noted. Figure 3. Supply Current vs. Frequency Figure 4. Supply Current vs. Temperature Figure 7. Output Low Voltage vs. VCC Figure 8. Output High Voltage vs. VCC Differential Output Voltage (mV) .
8 Detailed Description
ences of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated. and EMI emissions, and less susceptibility to noise. The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground. other words, the transmission line is terminated on the IC. AS1157/58 automatically sets the output high if any of these conditions are true.
- 0.3V, activating the Failsafe circuit and thus forcing the device output high.
Figure 18. Failsafe Input Circuit
9 Applications
Figure 19. Typical Application Circuit device as possible, with the smaller valued capacitor closest to pin VCC. Input trace characteristics can adversely affect the performance of the AS1155/58 and AS1153/57. must also be matched to this characteristic impedance. ! Eliminate reflections and ensure that noise couples as common mode by running differential traces close together. data recovery of the devices. ! Avoid 90° turns (use two 45° turns). ! Minimize the number of vias to further prevent impedance irregularities. Supported transmission media include printed circuit board traces, backplanes, and cables. Table 5. Function Table
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. integrated resistor is specified in Table 3. medium. Use 1% surface-mount resistors. The device should be placed as close to the interface connector as possible to minimize LVDS trace length. ! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. ! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. ! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 20. Propagation Delay and Transition Time Test Circuit
- 50Ω required for pulse generator.
put to account for internal termination resistor.
Figure 21. Propagation Delay and Transition Time Waveforms
The AS1155/58 and AS1153/57 are available in a 8-pin SOIC package. Figure 22. 8-pin SOIC Package Diagram
- Lead coplanarity should be 0 to 0.10MM max.
- Package surface finishing:
- All dimension excluding Mold Flashes and End Flash from the package body shall not exceed 0.25MM per side (D)
- Details of PIN #1 identifier are optional, but must be located within the zone indicated.
Table 6. 8-pin SOIC Package Dimensions
www.austriamicrosystems.com Revision 1.01 14 - 15 AS1153/55 Data Sheet - Ordering Information Part Number Marking Description Delivery Form Package Type AS1155 AS1155 Single LVDS Receiver Tubes 8-pin SOIC AS1155-T AS1155 Single LVDS Receiver Tape and Reel 8-pin SOIC AS1158 AS1158 Single LVDS Receiver, with termination Tubes 8-pin SOIC AS1158-T AS1158 Single LVDS Receiver, with termination Tape and Reel 8-pin SOIC AS1153 AS1153 Dual LVDS Receiver Tubes 8-pin SOIC AS1153-T AS1153 Dual LVDS Receiver Tape and Reel 8-pin SOIC AS1157 AS1157 Dual LVDS Receiver, with termination Tubes 8-pin SOIC AS1157-T AS1157 Dual LVDS Receiver, with termination Tape and Reel 8-pin SOIC
www.austriamicrosystems.com Revision 1.01 15 - 15 AS1153/55 Data Sheet Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami- crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact