AS1152 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 15
Technical content
1 General Description
are PCB traces, backplanes, and cables. MOS inputs and LVDS outputs. specified for operation from -40 to +85°C. Figure 1. Block Diagram
2 Key Features
3 Applications
4 Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings
5 Electrical Characteristics
- Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are
- Currents into the device are positive, and current out of the device is negative. All voltages are referenced to
- Guaranteed by correlation data.
Table 2. DC Electrical Characteristics
6 Typical Operating Characteristics
Figure 2. Output High Voltage vs. VCC Figure 3. Output Low Voltage vs. VCC Figure 4. Output Short-Circuit Current vs. VCC; Figure 5. Output High-Impedance State Current vs. Figure 6. Differential Output Voltage vs. VCC Figure 7. Differential Output Voltage vs. Load Differential Output Voltage (V) . Differential Output Voltage (mV) .
Figure 14. Differential Skew vs. VCC; Figure 15. Differential Skew vs. Temperature;
7 Pinout and Packaging
Figure 16. AS1152 Pin Assignments (Top View) Table 4. AS1152 Pin Descriptions Driver Enable Input. Internally pulled down to GND. combinations of EN and ENn, the outputs are disabled and in high impedance. Driver Enable Input. Internally pulled down to GND. combinations of EN and ENn, the outputs are disabled and in high impedance.
10 OUT4+ Noninverting LVDS Driver Output
11 OUT3+ Noninverting LVDS Driver Output
12 OUT3- Inverting LVDS Driver Output
13 OUT2- Inverting LVDS Driver Output
14 OUT2+ Noninverting LVDS Driver Output
15 OUT1+ Noninverting LVDS Driver Output
16 OUT1- Inverting LVDS Driver Output
www.austriamicrosystems.com Revision 1.00 9 - 15 AS1152 austria micro systems Data Sheet LVDS Interface
8 Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-imped- ance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower volt- age swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The AS1152 is an 500Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The AS1152 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This current steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed per- formance. The driver outputs are short-circuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the AS1152 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver (AS1150, AS1151). Logic states are deter- mined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the AS1152 produces an output voltage of 370mV when driving a 100Ω load. Note: The AS1152 is conform to the ANSI TIA/EIA 644 LVDS Standards when operating ≤150MHz. Paired with the AS1150 the datarate can be increased to 500Mbps. While operating faster then 150MHz, the rise and fall time, as well as the setup and hold time are not conform to the ANSI TIA/EIA 644 LVDS Standards. Termination Because the AS1152 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The AS1152 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may range between 90 and132Ω, depending on the characteristic impedance of the transmission medium.
9 Applications
Figure 17. Typical Application Circuit device as possible, with the smaller valued capacitor closest to pin VCC. Input trace characteristics can adversely affect the performance of the AS1152. also matched to this characteristic impedance. ! Avoid 90° turns (use two 45° turns). ! Minimize the number of vias to further prevent impedance irregularities. Table 5. Function Table
Supported transmission media include printed circuit board traces, backplanes, and cables. field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. The device should be placed as close to the interface connector as possible to minimize LVDS trace length. ! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. ! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. ! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 18. Driver Propagation Delay and Transition Time Waveforms Figure 19. Driver Propagation Delay and Transition Time Test Circuit
0 Differential
Figure 23. 16-pin TSSOP Package
- All dimensions are in millimeters; angles in degrees.
- Dimensioning and tolerancing per ASME Y14.5M – 1994.
- Dimension D does not include mold flash, protrusions, or gate
- Dimension E1 does not include interlead flash or protrusion.
- Dimension b does not include dambar protrusion. Allowable
located on the lower radius of the foot.
- Terminal numbers are for reference only.
- Datums A and B to be determined at datum plane H.
- Dimensions D and E1 are to be determined at datum plane H.
- This dimension applies only to variations with an even number
- Cross section A-A to be determined at 0.10 to 0.25mm from
www.austriamicrosystems.com Revision 1.00 14 - 15 AS1152 austria micro systems Data Sheet Board Layout Part Number Description Package Type Delivery Form AS1152 Quad low-voltage differential signaling driver 16-pin TSSOP Tube AS1152-T Quad low-voltage differential signaling driver 16-pin TSSOP Tape and Reel
www.austriamicrosystems.com Revision 1.00 15 - 15 AS1152 austria micro systems Data Sheet Board Layout Copyrights Copyright © 1997-2005, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami- crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com austria micro systems – a leap ahead in mixed signal