AS1150 AMSCO
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 15
Technical content
1 General Description
rates and reduced EMI emissions. media are PCB traces, backplanes, and cables. by separating the LVDS inputs and LVCMOS outputs. The devices are available in a 16-pin TSSOP package. Figure 1. Block Diagrams
2 Key Features
3 Applications
ble/battery-powered equipment.
4 Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings
5 Electrical Characteristics
- Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced
to ground except VTH, VTL, and VID.
- Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Table 2. DC Electrical Characteristics
- AC parameters are guaranteed by design and characterization.
- CL includes scope probe and test jig capacitance.
- tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
- tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other chan-
- tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions at the same VCC and within 5ºC of each other.
- tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated
- fMAX generator output conditions:
Table 3. AC Electrical Characteristics
6 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 15pF, TAMB = +25ºC, unless otherwise noted. Figure 2. Supply Current vs. Frequency Figure 3. Supply Current vs. Temperature Figure 6. Output Low Voltage vs. VCC Figure 7. Output High Voltage vs. VCC Diff. Threshold Voltage (mV) .
Figure 14. Transition Time vs. Temperature
7 Pinout
Figure 15. Pin Assignments (Top View) Table 4. Pin Descriptions Receiver Enable Input. Internally pulled down to GND. combinations of EN and ENn, the outputs are disabled and in high impedance.
10 OUT4 LVCMOS/LVTTL Receiver Output
11 OUT3 LVCMOS/LVTTL Receiver Output
12 GND Ground
13 V CC
14 OUT2 LVCMOS/LVTTL Receiver Output
15 OUT1 LVCMOS/LVTTL Receiver Output
Receiver Enable Input. Internally pulled down to GND. combinations of EN and ENn, the outputs are disabled and in high impedance.
15 OUT1
14 OUT2
13 VCC
12 GND
11 OUT3
10 OUT4
9 ENn
8 Detailed Description
power applications. Each independent channel accepts and converts an LVDS input to an LVTTL/LVCMOS output. The devices are capable of detecting differential signals from 100mV to 1V within an input voltage range of 0 to 2.4V. ences of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated. and EMI emissions, and less susceptibility to noise. The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground. other words, the transmission line is terminated on the IC. automatically sets the output high if any of these conditions are true. activating the failsafe circuit and thus forcing the device output high. Figure 16. Failsafe Input Circuit
9 Applications
Figure 17. Typical Application Circuit device as possible, with the smaller valued capacitor closest to pin VCC. Input trace characteristics can adversely affect the performance of the AS1150 and AS1151. must also be matched to this characteristic impedance. ! Eliminate reflections and ensure that noise couples as common mode by running differential traces close together. data recovery of the devices. ! Avoid 90° turns (use two 45° turns). ! Minimize the number of vias to further prevent impedance irregularities. Table 5. Function Table
Supported transmission media include printed circuit board traces, backplanes, and cables. field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. integrated resistor is specified in Table 2 on page 3. The device should be placed as close to the interface connector as possible to minimize LVDS trace length. ! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. ! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. ! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 18. Propagation Delay and Transition Time Test Circuit
- 50Ω required for pulse generator.
to account for internal termination resistor.
Figure 22. 16-Pin TSSOP Package
- All dimensions are in millimeters; angles in degrees.
- Dimensions and tolerancing per ASME Y14.5M-1994.
- Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
- Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm
- Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of
space between protrusion and adjacent lead is 0.07mm for 0.5mm pitch packages.
- Terminal numbers shown are for reference only.
- Datums A and B to be determined at datum plane H.
- Dimensions D and E1 to be determined at datum plane H.
- This dimension applies only to variations with an even number of leads per side. For variations with an odd number
of leads per package, the center lead must be coincident with the package centerline, datum A.
- Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip.
www.austriamicrosystems.com Revision 1.19 14 - 15 AS1150, AS1151 austria micro systems Data Sheet Board Layout Model Description Package Type Delivery Form AS1150 Quad low-voltage differential signaling receiver 16-pin TSSOP Tubes AS1150-T Quad low-voltage differential signaling receiver 16-pin TSSOP Tape and Reel AS1151 Quad low-voltage differential signaling receiver with integrated termination 16-pin TSSOP Tubes AS1151-T Quad low-voltage differential signaling receiver with integrated termination 16-pin TSSOP Tape and Reel
www.austriamicrosystems.com Revision 1.19 15 - 15 AS1150, AS1151 austria micro systems Data Sheet Board Layout Copyrights Copyright © 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami- crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com austria micro systems – a leap ahead