AN8150FB PANASONIC
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 19
Technical content
Datasheet sections
1Publication date: February 2008 SDJ00021AEB DATA SHEET AN8150FBPart No.
Octal, high precision 13-bit voltage output DAC Overview AN8150FB is IC which has octal 13 bit DACs constituted by Bi-CMOS process. Features yResolution: 13-bit yBuilt-in DAC: 8 DACs. yIntegral linearity error: ±2 LSB typ. yDifferential linearity error: ±0.5 LSB typ. ySupply voltage: +10.5 V (AVCC), –7.5 V (AVEE), +5 V (VDD) yOutput range: –3.3 V to +7.7 V yDAC input data: 13-bit parallel yDAC selection address data: 3-bit parallel yInput interface: TTL compatible Applications yIndustrial instrumentation Package y44 pin plastic quad flat package (QFP type) Type ySilicon monolithic bipolar IC
Block Diagram DAC LATCH A INPUT LATCH A INPUT LATCH B INPUT LATCH C INPUT LATCH D INPUT LATCH E INPUT LATCH F INPUT LATCH G INPUT LATCH H CONTROL LOGIC DAC LATCH B DAC LATCH C DAC LATCH D DAC LATCH E DAC LATCH F DAC LATCH G DAC LATCH H DAC A (DAC+BUF) DAC B (DAC+BUF) DAC C (DAC+BUF) DAC D (DAC+BUF) DAC E (DAC+BUF) DAC F (DAC+BUF) DAC G (DAC+BUF) DAC H (DAC+BUF) D0(LSB) D11 D10 D12(MSB) VRBCDEF VRMCDEF VRBGH VRMGH CS WR LD CLR VDD VSS VRBAB VRMAB AVEE AVCC AVEE AVCC VOUTA VOUTB AMPREFAB VOUTC VOUTD AMPREFCD VOUTE VOUTF AMPREFEF VOUTG VOUTH AMPREFGH Note) This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified.
Pin Descriptions Reference voltage (Bottom) for DAC G, HInputVRBGH31 Reference voltage (Midpoint) for DAC G, H InputVRMGH30 Analogue negative supply voltagePower supplyAVEE29 Digital input (MSB) InputD12(MSB)27 Digital inputInputD1126 Digital inputInputD1025 Digital inputInputD924 Output voltage of DAC HOutputVOUTH32 Asynchronous clear inputInputCLR28 Offset adjustment for DAC G, HInputAMPREFGH33 Digital inputInputD823 Output voltage of DAC GOutputVOUTG34 Digital inputInputD722 Digital inputInputD621 Write digital inputInputWR12 Chip selection digital inputInputCS11 Address 0 digital input (LSB)InputA010 Address 1 digital inputInputA19 Address 2 digital input (MSB)InputA28 Load inputInputLD7 Analogue negative supply voltagePower supplyAVEE6 Analogue positive supply voltagePower supplyAVCC5 Reference voltage (Midpoint) for DAC A, BInputVRMAB4 Reference voltage (Bottom) for DAC A, BInputVRBAB3 Output voltage of DAC AOutputVOUTA2 Offset adjustment for DAC A, BInputAMPREFAB1 Digital inputInputD318 Digital inputInputD217 Digital inputInputD116 Digital input (LSB)InputD0(LSB)15 Ground for digitalGNDVSS14 Digital positive supply voltagePower supplyVDD13 Digital inputInputD520 Digital inputInputD419 DescriptionTypePin namePin No.
Pin Descriptions (continued) Reference voltage (Midpoint) for DAC C, D, E, FInputVRMCDEF39 Analog positive supply voltagePower supplyAVCC38 Output voltage of DAC E OutputVOUTE37 Offset adjustment for DAC E, FInputAMPREFEF36 Output voltage of DAC F OutputVOUTF35 Output voltage of DAC B OutputVOUTB44 Output voltage of DAC D OutputVOUTD41 Reference voltage (Bottom) for DAC C, D, E, FInputVRBCDEF40 Offset adjustment for DAC C, DInputAMPREFCD42 Output voltage of DAC C OutputVOUTC43 DescriptionTypePin namePin No.
Absolute Maximum Ratings mA mA V *3°C–55 to +125TstgStorage temperature5 *3°C0 to +70ToprOperating ambient temperature4 *2mW359PDPower dissipation3 ⎯10IDD ⎯–50IEE ⎯mA50ICC Supply current2 7VDD V19.7AVCC –A VEE Supply voltage1 NoteUnitRatingSymbolParameterA No. Operating Supply Voltage Range ⎯+10.0 V to +11.0 VAV CC –7.7 V to –6.8 VAVEE Note V Unit 4.75 V to 5.25 V VDD Supply voltage range RangeSymbolParameter Note) The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at T a = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the • PD –T a diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the powe r dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C.
V/μs——3—SROutput voltage slew rate23 —LSB±4±2——ELLinearity error17 —Bits—13——ResResolution16 *1VVRM0——VRBReference voltage (bottom)15 *1V—2.2VRB—VRMReference voltage (midpoint)14 *1VAVEE + 3———VOMINMin. output voltage13 *1V——AVCC –2—VOMAXMax. output voltage12 —VVDD—0.7 × VDD —DIHHigh-level digital input voltage10 LSB±10±4——EGGain error21 LSB±8±4——EZSZero-scale error20 —LSB±8±4——EFSFull-scale error19 —LSB±1±0.5— —μA—–3–6 —μA1—–1 —mA383328 —EDDifferential linearity error VRMCDEF VRM = 2.2 V, VRB = 0 VIVRMHigh reference resistor current (2) —IILLow digital input current —ICCSupply current μs30———TSTSettling time24 LSB±8±4——EOFFOffset error22 VRBCDEF VRM = 2.2 V, VRB = 0 V VRMAB, VRMGH VRM = 2.2 V, VRB = 0 V —μA1—–1—IIHHigh digital input current 4 —μA—–1.5–3IVRMHigh reference resistor current (1)6 —μA–1 330–1 600–1 870VRBAB, VRBGH VRM = 2.2 V, VRB = 0 VIVRBLow reference resistor current (1)7 —μA– 2 660–3 200–3 740IVRBLow reference resistor current (2)9 —10.01—IDD3 —V0.3 × VDD —VSSDILLow-level digital input voltage11 Limits Typ Unit Max No teMin ConditionsSymbolParameterB No. Electrical Characteristics at AVCC = 10.5 V, AVEE = –7.5 V, VDD = 5 V Note) Ta = 25°C±2° unless otherwise specified. Note) *1: Sets so that the following conditions are satisfied. For details, refer to Technical Data. VOMAX = 5 × VRM – 2.5 × VRB – 1.5 × AMPREF < AVCC –2 V VOMIN = 2.5 × VRB – 1.5 × AMPREF > AVEE + 3 V
Technical Data 1. I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Analog negative supply voltage Apply –7.5 V normally.——–7.7 V to –6.8 V6, 29 Analog positive supply voltage Apply 10.5 V normally——+10.0 V to +11.0 V5, 38 DC = 2.2 V DC = 0 V DC = 2.2 V Waveform and voltage Offset adjustment pin of DAC A, B. Apply the same voltage as VRMAB normally.
10 MΩ or more1
80 Ω 2, 32, 34, 35, 37, 41, 43, 44 Reference voltage of DAC A, B (bottom). Apply 0 V normally. 1.38 kΩ or more3 Reference voltage of DAC A, B (midpoint) VRTAB. i.e., 2 × (VRMAB–VRBAB) is generated inside the IC. DAC A, B output amplitude = 2.5 × (VRTAB – VRBAB)10 MΩ or more4 Impedance DescriptionInternal circuitPin No. AVCC (Pin5, Pin38) AVEE (Pin6, Pin29) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) Pin 2, 32, 34, 35, 37, 41, 43, 44 7.7 V –3.3 V
Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Digital ground——0 V14 Digital positive supply voltage Apply 5 V normally.——+4.75 V to +5.25 V13 Write digital input Level trigger. The data is written to the input latch of DAC selected at A2, A1, A0 when this pin is low
10 MΩ or more12
Transfer the data of input latch to DAC latch at LD. Start DAC settling.
10 MΩ or more7
A2: MSB, A0: LSB
10 MΩ or more
Level trigger. DAC determined by A1, A2, and A0 is selected when this pin is low.
10 MΩ or more11
Impedance DescriptionInternal circuitPin No. VSS (Pin 14) VDD (Pin 13) VSS (Pin14) VDD (Pin13) VSS (Pin 14) VDD (Pin 13) VSS (Pin 14) VDD (Pin 13) Pin 8, 9, 10
Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Reference voltage of DAC G, H (bottom). Apply 0 V normally. 1.38 kΩDC = 0 V31 Reference voltage of DAC G, H (midpoint) VRTGH. i.e., 2 × (VRMGH – VRBGH) is generated inside the IC. DAC G, H output amplitude = 2.5 × (VRTGH – VRBGH)10 MΩ or moreDC = 2.2 V30 Waveform and voltage Digital input DB0: LSB, DB12: MSB 0 V is output during low. The previous value is hold as for latch.
10 MΩ or more28
Impedance DescriptionInternal circuitPin No. VSS (Pin 14) VDD (Pin 13) VSS (Pin 14) VDD (Pin 13) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) Pin 15 to 27 AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29)
Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Offset adjustment pin of DAC C, D. Apply the same voltage as VRMCD normally. 9k ΩDC = 2.2 V42 Reference voltage of DAC C, D, E, F (bottom). Apply 0 V normally. 0.69 kΩDC = 0 V40 DC = 2.2 V DC = 2.2 V DC = 2.2 V Waveform and voltage Offset adjustment pin of DAC G, H. Apply the same voltage as VRMGH normally. 9k Ω33 Offset adjustment pin of DAC E, F. Apply the same voltage as VRMEF normally. 9k Ω36 Reference voltage of DAC C, D, E, F (midpoint) VRTAB. i.e., 2 × (VRMCDEF – VRBCDEF) is generated inside the IC. DAC C, D, E, F output amplitude = 2.5 × (VRTCDEF – VRBCDEF)
10 MΩ or more39
Impedance DescriptionInternal circuitPin No. AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) AVEE (Pin 6, Pin 29)
Technical Data (continued) 2. Timing chart At operation of D/A converter At CLR operation A0, A1, A2 DATA VOUT CS WR LDAC CLR t12 t14t13 0 V Settling time of VOUT compared to CLR cancelμs30t14 Settling time of VOUT compared to CLRμs30t13 Min. pulse width of CLRns75t12 Settling time of VOUT compared to LDACμs30t11 Setup time of WR compared to LDACns100t10 Min. pulse width of LDACns75t9 Hold time of DATA compared to WRns15t8 Setup time of DATA compared to WRns15t7 Hold time of CS compared to WRns0t6 Setup time of CS compared to WRns0t5 Min. pulse width of WRns75t4 Pulse width of CSns75t3 Hold time of A0, A1, A2 compared to WRns25t2 Setup time of A0, A1, A2 compared to WRns25t1 DescriptionUnitRatingSymbol t10 t11 VOUT
Technical Data (continued) 3. Truth table DAC address DAC H input latch111 DAC G input latch011 DAC F input latch101 DAC E input latch001 DAC D input latch110 DAC C input latch010 DAC B input latch100 DAC A input latch000 機能A0A1A2 DAC operation T (0 V) T (0 V) x x x L L T DAC LATCH x x x x CS T (0 V)xx0 xx01 Lxx1 L1x1 T0x1 Lx11 L111 T001 INPUT LATCHWRLDCLR Note) T: through L: latch
Technical Data (continued) 4. DAC code table –3 V–3.3 V0 0000 0000 0000 –2.99878 V–3.29866 V0 0000 0000 0001 ::: 1.99878 V2.19866 V0 1111 1111 1111 2 V2.2 V1 0000 0000 0000 2.00122 V2.20134 V1 0000 0000 0001 ::: 6.99878 V7.69866 V1 1111 1111 1111 –3 V–3.3 VDACOUT (Min) 6.99878 V7.69866 VDACOUT (Max) 2 V2.2 VMidpoint electric potential
10 V[p-p]11 V[p-p]Output amplitude
0 V0 VVRB
2 V (VRT = 4 V)2.2 V (VRT = 4.4 V) *1VRM UnipolarBipolar Note) *1: VRT = 2 × VRM – VRB (generated inside) VDAC = (VRM–VRB) × 2 × D/8192+VRB (internal DAC output voltage) DACOUT = 2.5 × VDAC – 1.5 × AMPREF AMPREF = VRM DAC + DACOUT AMPREF 1.5R R VDAC Equivalent circuit of DAC output block amp. VRT VRB
Technical Data (continued) 5. P D ⎯ Ta diagram
- This IC is intended to be used for Industrial instrumentation. Consult our sales staff in advance for information on the following applications:
- Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body.
- Any applications other than the standard applications intended. 1) Space appliance (such as artificial satellite, and rocket) 2) Traffic control equipment (such as for automobile, airplane, train, and ship) 3) Medical equipment for life support 4) Submarine transponder 5) Control equipment for power plant 7) Weapon 8) Others: Applications of which reliability equivalent to 1) to 7) is required. 2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might smoke or ignite. 3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 4. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solder- bridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin CC short (Power supply fault), output pin – GND short (Ground fault), or output-to-output-pin short (load short). And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6. When using the LSI for new models, verify the safety including the long-term reliability for each product. 7. When the application system is designed by using this LSI, be sure to confirm notes in this book. Be sure to read the notes to descriptions and the usage notes in the book. 8. Power-on sequence Note that this IC may be latched up depending on the power-on sequence because it has positive/negative multi-power supplies. The recommended power-on sequence is described below. 1) DV DD 2) AVCC , VRT, VRB, AMPREF (No sequence limit) Note) The sequence of AVEE does not matter; that is, AVEE does not malfunction either before or after DVDD . 9. DV DD voltage supply range The conversion accuracy of this IC may deteriorates depending on the voltage of DVDD and VRM. Use the IC within the following range. 2 × VRM – VRB – DVDD ≤ 0.3 V 10.The conversion accuracy of this IC deteriorates depending on the voltage of VRM. Use the IC within the following range. VRB ≥ – 0.3 V Usage Notes
Usage Notes (continued) 11. Output voltage and load resistance This IC has been designed to drive an output load resistance of 50 Ω. When this IC is used with a resistance under 50 kΩ, the integral linearity error might be worse. In this case, raise the power supply voltage to prevent it. Determine the power supply voltage referring to the diagrams below. VEE –V OUTmin output load resistance characteristics Output load resistance (kΩ) VOUTmin –V EE (V) VCC –V OUTmax output load resistance characteristics Output load resistance (kΩ) VCC –V OUTmax (V)
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