AN8133FHP PANASONIC

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Technical content

A/D and D/A Converters Panasonic a AN8133FHP (Under development) High Speed Low Power Consumption Bi-CMOS 10-Bit A/D Converter @ Overview Unit: mam The AN8133FHP is a 10-bit A/D converter for image 36 25 processing which employs the Bi-CMOS process to real- ” HARRRARARABA ize the low power consumption. = us # * 10-bit resolution = =I + Maximum conversion rate : 40 MSPS (min.) = = + Low power consumption : 200 mW (typ.) “Noma + Operation on single power supply of 5 V BUBUUUUE LUGE « SH circuit not required 3 Z| + InpuvOutput form : TTL level compatible 3 S913] g é TT \\ rf

1 Application Field FTUUTTTT |

+ Digital video broadcasting such as D-STB roto? a + Image equipment such as HDTV Ga fotos 3 » OA equipment such as image scanner 3 + Medical equipment such as ultrasonic diagnosis device 48-pin QFP Package (QFHO48-P-0707) Note) Since the AN8133FHP is under development, the description here may be modified without any prior notice. When the final design is reviewed, refer to the up-to-date product standards. Block Diagram Analog Input INV O Vir O Ven O Upper Comparator with S/H > Vie O 3 vb $ mp) a ps Digital

5 Output

AN8133FHP : A/D and D/A Converters Hl Absolute Maximum Rating (Ta=25) Supply volags v “Analogue input volage v Digiulinpt voltage v Digital oupatcuteat 2 Reference voliage v Power dissipation [| moa) |W Operating ambient emperature [_t | ows SiC Storage emperuure v li Recommended Operating Conditions (Ta=25'°C) Parameter [swmbot_[ Condition] min | op | max | Unt Supply volage [ve | SS—~d as} sof 525] v [ve [dt ‘| asf — |v Reference voliage [ep as ‘Analogue input volage [ve | Vf — Pe] a v Peete sp v igi] ouput caren [t. [va=oav Sd | tf — | ma @ Electrical Characteristics (Voc=5V, Ta=25C) - [ee | vemaasy SSCS | | — | Reference resistive cuent [hs [ves=225v«Y| | 24] — | ma Input bas caren [ts [vw=3av | — | — | 80a ; [tw [vex=27v Sid | | — [na Crock input cument [me [vex=oev | | | — |p 7 [Vor flow=—400A «S| sf — | Pipi] ouput voltage [va [t=i6ma Sid | — | onl Linearity enor [ee [vm=2ver | | et] I Differential linearity enor es) Maximum conversion rate [Fe [Vw=2ver =i? S| — ‘| — | ses on [fau=40MHe, f=iMee | — | 38] — | a Quantization nose SN Fteax=40Mi, f=1sMHz | — | sof — | _«B Difference gn [pe | BesaniadisKe [os] tol Differential phase [pp | far ovate Nock | — | 0s] 10] © Input band [Bw | Vv=2ve.—3 —*(| so] — | — | Mie Digit ouput ay [se [tax=aomne | — | of — Tape capecitance [cu [nas — | of — or

A/D and D/A Converters AN8133FHP @ Pin Description Tate Symbol [_Finmane [Santa] Voge eve Descipon Setting INV pin to “L” level inverts all the data outputs (DO-D9) but not the overflow output.

42 Digital output invert pin TTL ‘This pin is set to “L” level with no connection

and operates a synchronously with clock. 2430 It is a power supply pin for digital circuit block. , . Connect tantalum capacitor of several uF and 3940 DvCC_| Digital power supply pin Sv ceramic capacitor of 0.1 uF as near as possible to " this pin between this pin and DGND. 21,23 Connect AGND and DGND with the possible 31,38 Digital ground lowest impedance at one point as near as possible 41,46 to the chip. ‘When overflow occurs, it becomes “H.” This pin 37 | OVE TIL is not affected by INV pin. 25 | Do — [Digital output (LSB) It is an output pin of TTL Level. In order to 26 | D1 [Digital output prevent the digital noise to entering the analogue 27 D2 _—_| Digital output circuit, suppress the ringing as far as possible. 28 | D3 _ | Digital output 29 | D4 [Digital output Refer to the TTL 32 | DS [Digital output timing chart.

33 D6 —_| Digital output

34 | D7 | Digital output

35 D8 —_| Digital output

36 D9 —_|Digital output (MSB)

36 Connect the AGND and DGND with the possible

8,10 lowest impedance at one point as near as the chip. 13,15] AGND |Analogue ground ov 18,45 It is used to set the reference voltage for comparator. Normally, Ver is given 4.25V and 11 | Ver [Reference voltage high 4.25V | Ves is given 2.25V. Connect tantalum capacitor 12 | Vers level, of several F and ceramic capacitor of 0.1 F in 14 | Vam [Reference voltage middle 3.25V | parallel between each pin and analogue ground. 16 | Vans point level, ‘Vim is provided for linearity compensation, which 17 | Ves [Reference voltage low 2.25V | gives middle point potential between Var and level Ves. However, it is normally opened. Vers and fra Veas are sense pin of Ver or Vrs respectively. 9 | Va [pesos pasn | ———_*( 22572250 [Wi tap pl A ei 12 tis a power supply pin for analogue circuit block. Connect tantalum capacitor of several HF and ce- TY? | AVEC |Analogue power supply 5.0V | ramic capacitor of 0.1 uF as near as possible to P this pin between this pin and AGND. Refer to the It is a clock for sampling. For their timing, refer 22 | CLK [Clock input timing chart. TTL to the timing chart. Pin No.4, 5, 20: NC

AN8133FHP A/D and D/A Converters W@ Output Code . Digital output sup wn =L 2.000VFS 1,953mV STEP M L M L OVP9876543210 OVP9876543210 000 4.250000 © — 0000000000 QO iit 001 4.248047 0 0000000001 O = 1111111110 Sil 3.251953 O Olliiiiiit @ 1000000000 512 3.250000 © 1000000000 O ONLI 513 3.248047 © 1000000001 O 111111110 1023 2.251953 O iit © 0000000000 1024 2.250000 pie besescccns 1 0000000000 Timing Chart N+3 N+2 N+i | : | N N+1 N+2 Clock input vontem [XX XS”