AN731

71128 VISHAY

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www.vishay.com FaxBack 408-970-5600 Document Number: 71128 28-Jan-00 /C0067/C0073/C0082/C0067/C0085/C0073/C0084 /C0065/C0078/C0065/C0076/C0089/C0083/C0073/C0083 In a closed-loop power supply, node A will servo to attain a voltage equal to VR . Node B will servo to attain a voltage equal to Vr2. Assuming an ideal op-amp and using Kirchkorf’s current law at node A and B, we have: (Vo Vr) R1 (Vr Vx) and (Vx Vr2) R3 (Vr2 Vc) (1) Let: M1 R2 and M2 R3 (2) Solve for VX, Vx (1 m1 )Vr m1Vo and Vx (1 m2 )Vr2 m2Vc (3) Equate the above two equations and solve for VO : Vo 1 m1 1/C0467Vr 1 m2 m1 /C0467Vr2 m2 m1 Vc b aVc (4) Where: a m2 and b 1 m1 1/C0467Vr 1 m2 m1 /C0467Vr2 (5) So, VO is a linear function with respect to VC . The function has slope a and y intercept b. A curve-fitting technique is used to force the equation (4) to follow the requirement. This is done in two steps: Matching the slope: a Vo2 Vo1 Vc2 Vc1 m2 m1 (6) Matching one point: Pick point B → VO2 = b + aVC2 b Vo2 aVc2 1 m1 1/C0467Vr 1 m1 a/C0467Vr2 (7) Equate (4) and (5) and solve for m1 m1 Vr Vr2 Vo2 a(Vr2 Vc2) Vr (8) Note: m1 R2 R1 (9) Since m1 is the ratio of 2 real resistors, it must be a positive number. Furthermore, m1 should not be too small or too large to have realistic resistor values for R1 and R2. There are two valid scenarios: 1. Vr – Vr2 > 0 and Vo2 + a(Vr2 – Vc2)–Vr > 0 or, 2. Vr – Vr2 < 0 and Vo2 + a(Vr2 – Vc2)–Vr < 0 Both of these present a restricted range of values for V r2 to give a meaningful value of m1. Once Vr2 is chosen correctly, m1 and the rest of the parameter values can be determined. /C0068/C0069/C0083/C0073/C0071/C0078 /C0080/C0082/C0079/C0067/C0069/C0068/C0085/C0082/C0069 /C0065/C0078/C0068 /C0069/C0088/C0065/C0077/C0080/C0076/C0069 Given: Vr = 1.3 V, R1 = 22.1 k. Also, 1 V < VX < 3 V. Calculate the slope, a: a Vo2 Vo1 Vc2 Vc1 3.4 0.4 2.7 0.2 1.2 (10) Determine Vr2: Choose a sensible value of Vr2 to satisfy either (1) or (2) above. Since it is easier to derive a value for Vr2 that is smaller than Vr (by using a simple resistor voltage divider), scenario (1) is used here. Vr–Vr2 0 Vr2 Vr 1.3 V and, Vo2 a(Vr2–Vc2)–Vr 0 Vr2 Vr–Vo2 a Vc2 1.3 V–3.4 V 1.2 2.7 0.95V (11)

Document Number: 71128 28-Jan-00 www.vishay.com FaxBack 408-970-5600 To limit the common mode range of VX, the following equations can be used: 1. To keep VX equal or greater than a minimum value, VXm = 1 V: Vr2 /C0119Vxm (Vo2–Vr–aVc2)/C0041aVc2Vr Vo2 /C0041a(Vr–Vxm )–Vr (12) 2. To keep VX equal or less than a maximum value, VXm = 3 V: Vr2 /C0119VxM (Vo2–Vr–aVc2)/C0041aVc1Vr Vo2 /C0041a(Vr–VxM–Vc2 /C0041Vc1)–Vr (13) So, Vr2 can be any value between 1.249 V and 1.3 V. Choose Vr2 = 1.25 V. Calculate m1 and then R2: m1 Vr–Vr2 Vo2 /C0041a(Vr2–Vc2)–Vr 1.3–1.25 m1 R2 R1 /C0229R2 m1R1 0.139/C003222.1 k 3.07 k (14) Choose R2 = 3.01 k as a practical value Calculate R3 and R4: a m2 m1 R3 m1R4 /C0229R3 am1R4 (15) Choose R4, then calculate R3. The value of R4 should be large enough such that the current going through it will not be so large as to cause excessive power dissipation under extreme conditions. On the other hand, R4 should be small enough that its current will not be overly sensitive to noise and op-amp bias current. If R4 is set at 22.1k, then R3 = 3.68 k, and we can choose R3 = 3.60 k as a practical value. Express V O as a function of VC , using practical values of R’s: a m2 m1 R1R3 R2R4 22.1kx3.68k 3.01kx22.1k 1.223 b /C04661 m1 /C00411/C0467Vr–/C04661 m1 /C0041a/C0467Vr2 /C0466R1 R2 /C00411/C0467Vr–/C0466R1 R2 /C0041a/C0467Vr2 b /C046622.1k 3.01k/C00411/C04671.3–/C046622.1k 3.01k/C00411.223/C04671.25 0.1389 (16) The final result: VO = aVC + b = 1.223 x VC + 0.1389 /C0069/C0088/C0080/C0069 /C0077/C0069/C0078/C0084/C0065/C0076 /C0069 /C0076/C0084 A circuit was built and tested (see Figure 5). The result is tabulated in Table 1 and plotted in Figure 4: /C0084/C0065/C0066/C0076/C0069 /C0049 V VX VO VC Measured Calculated Measured Required 0.1 1.43 0.26 0.32 2.8 0.99 3.56 3.58 3.0 0.96 3.81 3.78 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Control Voltage—VC (v) Output Voltage–VO (V) FIGURE 4. VX Measured VO The measured values are very much in agreement with the calculated and required values. A negligible error results from the difference between an ideal op-amp and the actual circuit with its finite offset voltage and bias current.

www.vishay.com FaxBack 408-970-5600 Document Number: 71128 28-Jan-00 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0069/C0083/C0080/C0079/C0078/C0083/C0069 /C0080/C0069/C0082/C0070/C0079/C0082/C0077/C0065/C0078/C0067/C0069 Figures 7 and 8 show the dynamic response of the output voltage with different dynamic control voltages. The VO response and settling time depend on the following factors: 1. the bandwidth of the converter control loop: the larger the bandwidth, the faster VO response time 2. the large signal response slew rate of the converter: the faster the slew rate, the faster the response 3. the slew rate of the converter control loop error amplifier 4. the bandwidth of the difference amplifier. The bandwidth of the converter control loop is the most important parameter. The maximum attainable bandwidth of a converter control loop is 1/(2*pi) times the switching frequency. For a converter switching at 100 kHz, the control bandwidth is limited to 16 kHz. Vishay Siliconix high-frequency switching regulators (including the Si9165, Si9169, and Si9170) offer switching frequencies up to 2 MHz and have a theoretical bandwidth limit of 318 kHz. Thus they would be good candidates for this kind of application. Figure 5 shows a complete example of a dc-to-dc converter using the Si9165 controller IC and the op-amp circuit. The output voltage can be programmed from 0.4 V to 3.4 V with a control voltage from 0.2 V to 2.7 V. Figure 6 shows a similar example using the Si9166 controller. The signal response slew rate of the converter dictates how fast the converter can slew its output voltage up or down given an infinitely large control loop bandwidth. The converter slew rate depends on the converter output averaging LC filter. The smaller the LC, the faster the slew rate. With respect to the slew rate of the converter control loop error amplifier, most of the converter control loop is figured as an integrator. The error amplifier often drives a fairly large integrator capacitor. The slew rate of the op-amp should be sized adequately. The bandwidth of the difference amplifier requires the difference amplifier to have its unity gain bandwidth a decade or more larger than the control loop bandwidth. /C0067/C0079/C0078/C0067/C0076/C0085/C0083/C0073/C0079/C0078 A simple op-amp circuit is used to program the output voltage of a typical dc-to-dc converter. The circuit offers flexible voltage scaling using a linear control voltage. The control voltage can be hard-wired for fixed-voltage operation. When used together with a wide bandwidth dc-to-dc converter, the circuit offers a simple solution for controlling the output voltage dynamically.

–SD to PGND for shutdown mode. PWM/–PSM to PGND for PSM mode. FIGURE 5. Schematic of Design Example, Using Si9165 Converter

3 Disable

FIGURE 6. Example Circuit Using Si9166 Controller PWM/–PSM to PGND for PSM mode. –SD to PGND for shutdown mode.