AN44071A-VF PANASONIC
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Receipt Date: / / Issuance Date: / / Panasonic Global Part Number Vendor Issue Number Orderer (Customer) Part Number "Changes in the description of Delivery Specifications" and "changes that affect performance, quality or environment" are implemented according to advance consultation. ORDERER (CUSTOMER)VENDOR Confirmation of Security Control We confirm and certify that the products of these specifications shall not be supplied so as to be used for Military Purpose (defined herein below). "Military Purpose" in this statement means the design, development, manufacture, storage or use of any weapons, including without limitation nuclear weapons, biological weapons, chemical weapons and missiles. DELIVERY SPECIFICATIONS Industrial Devices Company, Panasonic Corporation SMART Puniness distraction S423141-01#01 3.122012.
Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2)The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information de-scribed in this book. (3)The products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. Consult our sales staff in advance for information on the following applications: ・Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4)When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Other-wise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (5)Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (6)This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. Reprint from WARNING LABEL STANDARDS SC3-11-00007 This delivery specifications may include old company names such as “Matsushita Electronics Corporation” o r “Semiconductor Company, Matsushita Electric Industrial Co., Ltd .“”Semiconductor Company, Panasonic Corporation ” Please interpret these old company names as Industrial Devices Company, Panasonic Corporation” as of January 1, 2012.
AN44071APart No. Part No. Package Code No. Semiconductor Company, Panasonic Corporation Established by Applied by Checked by Prepared by Semiconductor Company Panasonic Corporation T.Yokouchi Regulations No. IC3F5544 J.KanedaM.Hiramatsu 2010-08-20
Semiconductor Company, Panasonic Corporation 2010-08-20
Contents
- Timing chart 9. About inputting the supply voltage to IF pins when VM power supply is not applied ……………………… 44
Semiconductor Company, Panasonic Corporation 2010-08-20 AN44071A Driver IC for Stepping Motor Overview AN44071A is a quad channel H-bridge driver IC. Two bipolar stepping motor can be controlled by a single driver IC. Interface control is 1CLK_type, it can be selected 2-phase excitation, half- step, 1-2 phase excitation, W1-2 phase excitation and 2W1-2 phase excitation. Features y2-channel stepping motor driver → A signal driver controls 2 stepping motors yBuilt-in decoder for micro steps (2-phase, half step, 1-2 phase, W1-2 phase and 2W1-2 phase excitation) → Stepping motor can be driven by only external clock signal. yPWM can be driven by built-in CR (3-value can be selected during PWM OFF period.) → The selection of PWM OFF period enables the best PWM drive. yMix Decay control (4-value can be selected for Fast Decay ratio) → Mix Decay control can improve accuracy of motor current waveform. yBuilt-in over-current protection (OCP) → If the current flows to motor output more than the setup value due to ground-fault etc., the OCP operates and all motor outputs are turned OFF. yBuilt-in under voltage lockout (UVLO) → If supply voltage falls to less than the operating supply voltage range, the UVLO operates and all motor outputs are turned OFF. yBuilt-in thermal protection (TSD) → If chip junction temperature rises and reaches to the setup temperature, all motor outputs are turned OFF. yBuilt-in abnormal detection output function → If OCP or TSD operates, an abnormal detection signal is output. yBuilt-in standby function → The operation of standby function can lower current consumption of this IC. yBuilt-in Home Position function → Home Position function can detect the position of motor. yBuilt-in step detection output function → If step detection output function detects clock input signal, it outputs a signal. yBuilt-in 5 V power supply (accuracy : ±5%) Applications yStepping motor drive Package y56 pin Plastic Small Outline Package With Heat Sink (SOP Type) Type yBi-CDMOS IC
Semiconductor Company, Panasonic Corporation 2010-08-20 DOUT2 AOUT1 0.01 μF ENABLEAB DECAY1AB DECAY2AB TjmonABCD CHARGE PUMP BC1 BC2 GND 0.01 μF VPUMP AOUT2 AOUT1 RCSA RCSB Gate Circuit Gate Circuit BOUT2 BOUT1 COUT2 COUT1 RCSC RCSD DOUT2 DOUT1 OCP VREFAB BLANK OSC CLKAB DIRAB ST2AB ST3AB ST1AB TEST TEST DACA DACB Micro Step Decoder PWMSWPWMSWAB R Q S R S Q ENABLECD DECAY1CD DECAY2CD VREFCD BLANK OSC CLKCD DIRCD ST2CD ST3CD ST1CD DACC DACDMicro Step Decoder PWMSWPWMSWCD R Q S R S Q 0.1 μF TSD 47 μF UVLO 0.1 μF S5VOUT BG VM AMP STBYSTBY STPHAB STPHCD VM2 VM1NFAULT 100 kΩ 10 kΩ 10 kΩ 10 kΩ S5VOUT Notes) y This application circuit is shown as an example but does not guarantee the design for mass production set. y VM1 and VM2 should be connected outside. Application Circuit Example
Semiconductor Company, Panasonic Corporation 2010-08-20 DOUT2 AOUT1 CHARGE PUMP Gate Circuit Gate Circuit OCP BLANK OSC TEST DACA DACB Micro Step Decoder R Q S R S Q BLANK OSC1/10 DACC DACDMicro Step Decoder R Q S R S Q TSD UVLO BG VM AMP STBY 100 kΩ S5VOUT PWMSW PWMSW ENABLEAB DECAY1AB DECAY2AB TjmonABCD BC1 BC2 GND VPUMP VREFAB CLKAB DIRAB ST2AB ST3AB ST1AB TEST PWMSWAB ENABLECD DECAY1CD DECAY2CD VREFCD CLKCD DIRCD ST2CD ST3CD ST1CD PWMSWCD S5VOUT STBY STPHAB STPHCD NFAULT AOUT2 AOUT1 RCSA RCSB BOUT2 BOUT1 COUT2 COUT1 RCSC RCSD DOUT2 DOUT1 VM2 VM1 Note) This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified. Block Diagram
Semiconductor Company, Panasonic Corporation 2010-08-20 Pin Descriptions Phase A/B Mix Decay setup 2InputDECAY2AB34 N.C.—N.C.32 Phase A motor drive output 1OutputAOUT133 N.C.—N.C.30 Phase A motor current detectionInput/OutputRCSA31 Phase A motor drive output 2OutputAOUT229 N.C.—N.C.27 Phase B motor drive output 1OutputBOUT128 N.C.—N.C.25 Phase B motor current detectionInput/OutputRCSB26 Phase B motor drive output 2OutputBOUT224 Phase A/B Mix Decay setup 1InputDECAY1AB23 Capacitor connection 1 for charge pumpOutputBC116 Capacitor connection 2 for charge pumpOutputBC217 Charge pump circuit outputOutputVPUMP18 N.C.—N.C.19 Phase A/B Home Position / Step detection signal outputOutputSTPHAB20 Phase A/B Torque reference voltage inputInputVREFAB21 Phase A/B PWM OFF period selection inputInputPWMSWAB22 GroundGroundGND14 Die pad ground 1—COM115 Internal reference voltage (output 5 V)OutputS5VOUT13 Test mode setupInputTEST12 Phase A/B, C/D VBE monitorOutputTjmonABCD10 Abnormal detection outputOutputNFAULT11 Phase C/D Torque reference voltage inputInputVREFCD8 Phase C/D Home Position / Step detection signal outputOutputSTPHCD9 Phase C/D Mix Decay setup 1InputDECAY1CD6 Phase C/D PWM OFF period selection inputInputPWMSWCD7 N.C.—N.C.4 Phase D motor drive output 2OutputDOUT25 Phase D motor current detectionInput/OutputRCSD3 N.C.—N.C.2 Phase D motor drive output 1OutputDOUT11 DescriptionTypePin namePin No.
Semiconductor Company, Panasonic Corporation 2010-08-20 Phase C/D excitation selection 2InputST2CD49 Phase C/D excitation selection 1InputST1CD50 N.C.—N.C.53 Phase C motor drive output 1OutputCOUT152 Phase C motor current detectionInput/OutputRCSC54 Phase C/D excitation selection 3InputST3CD48 Phase C/D Enable / disable CTLInputENABLECD45 StandbyInputSTBY44 Phase C/D clock inputInputCLKCD46 Power supply 1 for motorPower supplyVM143 Die pad ground 2—COM242 Phase A/B Enable / disable CTLInputENABLEAB40 Power supply 2 for motorPower supplyVM241 Phase C/D rotation direction setupInputDIRCD47 Phase A/B clock inputInputCLKAB39 Phase A/B excitation selection 1InputST1AB35 Phase A/B excitation selection 2InputST2AB36 Phase A/B excitation selection 3InputST3AB37 Phase A/B rotation direction setupInputDIRAB38 Phase C/D Mix Decay setup 2InputDECAY2CD51 N.C.—N.C.55 Phase C motor drive output 2OutputCOUT256 DescriptionTypePin namePin No. Pin Descriptions (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 *5A±1.7IOUT2Motor drive current 2 (Pin 1, 5, 52, 56)7 *5A±1.0If1Flywheel diode current 1(Pin 24, 28, 29, 33)8 *4V37VOUTOutput pin voltage (Pin 1, 5, 24, 28, 29, 33, 52, 56)5 *5A±1.0IOUT1Motor drive current 1 (Pin 24, 28, 29, 33)6 *3°C–55 to +150TstgStorage temperature4 NotesUnitRatingSymbolParameterA No. *5A±1.7If2Flywheel diode current 2 (Pin 1, 5, 52, 56)9 *3°C–20 to +85ToprOperating ambient temperature3 *2mW448PDPower dissipation2 *1V37VMSupply voltage (Pin 41, 43)1 Operating Supply Voltage Range Supply voltage range *1 NotesUnitRangeSymbolParameter V10.0 to 34.0VM Absolute Maximum Ratings Note) Absolute maximum ratings are limit values which do not result in damages to this IC, and IC operation is not guaranteed at these limit values. Note) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. Notes) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : The power dissipation shown is the value at T a =85°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the PD-Ta diagram of the package standard and design the heat radiation with sufficient margin so that the allowable value might not be exceeded based on the conditions of power supply voltage, load, and ambient temperature. *3 : Except for the power dissipation, operating ambient temp erature, and storage temperature, all ratings are for Ta =25°C. *4 :This is a rated value of output voltage, and do not apply input voltage from outside to these pins. Set not to exceed the allowable range at any time. *5 :Do not apply external current to any pin specially mentioned. For circuit currents, (+) denotes current flowing into the IC and (–) denotes current flowing out of the IC.
Semiconductor Company, Panasonic Corporation 2010-08-20 —V−0.3 to 6STBY44 —V−0.3 to 6ST2CD49 —V−0.3 to 6ST1CD50 —V2.5RCSC54 —V−0.3 to 6DIRAB38 —V−0.3 to 6ST2AB36 —V−0.3 to 6ST3AB37 —V−0.3 to 6ST1AB35 —V−0.3 to 6DECAY2AB34 —V2.5RCSB26 —V−0.3 to 6PWMSWAB22 —V−0.3 to 6DECAY1AB23 *2V(VM –1 ) t o4 3BC217 *2V(VM –2 )t o4 3VPUMP18 *1V−0.3 to 6STPHAB20 —V−0.3 to 6VREFAB21 —V2.5RCSD3 —V−0.3 to 6DECAY1CD6 —V−0.3 to 6PWMSWCD7 —V−0.3 to 6VREFCD8 *1V−0.3 to 6STPHCD9 *1V−0.3 to 6NFAULT11 —V−0.3 to 6TEST12 —V−0.3 to 6DECAY2CD51 —V−0.3 to 6CLKCD46 —V−0.3 to 6DIRCD47 —V−0.3 to 6ST3CD48 —V−0.3 to 6ENABLECD45 —V−0.3 to 6ENABLEAB40 —V−0.3 to 6CLKAB39 2.5RCSA NotesUnitRatingPin namePin No. —V31 *1mA2STPHAB20 —mA−7 to 0S5VOUT13 NotesUnitRatingPin namePin No. *1mA2NFAULT11 *1mA2STPHCD9 Allowable Current and Voltage Range Notes) y Allowable current and voltage ranges are limit ranges which do not result in damages to this IC, and IC operation is not guaranteed within these limit ranges. y Voltage values, unless otherwise specified, are with respect to GND. y Do not apply external currents or voltages to any pin not specifically mentioned. y For the circuit currents, "+" denotes current flowing into the IC, and "−" denotes current flowing out of the IC. Notes) *1 : This pin is connected to open drain circuit inside. Connect a resistor in series with power supply. Do not exceed the rated value at any time. Refer to page 4 for the recommended value. *2 : External voltage must not be applied to this pin. Do not exceed the rated value at any time.
Semiconductor Company, Panasonic Corporation 2010-08-20 *1μA——−10VM = 37 V, VRCS = 0 V, OUT = 0 V2IOUTOFF1Upper-side output OFF current7 Supply current I/O block —V5.5—2.1—1VSTBYHSTBY High-level input voltage11 —V0.6—0—1VSTBYLSTBY Low-level input voltage12 —μA1005025STBY = 5 V1ISTBYHSTBY High-level input current13 —μA2—−2STBY = 0 V1ISTBYLSTBY Low-level input current14 *2V5.5—2.1—1VCLKHCLK High-level input voltage15 *2V0.6—0—1VCLKLCLK Low-level input voltage16 *2μA1005025CLK = 5 V1ICLKHCLK High-level input current17 *2μA2—−2CLK = 0 V1ICLKLCLK Low-level input current18 *2kHz——50—1fCLKCLK maximum input frequency19 *3V5.5—2.1—1VENABLEHENABLE High-level input voltage20 *3V0.6—0—1VENABLELENABLE Low-level input voltage21 *3μA1005025ENABLE = 5 V1IENABLEHENABLE High-level input current22 *3μA2—−2ENABLE = 0 V1IENABLELENABLE Low-level input current23 —μA4022—STBY = Low1IMSTBYSupply current (STBY)10 ENABLEAB = ENABLECD = Low, STBY = High I = 0.8 A (Pin 1, 5, 52, 56) I = 0.8 A (Pin 1, 5, 52, 56) I = 0.5 A (Pin 24, 28, 29, 33) —V—VM –0 . 3 5 VM –0 . 5 5I = –0.8 A (Pin 1, 5, 52, 56)2VOH2Output saturation voltage 2 High3 —V0.970.64—2VOL2Output saturation voltage 2 Low4 —V1.510.5I = 0.5 A (Pin 24, 28, 29, 33)2VDI1Flywheel diode forward voltage 15 —V1.510.52VDI2Flywheel diode forward voltage 26 *1μA100——VM = 37 V, VRCS = 0 V, OUT = 37 V2IOUTOFF2Lower-side output OFF current8 Power block —V—VM –0 . 3 VM –0 . 5I = –0.5 A (Pin 24, 28, 29, 33)2VOH1Output saturation voltage 1 High1 —V0.750.48—2VOL1Output saturation voltage 1 Low2 —mA1910—1IMSupply current (Active)9 Limits Typ Unit Max Test circuits Notes Min ConditionsSymbolParameterB No. Notes) *1 : OUT represents AOUT1, AOUT2, BOUT1, BOUT2, COUT1, COUT2, DOUT1 and DOUT2. *2 : CLK represents CLKAB and CLKCD. *3 : ENABLE represents ENABLEAB and ENABLECD. Electrical Characteristics at VM =24.0 V Note) T a =25°C±2°C unless otherwise specified.
Semiconductor Company, Panasonic Corporation 2010-08-20 *4μs11.38.14.9PWMSW = Middle1TOFF3PWM OFF time 346 *4V1.7—1.3—1VPWMSWM PWMSW Middle-level input voltage25 *4V5.5—2.3—1VPWMSWHPWMSW High-level input voltage24 *4μA1508340PWMSW = 5 V1IPWMSWHPWMSW High-level input current27 *4V0.6—0—1VPWMSWLPWMSW Low-level input voltage26 *4μA–18–36–70PWMSW = 0 V1IPWMSWLPWMSW Low-level input current28 *4V1.71.51.3—1VPWMSWOPWMSW open voltage29 Torque control block —μA2—−2VREFAB = V REFCD = 5 V1IREFHInput bias current 142 —μA2—−2VREFAB = V REFCD = 0 V1IREFLInput bias current 243 *4μs39.22816.8PWMSW = Low1TOFF1PWM OFF time 144 *4μs21.315.29.1PWMSW = High1TOFF2PWM OFF time 245 —μs1.00.70.4VREFAB = V REFCD = 0 V1TBPulse blanking time47 —mV525500475VREFAB = V REFCD = 5 V1VTCMPComp threshold48 Reference voltage block —V5.255.04.75IS5VOUT = 0 mA1VS5VOUTReference voltage49 —Ω10——IS5VOUT = –7 mA1ZS5VOUTOutput impedance50 *5V5.5—2.1—1VDECAYHDECAY High-level input voltage30 *5V0.6—0—1VDECAYLDECAY Low-level input voltage31 *5μA1005025DECAY = 5 V1IDECAYHDECAY High-level input current32 *5μA2—−2DECAY = 0 V1IDECAYLDECAY Low-level input current33 *6V5.5—2.1—1VDIRHDIR High-level input voltage34 *6V0.6—0—1VDIRLDIR Low-level input voltage35 *6μA1005025DIR = 5 V1IDIRHDIR High-level input current36 *6μA2—−2DIR = 0 V1IDIRLDIR Low-level input current37 *7V5.5—2.1—1VSTHST High-level input voltage38 *7V0.6—0—1VSTLST Low-level input voltage39 *7μA1005025ST = 5 V1ISTHST High-level input current40 *7μA2—−2ST = 0 V1ISTLST Low-level input current41 I/O block (continued) Limits Typ Unit Max Test circuits Notes Min ConditionsSymbolParameterB No. Notes) *4 : PWMSW represents PWMSWAB and PWMSWCD. *5 : DECAY represents DECAY1AB, DECAY2AB, DECAY1CD and DECAY2CD. *6 : DIR represents DIRAB and DIRCD. *7 : ST represents ST1AB, ST2AB, ST3AB, ST1CD, ST2CD and ST3CD. Electrical Characteristics (continued) at VM =24.0 V Note) T a =25°C±2°C unless otherwise specified.
Semiconductor Company, Panasonic Corporation 2010-08-20 Test input block *8μA5 ——VSTPH = 5 V1ISTPH(leak)STPH pin output leak current *8V0.2——ISTPH = 1 mA1VSTPHL STPH pin output Low-level voltage Home Position/ STEP detection output block —μA1005025TEST = 5 V1ITESTHTEST High-level input current57 —V5.5—4.0—1VTESTHTEST High-level input voltage55 —V0.6—0—1VTESTLTEST Low-level input voltage56 —μA5 ——VNFAULT = 5 V1INFAULT(leak)NFAULT pin output leak current52 —μA2—−2TEST = 0 V1ITESTLTEST Low-level input current —V0.2——INFAULT = 1 mA1VNFAULTL NFAULT pin output Low-level voltage Abnormal detection output block Limits Typ Unit Max Test circuits Notes Min ConditionsSymbolParameterB No. Note) *8 : STPH represents STPHAB and STPHCD. Electrical Characteristics (continued) at VM =24.0 V Note) T a =25°C±2°C unless otherwise specified.
Semiconductor Company, Panasonic Corporation 2010-08-20 —V—8.5———VUVLO2Protection stop voltage —V—7.5———VUVLO1Protection start voltage Thermal shutdown protection operating temperature *9V/μs—−400— At the falling edge of output voltage, sink side of motor current —VT fOutput slew rate 2 *9V/μs—350— At the rising edge of output voltage, sink side of motor current —VTrOutput slew rate 1 Output block Thermal shutdown protection Under voltage lockout Reference values Typ Unit Max Test circuits Notes Min ConditionsSymbolParameterB No. Electrical Characteristics (Reference values for design) at VM =24.0 V Notes) T a =25°C±2°C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. Note) *9 : The characteristics of all outputs of AOUT1, AOUT2, BOUT1, BOUT2, COUT1, COUT2, DOUT1 and DOUT2 are shown.
Semiconductor Company, Panasonic Corporation 2010-08-20 DOUT1 RCSD DOUT2 PWMSWCD N.C. DECAY2CDDECAY1CD N.C. VPUMP BC2 BC1 COM1 S5VOUT N.C. BOUT2 RCSB BOUT1 AOUT2 RCSA AOUT1 STPHCD ST3CD ENABLECD DIRCD CLKCD N.C. COUT1 RCSC COUT2 ST2CD ST1CD STBY VREFCD COM2 VM2 N.C. STPHAB ST3AB ENABLEAB DIRAB CLKAB ST2AB ST1AB VREFAB PWMSWAB DECAY2ABDECAY1AB TjmonABCD TEST GND NFAULT VM1 N.C.N.C. N.C. N.C. VS5VOUT IS5VOUT V IST1CD VST1CD A IDECAY2CD VDECAY2CD A AIST2CD VST2CD AIST3CD VST3CD AIDIRCD VDIRCD AICLKCD VCLKCD AIENABLECD VENABLECD AISTBY VSTBY ICLKAB VCLKAB A IENABLEAB VENABLEAB A AIDIRAB VDIRAB AIST3AB VST3AB AIST2AB VST2AB AIST1AB VST1AB AIDECAY2AB VDECAY2AB A IDECAY1ABVDECAY1AB A IPWMSWABVPWMSWAB A IVREFABVVREFAB A IVREFCDVVREFCD A IPWMSWCDVPWMSWCD A IDECAY1CDVDECAY1CD A ITESTVTEST 0.01 μF AIVM1 24 V S13 VRCSD 1 kΩ 21 3 5.6 Ω 12 V 2175 Ω 12 V 75 Ω VDOUT1 V VDOUT2 V S10 5 V 2.5 kΩ 21 3 5 V A 5 V S11 2.5 kΩ 21 3 5 V A 12 V 75 Ω 12 V 75 Ω VBOUT2 V VBOUT1 V S14 VRCSB 1 kΩ 21 3 5.6 Ω 5 V S12 2.5 kΩ 21 3 5 V A 12 V 2 1 75 Ω 12 V 2 1 75 Ω VAOUT2 VAOUT1 V VRCSA 1 kΩ 2 13 5.6 Ω V 12 V 2 1 75 Ω 12 V 2 1 75 Ω VCOUT1 VCOUT2 V VRCSC 1 kΩ 2 13 5.6 Ω V S15S16 10 kΩ2 15 Ω 330 μH S20 S19 S18S17 VSTPHCD ISTPHCD V V VNFAULT INFAULT V V VSTPHAB ISTPHAB V V 10 kΩ2 15 Ω 330 μH 10 kΩ2 15 Ω 330 μH 10 kΩ2 15 Ω 330 μH 0.01 μF VVPUMP V 1. Test Circuit 1 Test Circuit Diagram
Semiconductor Company, Panasonic Corporation 2010-08-20 DOUT1 RCSD DOUT2 PWMSWCD N.C. DECAY2CDDECAY1CD N.C. VPUMP BC2 BC1 COM1 S5VOUT N.C. BOUT2 RCSB BOUT1 AOUT2 RCSA AOUT1 STPHCD ST3CD ENABLECD DIRCD CLKCD N.C. COUT1 RCSC COUT2 ST2CD ST1CD STBY VREFCD COM2 VM2 N.C. STPHAB ST3AB ENABLEAB DIRAB CLKAB ST2AB ST1AB VREFAB PWMSWAB DECAY2ABDECAY1AB TjmonABCD TEST GND NFAULT VM1 N.C.N.C. N.C. N.C. 0.6 V 2.1 V VCLKAB VENABLEAB VVREFAB VVREFCD VTEST 0.01 μF VM VSDOUT1 IDOUT1 ISDOUT1 A VDOUT1 V VSDOUT2 IDOUT2 ISDOUT2 A VDOUT2 V VSBOUT2 IBOUT2 ISBOUT2 A VBOUT2 V VSBOUT1 IBOUT1 ISBOUT1 A VBOUT1 V VSAOUT2 IAOUT2 ISAOUT2 2 1 A VAOUT2 V VSAOUT1IAOUT1 ISAOUT1 2 1 A VAOUT1 V VSCOUT1ICOUT1 ISCOUT1 2 1 A VCOUT1 V VSCOUT2ICOUT2 ISCOUT2 2 1 A VCOUT2 V 0.6 V 0.6 V 0.6 V 0.6 V VCLKCD 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V V ENABLECD S10 0.01 μF 2. Test Circuit 2 Test Circuit Diagram (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 29V Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z VVPUMP input—12ON19, 2055 S17 to S20 Hi-Z0V0V0V0V0VHi-Z0V2.1 V0V0V11ON17, 2229 input12ON29, 2056 S13 to S16 S10 to S12 0.6 V /2.1 V 50 kHz pulse ON2 33, 29, 28, 24, 52, 56, 1, 5 15, 16, Hi-Z5 V0.6 V0.6 V0.6 V 0.475 0.525 V 29, 24, 56, 5, 3, 26, 31, 54 40, 4520, 21 0 V 0 V 0 V 0 V 5 V 0.6 V 0.6 V VPWMSW Hi-Z0 V0 V0 V0 V0 V0 V2.1 V0 V0 VON18, 2143 Hi-Z5 V0 V0 V0 V0 V0 V2.1 V0 V0 VON18, 2142 Hi-Z5 V0 V0 V0 V0 V0 V0 V0 V0 VON14414 IS5VOUTVVREFVTEST VST1 VST2 VST3 VDIRVRCSVENABLEVSTBY VDECAY1 VDECAY2 VCLK to ON ON ON ON Hi-Z Hi-Z –7 mA Hi-Z Measuring pin C No. 5 V 5 V 5 V
5 V5 V5 V0 V5 V5 V5 V5 V
6, 7, 12, 22, 23, 34 to 40, 44 to 51 13, 17, 22, 27, 32, 36, 40, 57
0 V0 V0 V0 V0 V5 V0 V0 V
6, 7, 12, 22, 23, 34 to 40, 45 to 51 18, 23, 28, 33, 37, 41, 58 Notes) *1 : CLK represents CLKAB and CLKCD. *2 : DECAY1 represents DECAY1AB and DECAY1CD. DECAY2 represents DECAY2AB and DECAY2CD. *3 : ENABLE represents ENABLEAB and ENABLECD. *4 : PWMSW represents PWMSWAB and PWMSWCD. *5 : RCS represents RCSA, RCSB, RCSC and RCSD. *6 : DIR represents DIRAB and DIRCD. *7 : ST1 represents ST1AB and ST1CD. ST2 represents ST2AB and ST2CD. ST3 represents ST3AB and ST3CD. *8 : VREF represents VREFAB and VREFCD. Electrical Characteristics Test Procedures 1. Test Circuit 1
Semiconductor Company, Panasonic Corporation 2010-08-20 20) ENABLE High-level input voltage V ENABLEH 21) ENABLE Low-level input voltage V ENABLEL Sweep ENABLE voltage, and check that VAOUT1 and VCOUT1 switch as follows. VENABLE 0.6 V VAOUT1 /VCOUT1 2.1 V VENABLEHVENABLEL SPEC 24 V SPEC 0 V 48) Comp threshold VT CMP Measure the voltages of VAOUT2, VBOUT2, VCOUT2 and VDOUT2. when input voltage is set to 0.475 V and 0.525 V respectively. VRCSA / VRCSB /VRCSC /VRCSD VAOUT2 /VBOUT2 /VCOUT2 /VDOUT2 12 V 24 V 0 V (A) area (B) area (A) area : Always output Low-level (B) area : Output High-level as measurement value (Average) 50) Output impedance Z S5VOUT VS5OUT IS5VOUT 0 mA –7 mA VS5VOUT VA ZS5VOUT = 7m A VS5VOUT –V A 0.475 V 0.525 V SPEC SPEC Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 15) CLK High-level input voltage V CLKH 16) CLK Low-level input voltage V CLKL 19) CLK maximum input frequency f CLK Input the pulse of 50 kHz as CLK as follows. Low-level voltage = 0.6 V High-level voltage = 2.1 V When the frequency of V AOUT1, VCOUT1, VAOUT2, VCOUT2, VBOUT1, VDOUT1, VBOUT2 and VDOUT2 is 25 kHz, measure CLK High- level input voltage, CLK Low-level input voltage and CLK maximum input frequency. VCLKAB /VCLKCD VAOUT1 /VCOUT1 24 V 12 V 0 V 2.1 V 0.6 V 24 V 12 V 0 V VBOUT1 /VDOUT1 VAOUT2 /VCOUT2 24 V 12 V 0 V 24 V 12 V 0 V VBOUT2 /VDOUT2 50 kHz fAOUT1/fCOUT1 fAOUT2/fCOUT2 fBOUT1/fDOUT1 fBOUT2/fDOUT2 55) TEST High-level input voltage V TESTH 56) TEST Low-level input voltage V TESTL Check that the output status is as follows when Low-level input voltage (0.6 V) and High-level input voltage (4.0 V) are applied to TEST pin, Low-level / High-level input voltage to TEST pin. Table Output status at TEST Low / High-level input voltage 4.0 V 0.6 V TEST pin voltage conditions STPH pin = Home Position output (Refer to page 40 to 43 for details.)TEST High-level input voltage STPH pin = Step detection output (Refer to page 44 for details.) Status TEST Low-level input voltage Parameter Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 34) DIR High-level input voltage V DIRH 35) DIR Low-level input voltage V DIRL 38) ST1/ST2/ST3 High-level input voltage V STH 39) ST1/ST2/ST3 Low-level input voltage V STL Check the logic related to the operation of each excitation mode in page 35 to 38 under the conditions that the input voltage of DIR, ST1, ST2 and ST3 is set as follows. Confirm Low-level / High-level of DIR, ST1, ST2 and ST3 by checking the logic. Half step drive (8-step sequence) / Reverse0.6 V2.1 V0.6 V2.1 V W1-2 phase excitation drive (16-step sequence) / Reverse0.6 V2.1 V2.1 V2.1 V 1-2 phase excitation drive(8-step sequence) / Reverse0.6 V0.6 V2.1 V2.1 V 2.1 V 2.1 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V DIR 0.6 V 0.6 V 0.6 V 2.1 V 2.1 V 0.6 V 0.6 V ST1 2.1 V 0.6 V 2.1 V 2.1 V 0.6 V 2.1 V 0.6 V ST2 2.1 V 0.6 V 2.1 V 0.6 V 0.6 V 0.6 V 0.6 V ST3 2W1-2 phase excitation drive (32-step sequence) / Reverse 2-phase excitation drive (4-step sequence) / Reverse 2W1-2 phase excitation drive (32-step sequence) / Forward W1-2 phase excitation drive (16-step sequence) / Forward 1-2 phase excitation drive (8-step sequence) / Forward Half step drive (8-step sequence) / Forward 2-phase excitation drive (4-step sequence) / Forward Excitation mode 30 V Hi-Z 30 V VVPUMP Hi-ZPatternPatternPatternPatternPatternPatternPattern2.1 VPatternPattern—32OFF2 33, 29, 28, 24, 52, 56, 1, 5, 6, 23, 34, 51 30, S17 to S20 Hi-Z0.5 V0.6 V0.6 V0.6 V— 0.6 V 1.3 V 1.7 V 2.3 V 2.1 V2.1 V0.6 VPulse input31ON3 33, 29, 28, 24, 52, 56, 1, 5, 7, 22 24, 25, 26, 44, 45, 46, S13 to S16 S10 to S12 Hi-ZPatternPatternPatternPatternPatternPatternPattern2.1 VPatternPatternOFF2 33, 29, 28, 24, 52, 56, 1, 5, 35 to 38, 47 to 50 34, 35, 38, VPWMSW IS5VOUTVVREFVTEST VST1 VST2 VST3 VDIRVRCSVENABLEVSTBY VDECAY1 VDECAY2 VCLKS9 to Measure ment pin C No. Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 24) PWMSW High-level input voltage V PWMSWH 25) PWMSW Middle-level input voltage V PWMSWM 26) PWMSW Low-level input voltage V PWMSWL 44) PWM OFF time 1 T OFF1 45) PWM OFF time 2 T OFF2 46) PWM OFF time 3 T OFF3 47) Pulse blanking time T B Each parameter is obtained by the timing chart of VAOUT1, VBOUT1 , VCOUT1, VDOUT1, VAOUT2,VBOUT2, VCOUT2 and VDOUT2 at VREF = 0.5 V. The timing chart is shown as follows. x For 24) to 26), 44) to 47), measure T OFF1, TOFF2 and TOFF3 under the input conditions of PWMSW pin in the below chart. x For 47), measure the Low-level interval of VAOUT1, VBOUT1, VCOUT1 and VDOUT1 : TB in the below chart. Table PWMSW input voltage vs. T OFF TOFF3 = 8.1 μs1.3 V TOFF3 = 8.1 μs1.7 V VPWMSWH / VPWMSWM / VPWMSWL TOFF2 = 15.2 μs TOFF1 = 28 μs0.6 V PWMSW 2.3 V Status Voltage conditions Input pin t[μs] VAOUT1 /VBOUT1 24 V 0 V TOFF1 / TOFF2 / TOFF3 VCOUT1 /VDOUT1 VAOUT2 /VBOUT2 VCOUT2 /VDOUT2 t[μs] 24 V 0 V TB TB Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 30) DECAY High-level input voltage V DECAYH 31) DECAY Low-level input voltage V DECAYL Perform the logic test under the conditions that Low-level input voltage of DECAY1/DECAY2 is 0.6 V and High-level input voltage is 2.1 V. The timing chart of V AOUT1, VBOUT1 , VCOUT1, VDOUT1, VAOUT2, VBOUT2, VCOUT2 and VDOUT2 is as follows at the logic test. Measure TDECAY and TOFF-R, and check Low-level / High-level input voltage of DECAY1/DECAY2. t[μs] VAOUT1 /VBOUT1 VAOUT2 /VBOUT2 24 V 24 V 12 V 12 V 0 V 0 V TDECAY t[μs] TDECAY Table DECAY1/2 input voltage vs. Decay control 100% mode 50% mode 25% mode 0% mode (Slow Decay) Decay control (T DECAY / TOFF-R) 2.1 V0.6 V 0.6 V2.1 V 2.1 V DECAY2 0.6 V0.6 V 2.1 V DECAY1 VCOUT1 /VDOUT1 VCOUT2 /VDOUT2 TOFF-R Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 51) NFAULT pin output Low-level voltage V NFAULTL Input 1 mA to NFAULT pin under the condition that the output of NFAULT pin is Low, and measure the voltage of NFAULT pin. 52) NFAULT pin output leak current I NFAULT(leak) Input 5 V to NFAULT pin under the condition that the output of NFAULT pin is Hi-Z, measure the leak current. 53) STPH pin output Low-level voltage V STPHL Input 1 mA to STPH pin under the condition that the output of STPH pin is Low, measure the voltage of STPH pin. 54) STPH pin output leak current I STPH (leak) Input 5 V to STPH pin under the condition that the output of STPH pin is Hi-Z, measure the leak current. Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 1) Output saturation voltage 1 High V OH1 2) Output saturation voltage 1 Low V OL1 3) Output saturation voltage 2 High V OH2 4) Output saturation voltage 2 Low V OL2 2-phase excitation drive (4-step sequence) (ST1AB/ST1CD = Low, ST2AB/ST2CD = Low, ST3AB/ST3CD = Low), (DIRAB/DIRCD = Low) Measure the output saturation voltage High and the output saturation voltage Low under the below conditions. OFFOFFOFFOFFS10
6 V6 V6 V6 VVVREFAB /VVREFCD
24 V24 V24 V24 VVM
2.1 V 4 V ON ISAOUT2/ISBOUT2 = +0.5 A ISCOUT2/ISDOUT2 = +0.8 A VAOUT2/VBOUT2 VCOUT2/VDOUT2 AOUT2/BOUT2 COUT2/DOUT2 (d) BN o . 2 / N o . 4 2.1 V 4 V ON ISAOUT1/ISBOUT1 = +0.5 A ISCOUT1/ISDOUT1 = +0.8 A VAOUT1/VBOUT1 VCOUT1/VDOUT1 AOUT1/BOUT1 COUT1/DOUT1 (b) BN o . 2 / N o . 4 VAOUT2/VBOUT2 VCOUT2/VDOUT2 VAOUT1/VBOUT1 VCOUT1/VDOUT1 Measured voltage ONONS9
4 V4 VVTEST
ISAOUT2/ISBOUT2 = −0.5 A ISCOUT2/ISDOUT2 = −0.8 A ISAOUT1/ISBOUT1 = −0.5 A ISCOUT1/ISDOUT1 = −0.8 AApplied condition AOUT2/BOUT2 COUT2/DOUT2 AOUT1/BOUT1 COUT1/DOUT1Applied pin 2.1 V (a) BN o . 1 / N o . 3
2.1 VVENABLEAB
/VENABLECD (c) BN o . 1 / N o . 3 FWD (a) (b) (c)(d) 12341234 VAOUT1/ VCOUT1 VBOUT1/ VDOUT1 CLKAB/ CLKCD +100% –100% +100% –100% VBOUT2/ VDOUT2 +100% –100% VAOUT2/ VCOUT2 +100% –100% Electrical Characteristics Test Procedures (continued) 2. Test Circuit 2
Semiconductor Company, Panasonic Corporation 2010-08-20 5) Flywheel diode forward voltage 1 V DI1 6) Flywheel diode forward voltage 2 V DI2 Measure the Flywheel diode forward voltage 1 and the Flywheel diode forward voltage 2 under the below conditions. OFFOFFOFFOFFS10
0 V0 V0 V0 VVM
B No.6 (lower-side)B No.6 (upper-side)B No.5 (lower-side)B No.5 (upper-side)Measurement parameter 0.6 V ON ISCOUT1/ISDOUT1 = −0.8 A ISCOUT2/ISDOUT2 = −0.8 A VCOUT1/VDOUT1 VCOUT2/VDOUT2 COUT1/DOUT1 COUT2/DOUT2 0.6 V ON ISAOUT1/ISBOUT1 = −0.5 A ISAOUT2/ISBOUT2 = −0.5 A VAOUT1/VBOUT1 VAOUT2/VBOUT2 AOUT1/BOUT1 AOUT2/BOUT2 VCOUT1/VDOUT1 VCOUT2/VDOUT2 VAOUT1/VBOUT1 VAOUT2/VBOUT2 Measured voltage ONONS9 22S1 to S8 ISCOUT1/ISDOUT1 = +0.8 A ISCOUT2/ISDOUT2 = +0.8 A ISAOUT1/ISBOUT1 = +0.5 A ISAOUT2/ISBOUT2 = +0.5 AApplied condition COUT1/DOUT1 COUT2/DOUT2 AOUT1/BOUT1 AOUT2/BOUT2Applied pin 0.6 V 0.6 VVENABLEAB /VENABLECD 7) Upper-side output OFF current I OUTOFF1 Measure the output OFF current (IOUTOFF1) in each output pin under the below conditions. 8) Lower-side output OFF current I OUTOFF2 When the pattern is input to ENABLE pin as follows, and AOUT1, AOUT2, BOUT1, BOUT2, COUT1, COUT2, DOUT1 and DOUT2 output High, measure the output OFF current (IOUTOFF2) in each output pin. 5V5VVVREFAB /VVREFCD Pattern0.6 VVTEST ONOFFS10
37 V37 VVM
B No.8B No.7Measurement parameter Pattern OFF VSAOUT1 = VSBOUT1 = VSCOUT1 = VSDOUT1 = VSAOUT2 = VSBOUT2 = VSCOUT2 = VSDOUT2 =3 7V AOUT1/AOUT2 BOUT1/BOUT2 COUT1/COUT2 DOUT1/DOUT2 ONS9 1S1 to S8 VSAOUT1 = VSBOUT1 = VSCOUT1 = VSDOUT1 = VSAOUT2 = VSBOUT2 = VSCOUT2 = VSDOUT2 =0 V Applied conditions AOUT1/AOUT2 BOUT1/BOUT2 COUT1/COUT2 DOUT1/DOUT2 Applied pin Measurement current
0.6 VVENABLEAB
/VENABLECD Electrical Characteristics Test Procedures (continued) 2. Test Circuit 2 (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 Pin 1 : Phase D motor drive output 1 3 : Phase D motor current detection 5 : Phase D motor drive output 2 24 : Phase B motor drive output 2 26 : Phase B motor current detection 28 : Phase B motor drive output 1 29 : Phase A motor drive output 2 31 : Phase A motor current detection 33 : Phase A motor drive output 1 52 : Phase C motor drive output 1 54 : Phase C motor current detection 56 : Phase C motor drive output 2 Pin10 : VBE monitor——10 Impedance DescriptionInternal circuitWaveform and voltage Pin No. Pin 1 DOUT1
5 DOUT2
24 BOUT2
28 BOUT1
33 AOUT1
52 COUT1
56 COUT2
26 RCSB
31 RCSA
54 RCSC
Phase C/D 1.5k Pin 18 VPUMP Pin 10 TjmonABCD 800 800 Technical Data 1. I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Semiconductor Company, Panasonic Corporation 2010-08-20 Pin 17 : Capacitor connection 2 for charge pump 18 : Charge pump circuit output ——17 Pin 16 : Capacitor connection 1 for charge pump——16 Impedance DescriptionInternal circuitWaveform and voltage Pin No. 300k 125 VPUMPBC2 150 200 BC1 18 17 Technical Data (continued) 1. I/O block circuit diagrams and pi n function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Semiconductor Company, Panasonic Corporation 2010-08-20 Pin 44 : Standby100 kΩ—44 Pin 40, 45 : Enable / disable CTL Pin 39, 46 : Clock input Pin 37, 48 : Excitation selection 3 Pin 36, 49 : Excitation selection 2 Pin 35, 50 : Excitation selection 1 Pin 38, 47 : Rotation direction setup 100 kΩ— Impedance DescriptionInternal circuitWaveform and voltage Pin No. Pin 40 ENABLEAB, Pin 45 ENABLECD Pin 39 CLKAB, Pin 46 CLKCD Pin 37 ST3AB, Pin 48 ST3CD Pin 36 ST2AB, Pin 49 ST2CD Pin 35 ST1AB, Pin 50 ST1CD Pin 38 DIRAB, Pin 47 DIRCD STBY 68k 32k 100k 4kPin 152k Technical Data (continued) 1. I/O block circuit diagrams and pi n function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Semiconductor Company, Panasonic Corporation 2010-08-20 Pin 13 : Internal reference voltage (output 5 V)——13 Pin 21, 8 : Torque reference voltage input——8 Impedance DescriptionInternal circuitWaveform and voltage Pin No. Pin 21 VREFAB Pin 8 VREFCD 50k S5VOUT 50k 48k 100 Technical Data (continued) 1. I/O block circuit diagrams and pi n function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Semiconductor Company, Panasonic Corporation 2010-08-20 Pin 7, 22 : PWM OFF period setup——7 Pin 12 : Test mode setup100 kΩ—12 Impedance DescriptionInternal circuitWaveform and voltage Pin No. 60k 140kPin 7 PWMSWCD Pin 22 PWMSWAB 100k Pin 12 TEST Technical Data (continued) 1. I/O block circuit diagrams and pi n function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Semiconductor Company, Panasonic Corporation 2010-08-20 Pin 6, 23, 34, 51 : Mix DECAY setup100 kΩ— Pin 9, 20 : Home Position / Step detection signal output Pin 11 : Abnormal detection output Impedance DescriptionInternal circuitWaveform and voltage Pin No. Pin 6 DECAY1CD Pin 23 DECAY1AB Pin 34 DECAY2AB Pin 51 DECAY2CD 70k 30k 10k Pin 9 STPHCD Pin 11 NFAULT Pin 20 STPHAB Technical Data (continued) 1. I/O block circuit diagrams and pi n function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Semiconductor Company, Panasonic Corporation 2010-08-20 ———— Impedance DescriptionInternal circuitWaveform and voltage Pin No. S5VOUT (Pin13) VM(Pin41, Pin43) Diode Zener diode Ground Technical Data (continued) 1. I/O block circuit diagrams and pi n function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Semiconductor Company, Panasonic Corporation 2010-08-20 Phase B/D 90° delay to phase A/C Phase B/D 90° advance to phase A/C 1) Truth table (Excitation select) 2-phase excitation drive (4-step sequence)LowLowLowHighHigh Half step drive (8-step sequence)LowHighLowHighHigh 1-2 phase excitation drive (8-step sequence)LowLowHighHighHigh W1-2 phase excitation drive (16-step sequence)LowHighHighHighHigh 2W1-2 phase excitation drive (32-step sequence)High——HighHigh High High Low Low ST1* High Low High Low ST2* Output OFF——Low Half step drive (8-step sequence)LowLowHigh Low Low Low Low DIR* High High High High ENABLE* W1-2 phase excitation drive (16-step sequence)Low 2W1-2 phase excitation drive (32-step sequence)High 1-2 phase excitation drive (8-step sequence)Low Low ST3* 2-phase excitation drive (4-step sequence) Output excitation mode Technical Data (continued) 2. Control mode Note) * is AB or CD. 2) Truth table (Control / Charge pump circuit) OFF (*4)ONLowHigh (*3) High ENABLE* High (*3) Low STBY ONON All channel output : OFFOFF Output transistorControl / Charge pump circuit 4) Truth table (Decay selection) 50%LowHigh High High Low DECAY2* Slow DecayLow 25%Low High DECAY1* 100% Decay control (*6) 3) Truth table (PWM OFF period selection) 8.1 μsMiddle 15.2 μs 28.0 μs PWM OFF period (*5) Low High PWMSW* 5) Truth table (STPH output selection) Home Position output STEP detection output STPH* output Low High TEST Note) The above rate is applied to Fast Decay every PWM OFF period. 6) Truth table (NFAULT output) Hi-Z Low Low NFAULT ONOver-current detection stopThermal shutdown protection stop Over-current detection start OCP (*2) All channel output : OFFThermal shutdown protection start All channel output : OFF－ TSD (*1) Output transistor Notes) *1 : TSD is a latch type protection → The protection operation starts at 150°C. (All motor outputs are turned off , and latched.) / The latch is released by Standby or UVLO. *2 : OCP is a latch type protection → All motor outputs are turned off by over-current detection, and be latched. / The latch is released by Standby or UVLO. In addition, All motor outputs are turned off at under UVLO. *3 : Input external signals to STBY pin in order to set STBY signal to High-level. Because, STBY pin cannot be set to High-level when it is connected to S5VOUT(Pin13). *4 : The output transistors of AB/CD channel are controlled by ENABLEAB/CD respectively. *5 : The PWM OFF intervals of AB/CD channel are set by PWMSWAB/CD respectively. *6 : The Decay controls of AB/CD channel are set by DECAY1AB/CD ( DECAY2AB/CD) respectively.
Semiconductor Company, Panasonic Corporation 2010-08-20 Technical Data (continued) 3. Each phase current value 1) 1-2 phase, W1-2 phase, 2W1-2 phase DIRAB / DIRCD = Low Note) The definition of Phase A, B, C and D current "100%" : (VREFAB(VREFCD) ×0.1) / Motor current detection resistance –100029158 –98.1–19.528 –92.4–38.32714 –55.6–83.224 –38.3–92.42312 –19.5–98.122 0–10021116 19.5–98.120 –83.255.632 –92.438.33116 –98.119.530 –83.2–55.626 –70.7–70.725137 38.3–92.41910 55.6–83.218 70.7–70.71795 83.2–55.616 92.4–38.3158 98.1–19.514 10001374 98.119.512 92.438.3116 83.255.610 70.770.7953 55.683.28 38.392.474 19.598.16 0100532 –19.598.14 –38.392.432 –55.683.22 –70.770.7111 B/D phase current (%) A/C phase current (%) 2W1-2 phase (32-Step) W1-2 phase (16- Step) 1-2 phase (8-Step)
Semiconductor Company, Panasonic Corporation 2010-08-20 Technical Data (continued) 3. Each phase current value (continued) 2) 1-2 phase, W1-2 phase, 2W1-2 phase DIRAB / DIRCD = High Note) The definition of Phase A, B, C and D current "100%" : (VREFAB(VREFCD) ×0.1) / Motor current detection resistance 010029158 19.598.128 38.392.42714 83.255.624 92.438.32312 98.119.522 100021116 98.1–19.520 –55.683.232 –38.392.43116 –19.598.130 55.683.226 70.770.725137 92.4–38.31910 83.2–55.618 70.7–70.71795 55.6–83.216 38.3–92.4158 19.5–98.114 0–1001374 –19.5–98.112 –38.3–92.4116 –55.6–83.210 –70.7–70.7953 –83.2–55.68 –92.4–38.374 –98.1–19.56 –1000532 –98.119.54 –92.438.332 –83.255.62 –70.770.7111 B/D phase current (%) A/C phase current (%) 2W1-2 phase (32-Step) W1-2 phase (16-Step) 1-2 phase (8-Step)
Semiconductor Company, Panasonic Corporation 2010-08-20 Technical Data (continued) 4. Each phase current value (Timing chart) 1) 2-phase excitation drive (4-step sequence) (ST1AB/ST1CD = Low, ST2AB/ST2CD = Low, ST3AB/ST3CD = Low) 2) Half step drive (8-step sequence) (ST1AB/ST1CD = Low, ST2AB/ST2CD = High, ST3AB/ST3CD = Low) FWD (DIRAB/DIRCD = Low) REV (DIRAB/DIRCD = High) 12341234 IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD 123412341 123456781 123456781 +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD (DIRAB/DIRCD = Low) (DIRAB/DIRCD = High) IBOUT1/ IDOUT1 CLKAB/ CLKCD CLKAB/ CLKCD FWD REV IAOUT1/ ICOUT1 IAOUT1/ ICOUT1 IBOUT1/ IDOUT1
Semiconductor Company, Panasonic Corporation 2010-08-20 123456781 3) 1-2-phase excitation (8-step sequence) (ST1AB/ST1CD = High, ST2AB/ST2CD = Low, ST3AB/ST3CD = Low) 123456781 +100% –100% +100% –100% +100% –100% +100% –100% (DIRAB/DIRCD = Low) (DIRAB/DIRCD = High) IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD IAOUT1/ ICOUT1 CLKAB/ CLKCD FWD REV +70.7% –70.7% +70.7% –70.7% +70.7% –70.7% +70.7% –70.7% IBOUT1/ IDOUT1 2 2 Technical Data (continued) 4. Each phase current value (Timing chart) (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 4) W1-2-phase excitation (16-step sequence) (ST1AB/ST1CD = High, ST2AB/ST2CD = High, ST3AB/ST3CD = Low) 123456789 11 12 13 14 15 16 110 123456789 11 12 13 14 15 16 110 +100% +92.4% +70.7% –100% +38.3% IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD (DIRAB/DIRCD = Low) (DIRAB/DIRCD = High) FWD REV –38.3% –70.7% –92.4% +100% +92.4% +70.7% –100% +38.3% –38.3% –70.7% –92.4% +100% +92.4% +70.7% –100% +38.3% –38.3% –70.7% –92.4% +100% +92.4% +70.7% –100% +38.3% –38.3% –70.7% –92.4% Technical Data (continued) 4. Each phase current value (Timing chart) (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 5) 2W1-2-phase excitation (32-step sequence) (ST3AB/ST3CD = High) 1 2 3 4 5 6 7 8 9 1 11 21 31 41 51 61 710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 123456789 1 1 1 2 1 3 1 4 1 5 1 6 1 710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 (DIRAB/DIRCD = Low) (DIRAB/DIRCD = High) FWD REV IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD +100% +98.1% +92.4% +83.2% +70.7% +55.6% +38.3% +19.5% +0% –19.5% –38.3% –55.6% –70.7% –83.2% –92.4% –98.1% +100%/–100% +98.1% +92.4% +83.2% +70.7% +55.6% +38.3% +19.5% +0% –19.5% –38.3% –55.6% –70.7% –83.2% –92.4% –98.1% –100% +100% +98.1% +92.4% +83.2% +70.7% +55.6% +38.3% +19.5% +0% –19.5% –38.3% –55.6% –70.7% –83.2% –92.4% –98.1% +100%/–100% +98.1% +92.4% +83.2% +70.7% +55.6% +38.3% +19.5% +0% –19.5% –38.3% –55.6% –70.7% –83.2% –92.4% –98.1% –100% Technical Data (continued) 4. Each phase current value (Timing chart) (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 Technical Data (continued) 5. Timing chart when DIR switches (Example 1) Timing chart at 1-2-phase excitation (DIRAB/DIRCD : Low →High) CLKAB/ CLKCD IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 DIRAB/ DIRCD (Example 2) Timing chart at 1-2-phase excitation (DIRAB/DIRCD : High → Low) When DIRAB(DIRCD) switches, the state before switching is kept and operates continuously. State (DIRAB/DIRCD : Low) 5 6 7 6 5 4 3 State (DIRAB/DIRCD : High) 5 6 7 6 5 4 3 CLKAB/ CLKCD IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 DIRAB/ DIRCD When DIRAB(DIRCD) switches, the state before switching is kept and operates continuously.
Semiconductor Company, Panasonic Corporation 2010-08-20 y Home Position output timing chart (DIRAB / DIRCD = Low) CLKAB/ CLKCD IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 1 2 3 4 5 6 7 8 9 1 11 21 31 41 51 61 710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 STPHAB/ STPHCD This LSI has built-in Home Position function to reduce the displacement of motor current state at the change of excitation mode during motor drive. Low-level voltage is output to STPHAB pin and STPHCD pin at the timing when the displacement of motor current state doesn't occur at the change of excitation mode. The timing when Low-level voltage is output to STPHAB pin and STPHCD pin is as follows. The Home Position function becomes valid by setting TEST pin to High. Connect pull-up resistor to power supply (recommendation : S5VOUT), because STPHAB pin and STPHCD pin are composed by open drain circuit. The recommended value of pull-up resistor is 10 kΩ. Technical Data (continued) 6. Home Position function (TEST = High) +100% +98.1% +92.4% +83.2% +70.7% +55.6% +38.3% +19.5% +0% +100% +98.1% +92.4% +83.2% +70.7% +55.6% +38.3% +19.5% +0% –19.5% –38.3% –55.6% –70.7% –83.2% –92.4% –98.1% –100% 1) 2W1-2-phase excitation –19.5% –38.3% –55.6% –70.7% –83.2% –92.4% –98.1% –100%
Semiconductor Company, Panasonic Corporation 2010-08-20 Technical Data (continued) 6. Home Position function (TEST = High) (continued) y Home Position output timing chart (DIRAB / DIRCD = Low) (continued) IAOUT1/ ICOUT1 12 34 567 8 9 1 1 1 2 1 3 1 4 1 5 1 6 10 1 CLKAB/ CLKCD IBOUT1/ IDOUT1 STPHAB/ STPHCD +100% +92.4% +70.7% –100% +38.3% –38.3% –70.7% –92.4% +100% +92.4% +70.7% –100% +38.3% –38.3% –70.7% –92.4% 2) W1-2-phase excitation
Semiconductor Company, Panasonic Corporation 2010-08-20 1234 5 6 7 8 １ CLKAB/ CLKCD IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 STPHAB/ STPHCD +100% +70.7% –100% –70.7% +100% +70.7% –100% –70.7% 1234 5 6 7 8 １ CLKAB/ CLKCD IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 STPHAB/ STPHCD +100% –100% +100% –100% 3) 1-2-phase excitation 4) Half step Technical Data (continued) 6. Home Position function (TEST = High) (continued) y Home Position output timing chart (DIRAB / DIRCD = Low) (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 12 3 4 １ IAOUT1/ ICOUT1 IBOUT1/ IDOUT1 CLKAB/ CLKCD STPHAB/ STPHCD +100% –100% +100% –100% 5) 2-phase excitation Technical Data (continued) 6. Home Position function (TEST = High) (continued) y Home Position output timing chart (DIRAB / DIRCD = Low) (continued)
Semiconductor Company, Panasonic Corporation 2010-08-20 Table Step detection output pulse width About 20 μs 2-phase excitation About 10 μs W1-2-phase excitation About 5 μsAbout 20 μsPulse width (T1) 2W1-2-phase excitation Half step / 1-2 phase excitation CLK* (Clock input pin) Max. about 1 μs T1T1 T1 STPH* (Step detection output pin) （*: A B o r C D ) 8. Over-current protection function This IC has over-current protection (OCP) circuit to protect from the ground-fault etc. of the motor output. When motor current more than setting value flows to power MOS for about 3.8 μs (Typ.) due to the ground-fault, all motor outputs are turned OFF by latch operation. OCP is canceled by STBY = Low or UVLO (Under-voltage lockout) operation. However, the OCP circuit do not guaranteed the protection circuit of set. Therefore, do not use the OCP function of this IC to protect a set. Note that this IC might break before the protection function operates when it instantaneously exceeds the safe operation area and the maximum rating. When the inductor element is large due to the length of wiring at ground-fault, note that this IC might break. Because the motor output voltage falls on a negative voltage or excessively rises after motor current excessively flows to motor outputs. The setup current of the OCP (reference) is as follows. Technical Data (continued) 7. STEP detection output function (TEST = Low) Whenever edges signal is input into clock input pins, this IC outputs Low pulse signal from step detection output pins. The Low pulse width depend on each excitation mode. Refer to the below table. The STEP detection function becomes valid by setting TEST pin to Low. Connect pull-up resistor to supply voltage (Recommendation : S5VOUT), because STPHAB pin and STPHCD pin are composed by open drain circuit. The recommended value of pull-up resistor is 10 kΩ. Table Over-current protection setup current (Typ. value) 2.2 A A/Bch motor output
3.3 ASetup current
- About inputting the supply voltage to IF pins when VM power supply is not applied. This IC does the measures of error for inputting voltage to IF pins when VM power supply is not applied. IF pin : ENABLE*, DIR*, ST1*, ST2*, ST3*, CLK*, STBY, VREF* (* : AB or CD) Therefore, this IC doesn't break and it doesn't cause error operation by the input voltage to the IF pins when VM supply voltage is not supplied.
Semiconductor Company, Panasonic Corporation 2010-08-20 1. Special attention and precaution in using 1) This IC is intended to be used for gene ral electronic equipment [Stepping motor drive]. Consult our sales staff in advance for information on the following applications: x Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body. x Any applications other than the standard applications intended. (1) Space appliance (such as artificial satellite, and rocket) (2) Traffic control equipment (such as for automobile, airplane, train, and ship) (3) Medical equipment for life support (4) Submarine transponder (5) Control equipment for power plant (6) Disaster prevention and security device (7) Weapon (8) Others : Applications of which reliability equivalent to (1) to (7) is required It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the IC described in this book for any special application, unless our company agrees to your using the IC in this book for any special application. 2) Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might smoke or ignite. 3) Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 4) Perform a visual inspection on the PCB be fore applying power, otherwise damage might happen due to problems such as a solder- bridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5) Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin- V M short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short) . Especially, for the pins below, take notice Power supply fault, Ground fault, short to motor current detection pin, load short and short between the pin. x Motor drive output pin (Pin 1, 5, 24, 28, 29, 33, 52, 56) x Motor current detection pin (Pin 3, 26, 31, 54) x Charge pump circuit pin (Pin 16, 17, 18) x Power supply (Pin 41, 43) And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. 7) When using the LSI for new models, verify the safe ty including the long-term reliability for each product. 8) When the application system is designed by using this LSI, be sure to confirm notes in this book. Be sure to read the notes to descriptions and the usage notes in the book. 9) Connect the metallic plate (fin) on the back side of the IC with the GND potential. The thermal resistance and the electrical characteristics are guaranteed only when the metallic plate (fin) is connected with the GND potential. 10) Confirm characteristics fully when using the LSI. Secure adequate margin after considering variation of external part and this IC including not only static characteristics but transient characteristics. Especially, Pay attention that abnormal current or voltage must not be applied to external parts because the pins (Pin 1, 5, 16, 17, 18, 24, 28, 29, 33, 52, 56) output high current or voltage. Usage Notes
Semiconductor Company, Panasonic Corporation 2010-08-20 Usage Notes (continued) 2. Notes of Power LSI. 1) Design the heat radiation with sufficient margin so that Po wer dissipation must not be exceeded base on the conditions of power supply voltage, load and ambient temperature. (It is recommended to design to set connective parts to 70% to 80% of maximum rating) 2) The protection circuit is for maintaining safety against a bnormal operation. Therefore, the protection circuit should not work during normal operation. Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to VM short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be damaged before the thermal protection circuit could operate. 3) Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven. 4) The product which has specified ASO (Area of Safe Operation) should be operated in ASO. 5) Verify the risks which might be cause d by malfunctions of external parts. 6) Set capacitance value between VPUMP and GND so that VPUMP (Pin 18) must not exceed 43 V transiently at the time of motor standby to motor start. 7) This IC employs a PWM drive method that switches the high-current output of the output transistor. Therefore, the IC is apt to generate noise that may cause the IC to malfunction or have fatal damage. To prevent these problems, the power supply must be stable enough. Therefore, the capacitance between the S5VOUT and GND pins must be 0.1 μF and the one between the VM and GND pins must be a minimum of 47 μF and as close as possible to the IC so that PWM noise will not cause the IC to malfunction or have fatal damage.
Semiconductor Company, Panasonic Corporation 2010-08-20 Usage Notes (continued) 3. Notes of this IC 1) Pulse blanking time This IC has pulse blanking time (0.7 μs/Typ.value) to prevent erroneous current detection caused by noise. Therefore, the motor current value will not be less than current determined by pulse blanking time. Pay attention at the time of low current control. The relation between pulse blanking time and minimum current value is shown as Chart 1. In addition, increase-decrease of motor current value is determined by L value, wire wound resistance, induced voltage and PWM on Duty inside a motor. TB TPWM At normal operation In case of setting less than minimum current value Setup current value Setup current value Minimum current value TPWM : PWM OFF period TB : Pulse blanking time (Refer to ■ Electrical Characteristics B No.47) Chart 1. RCS current waveform 2) VREF voltage When VREF* voltage is set to Low-level, erroneous detection of current might be caused by noise because threshold of motor current detection comparator becomes low (= VREF/10 ×motor current ratio [%] (Refer to Page 33, 34). Use this IC after confirming no misdetection with setup VREF* voltage. If VREF* pin is open, input voltage might be irregular and rise, a large current might flow to the output. Therefore do not use on condition that VREF* pin is open. 3) Notes on interface Absolute maximum of Pin 6 to 8, Pin 12, Pin 21 to 23, Pin 34 to 40 and Pin 44 to 51 is –0.3 V to 6 V. When the setup current for a motor is large and lead line of GND is long, GND pin potential might rise. Take notice that interface pin potential is negative to difference in potential between GND pin reference and interface pin in spite of inputting 0 V to the interface pin. At that time, pay attention allowable voltage range must not be exceeded. 4) Notes on test mode When inputting voltage of above 0.6 V and below 4.0 V to TEST (Pin 12), this LSI might become test mode. When disturbance noise etc. makes this LSI test mode, motor might not operate normally. Therefore, use this LSI on condition that TEST pin is shorted to GND or S5VOUT at normal motor operation. （* : AB or CD)
Semiconductor Company, Panasonic Corporation 2010-08-20 Motor output Standby Standby All motor outputs OFF Start (At ENABLE = High) All motor outputs OFF (At ENABLE = Low) STBY About 100 μs(typ) Low High Motor output VM About 100 μs(typ) Low High All motor outputs OFF (UVLO) 【At Standby release】 【At under-voltage lockout release】 Standby release Ground fault detection Ground fault detection About 6.4 μs(typ) About 6.4 μs(typ) Usage Notes (continued) 3. Notes of this IC (continued) 5) Notes on Standby mode release / Under-voltage lockout release This LSI has all motor outputs OFF period of about 100 μs (typ) owing to release of Standby and UVLO (Refer to the below figure). This is why restart from Standby and UVLO after charge pump voltage rises sufficiently because charge pump operation stops at Standby and UVLO. When the charge pump voltage does not rise sufficiently during all motor outputs OFF period due to that capacitance between VPUMP and GND becomes large etc., the IC might overheat and it might not operate normally. In this case, release Standby and UVLO at ENABLE = Low-level, and restart at ENABLE = High-level after the charge pump voltage rises sufficiently. Moreover, take notice that state of motor current becomes default position at Standby and UVLO operation following as 3. Notes of this IC No.6. After all motor outputs OFF period, the ground-fault detection period is set to about 6.4 μs in order to detect the ground-fault of motor output before motor is turned on. All the upper side power MOS are turned on during the above ground fault detection period, and then whether the ground-fault occurs or not is checked. (Refer to the following contents.) If the ground-fault is detected at that time, all motor outputs are turned off, and motor drive stops. All motor outputs OFF Start (At ENABLE = High) All motor outputs OFF (At ENABLE = Low) All motor outputs OFF
Semiconductor Company, Panasonic Corporation 2010-08-20 Table Default position of each excitation mode Default electrical angle*Excitation mode –45°1-2 phase excitation (8-step) –45°W1-2 phase excitation (16-step) –45°2W1-2 phase excitation (32-step) –45°Half step (8-step) –45°2-phase excitation (4-step) AOUT1/COUT1 current BOUT1/DOUT1 current Default electrical angle : –45° DIR = "L" DIR = "H" 6) Default of motor current state The defaults of motor current state after the releases of UVLO and standby in each excitation mode are as follows. A BCD CLK* DIR*/ST1*/ ST2*/ST3* 10 μs or moreCLK* input minimum pulse width (High)A 10 μs or moreCLK* input minimum pulse width (Low)B DIR*/ST1*/ST2*/ST3* hold time DIR*/ST1*/ST2*/ST3* set time Contents TimePeriod 2 μs or moreD 2 μs or moreC *:A B o r C D Default position: 2-phase excitation / Half step Default position : 1-2 / W1-2 / 2W1-2 phase excitation Usage Notes (continued) 3. Notes of this IC (continued) 7) CLK* input signal and DIR* input signal The set/hold time of CLK* and DIR* input signals, CLK* input minimum pulse width (High/Low) are as follows. Input signals after securing set/hold time. Electrical angle : 0° *Definition of electric angle Electric angle is defined as 0°on the conditions of AOUT1/COUT1 current = 100% and BOUT1/DOUT1 current = 0%. It is defined at DIR = Low as "+" direction. It is defined at DIR = High as "–" direction.
Semiconductor Company, Panasonic Corporation 2010-08-20 CLKAB IAOUT Example) 1-2 phase excitation ENABLEAB IAOUT ENABLEAB CLKAB 7 8 1 2 1 2 3 4 5 6 3 4 5 6 7 8 1 2 3 4 5 6 6 7 8 1 2 High High High High Low Low Motor stop Motor stop Usage Notes (continued) 3. Notes of this IC (continued) 8) CLK input at ENABLE = Low As the below figure (Ex. 1-2 phase excitation), when inputting CLKAB at the time of motor stop and ENABLEAB = Low (all motor outputs OFF →Motor current = 0 A), the setup value of motor current will proceed at CLKAB input. Therefore, in case of restart at ENABLEAB = High, take notice that the position of restart is where the current state just before motor stop gains CLKAB input. For IBOUT, ICOUT and IDOUT, the operation is same as the below. In spite of stop at state[6] , because CLKAB is input at ENABLEAB = Low, the motor will restart after ENABLEAB = High at state [3]. In spite of stop at state [6] , because CLKAB is not input at ENABLEAB = Low, the motor will restart after ENABLE AB= High at state [6] just before stop.
Semiconductor Company, Panasonic Corporation 2010-08-20 Temp[°C] VBE[V] ΔVBE / Δtemp = –1.87 [mV / °C] 1500 TjmonABCD pin temperature characteristics 12) Power-on and Supply voltage change When supplying to VM pin (Pin 41, 43) or raising supply voltage, set the rise speed of VM voltage to less than 0.1 V/μs . If the rise speed of supply voltage is too rapid, it might cause error of operation and destruction of the IC. If the rise speed of VM voltage is more rapid than 0.1V/us, conduct a sufficient reliability test and also check a sufficient evaluation for a product. In addition, rise the VM supply voltage in an ENABLE = Low state when change VM supply voltage from low voltage to high voltage within the operating supply voltage range. Since there is not the all motor outputs OFF period shown in 3. Notes of this IC 5) (page 48) for the supply voltage change within the operating supply voltage range, the VPUMP voltage is in a low voltage state due to not following to VM supply voltage change enough, and this IC might not operate normally. Therefore, restart this IC by setting ENABLE to High after the VPUMP voltage rises enough. In addition, it is recommended to fall VM voltage in motor stop state (ENABLEAB/CD = Low or STBY = Low) for the stable fall of supply voltage. Supply voltage VM Time Rise at less than 0.1 V/μs 13) Pins to set mode x As for the High/Low setting of DECAY1AB, DECAY2AB, DECAY1CD, DECAY2CD, PWMSWAB and PWMSWCD, it is recommended to short to GND or S5VOUT. If the above pins are high-impedance such as open, note that this IC might not operate normally because it easily influences the noise x PWMSWAB/CD can be set to Middle by setting PWMSWAB/CD to Open. However, it might occur the error of operation due to the noise. In case, connect the capacity of 0.01 μF or more between PWMSWAB/CD and GND . Usage Notes (continued) 3. Notes of this IC (continued) 11) IC junction temperature In case of measuring chip temperature of this IC, measure the voltage of TjmonABCD pin (Pin 10) and estimate the chip temperature from the data below. However, because this data is technical reference data, conduct a sufficient reliability test of the IC and evaluate the product with the IC incorporated.
Semiconductor Company, Panasonic Corporation Package Code Regulations No. Revised Semiconductor Company Panasonic Corporation Package Standards Established by Applied by Checked by Prepared by HSOP056-P-0300B SC3S1959 61 M.ItohM.OkajimaH.YoshidaH.Shidooka Established: 2009-06-05 Revised : -
Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards Unit:mm Lead Finish Method : Pd Plating Lead Material : Cu Alloy Body Material : Epoxy Resin 1. Outline Drawing ゜ ゜ Established: 2009-06-05 Revised : -
Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 2. Package Structure (Technical Report : Reference Value) Method Material Method Material Method Material 23 1 6 45 7 Si Transfer molding Epoxy resin Wirebond Outer lead surface Au Cu alloy Pd plating Leadframe material Inner lead surface Chip Material Resin adhesive method Mass 250 mg Pd plating Adhesive material Thermo-compression bonding Molding Chip mount Established: 2009-06-05 Revised : -
Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 3. Mark Layout Product Name Date Code 1-pin direction Established: 2009-06-05 Revised : -
Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 4. Power Dissipation (Technical Report) 0.000 0.200 0.400 0.600 0.800 1.000 1.200 1.400 1.600 1.800 0 25 50 75 100 125 150 Ambient Temperature( o C ) Power Dissipation(Ｗ) Mount On PWB［GlassEpoxy:50X50X0.8t(mm)］ Rth(j-a) = 79.5 ºC/W Without PWB Rth(j-a) = 144.9 ºC/W 1.572 0.863 Established: 2009-06-05 Revised : -
Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 5. Power Dissipation (Supplementary Explanation) Package Semiconductor element Rth(j-c) Rth(c-a) Rth(j-a) Ta Tc Tj PWB [Definition of each temperature and thermal resistance] Ta ：Ambient air temperature ˞The temperature of the air is defined at the position where the convection, radiation, etc. don’t affect the temperature value, and it’s separated from the heating elements. Tc ：It’s the temperature near the center of a package surface. The package surface is defined at the opposite side if the PWB. Tj ：Semiconductor element surface temperature (Junction temperature.) Rth(j-c)：The thermal resistance (difference of temperature of per 1 Watts) between a semiconductor element junction part and the package surface Rth(c-a)：The thermal resistance (difference of temperature of per 1 Watts) between the package surface and the ambient air Rth(j-a)：The thermal resistance (difference of temperature of per 1 Watts) between a semiconductor element junction part and the ambient air [Supplementary information of PWB to be used for measurement] The supplement of PWB information for Power Dissipation data (Technical Report）are shown below. FR-44-layer4-layer FR-41-layerGlass-Epoxy Resin MaterialTotal LayerIndication [Notes about Power Dissipation（Thermal Resistance）] Power Dissipation values（Thermal Resistance）depend on the conditions of the surroundings, such as specification of PWB and a mounting condition , and a ambient temperature. (Power Dissipation (Thermal Resistance) is not a fixed value.) The Power Dissipation value（Technical Report）is the experiment result in specific conditions (evaluation environment of SEMI standard conformity) ,and keep in mind that Power Dissipation values (Thermal resistance) depend on circumference conditions and also change. [Experiment environment] Power Dissipation（Technical Report）is a result in the experiment environment of SEMI standard conformity. （Ambient air temperature (Ta) is 25 degrees C） [Definition formula] Rth(j-c) = Tj-Tc P Rth(c-a) = Tc-Ta P Rth(j-a) = Tj-Ta P (ˆ/W) (ˆ/W) (ˆ/W) Tj={Rth(j-c)+Rth(c-a)}ʷP+Ta =Rth(j-a)ʷP+Ta P:power(W)Fig1. Definition image = Rth(j-c)＋Rth(c-a) Established: 2009-06-05 Revised : -
In case that the semiconductor packages are mounted on the PCB, the soldering should be performed under the following conditions. ① Reflow soldering ＊Peak temperature : less than 260 ℃ ＊Temperature is measured at package surface point ② Wave soldering (Flow soldering) ＊Temp. of solder : 260 ℃ or less ＊Soak time : within 5 s ＊Number of flow : only 1 time ③ Manual soldering ＊Iron Temperature : 350 ℃ or less (Device lead temperature : 270 ℃､10 s max.) ＊Soldering time : within 3 s ＊Number of manual soldering : only 1 time No. value １．Recommended Soldering Conditions max. 260 ℃Reflow peak temp. : Industrial Devices Company, Panasonic Corporation 2012/3/6 Prepared Revised No． mark contents Recommended Soldering Conditions Total pages page 1T 1 Pre-heating temp. 150 ℃～180 ℃ 2 ｔ１ Pre-heating temp. hold time 60 s～120 s 3a Rising rate 2 ℃/s～5 ℃/s 4T p Peak temp. 255 ℃+5 ℃､-0 ℃ 5t p Peak temp. hold time 10 s±3 s b Down rate 2 ℃/s～5 ℃/s 6t w High temp. region hold time within 60 s (≧220 ℃) 11-155 Product name : Package : AN44071A-VF HSOP056-P-0300B 8- Number of reflow within 2 times 140 160 180 200 220 240 255 ℃ Time tw tp Tp 220 ℃ 260 ℃ a b 260
※ Because the taping and the magazine materials are not the heat-resistant materials, the bake at 125℃ cannot be done. Therefore, please solder everything or control everything in the rule time. Please keep them in an equal environment with the moisture-proof packaging or dry box. (Temperature: room temperature, relative humidity: 30% or less. ) To control storage time, when bake in the taping and the magazine is necessary, it is necessary for each type to set a bake condition. Please inquire of our company. ① Storage environment conditions: keep the following conditions Ta=5 ℃～30 ℃､RH=30 %～70 %. ② Storage period before opening dry pack shall be 1year from a shipping day under Ta=5 ℃～30 ℃､ RH=30 %～70 %. When the storage exceeds, Bake at 125 ℃ with 15 h to 25 h. ③ Baking cycle should be only one time. Please be cautious of solderability at baking. ④ In case that use reflow two times, 2nd reflow must be finished within 168 hours. ⑤ Remove flux sufficiently from product in the washing process. ( Flux : Chlorineless rosin flux is recommended.) ⑥ In case that use ultrasonic for product washing, There is the possibility that the resonance may occur due to the frequency and shape of PCB. It may be affected to the strength of lead. Please be cautious of this matter. No. Semiconductor Company, Panasonic Corporation 2012/3/6 Prepared Revised Recommended Soldering Conditions Total pages page ☆ AN44071A-VF limitation, low temperature bake condition ： 40 ℃ / 25 %RH or less / 192 h 11-155 2．Storage environment after dry pack opening Open dry pack Storage environment kept up to soldering (at 30 ℃/70 %RH max. , within 168h) Soldering Bake at 125 ℃ with 15 h to 25 h *Please refer to the following when doing at the low temperature bake. When the storage time exceeds 3．Note
Semiconductor Company, Panasonic Corporation 2009.10.07 Prepared Revised Recommended Land Pattern Total pages page
Semiconductor Company，Panasonic Corporation Prepared 2009.03.09 Specifications of packing by the embossment tape ( Specifications for dampproof packing of the reel without the inner carton) Total pages Packing Specification page AN12345A-NB 3000pcs. (3N)AN12345A-NB 1000 (3N)2 10N112200-NB 108010 AN12345A-NB AN12345A-NB 1.23-45 410N112300 2058 USP4B42516 AN12345A-NB 12345678 3000 23456789 3000 34567890 3000 45678901 3000 307 150000 Panasonic M MADE IN JAPAN Embossment carrier tape Top cover tape AN12345A-NB 90000pcs. (3N)AN12345A-NB 1000 (3N)2 10N112200-NB 108010 AN12345A-NB AN12345A-NB 1.23-45 410N112300 2058 USP4B42516 AN12345A-NB 12345678 3000 23456789 3000 34567890 3000 45678901 3000 307 150000 Panasonic M MADE IN JAPAN Corrugated cardboard for partition Outer box Laminated aluminum bag Inner frame C3 Label (Sampl)Reel Desiccant C3 Label (Sampl)
Semiconductor Company，Panasonic Corporation Prepared 2009.03.09 Total pages Packing Specification page Unit : mm Packing 1) Tape Reel V F Form IC quantity Contents Packing quantity 2) Reel 3) Packing case
3000 Pcs Reel × 1Pcs
Packing case 15000 Pcs Reel × ５Pcs 360 360 220 Draw out direction Emboss carrier tape 25.5 330
Packing Specification Total pages page 2009.03.09 Prepared Revised Semiconductor Company，Panasonic Corporation Unit : mm
Industrial Devices Company, Panasonic Corporation
1 Kotari-yakemachi, Nagaokakyo City, Kyoto 617-8520, Japan
Tel:075-951-8151
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