AN44067A-VF

AN44067A-VF PANASONIC

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Receipt Date: / / Issuance Date: / / Panasonic Global Part Number Vendor Issue Number Orderer (Customer) Part Number "Changes in the description of Delivery Specifications" and "changes that affect performance, quality or environment" are implemented according to advance consultation. ORDERER (CUSTOMER)VENDOR Confirmation of Security Control We confirm and certify that the products of these specifications shall not be supplied so as to be used for Military Purpose (defined herein below). "Military Purpose" in this statement means the design, development, manufacture, storage or use of any weapons, including without limitation nuclear weapons, biological weapons, chemical weapons and missiles. DELIVERY SPECIFICATIONS Industrial Devices Company, Panasonic Corporation SMART Puniness distraction S423140-10#01 3.122012.

Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2)The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information de-scribed in this book. (3)The products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. Consult our sales staff in advance for information on the following applications: ・Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4)When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Other-wise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (5)Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (6)This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. Reprint from WARNING LABEL STANDARDS SC3-11-00007 This delivery specifications may include old company names such as “Matsushita Electronics Corporation” o r “Semiconductor Company, Matsushita Electric Industrial Co., Ltd .“”Semiconductor Company, Panasonic Corporation ” Please interpret these old company names as Industrial Devices Company, Panasonic Corporation” as of January 1, 2012.

Regulations No.: Total Pages Page 145 AN44067APart No. Part No. Package Code No. Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Established by Applied by Checked by Prepared by Semiconductor Company Matsushita Electric Industrial Co., Ltd. 214406700108020 M.Hiramatsu H.Nobekawa T.Nagano 2008-02-20 IC3F5158

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700208020 2008-02-20

Contents

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700308020 2008-02-20 AN44067A Driver IC for Stepping Motor „ Overview AN44067A is s two channel H-bridge driver IC. Bipolar stepping motor can be controlled by a single driver IC. 2 phase excitation, half- step, 1-2 phase excitation, W1-2 phase excitation and 2W1-2 phase excitation can be selected. „ Features yBuilt-in decoder for micro steps (2 phase excitation, half-step, 1-2 phase excitation, W1-2 phase excitation and 2W1-2 phase excitation) Stepping motor can be driven by only external clock signal. y PMW can be driven by built-in CR (3-value can be selected during PWM OFF period.) Selection during PWM OFF period enables the best PWM drive. yMix Decay compatible (4-value for Fast Decay ratio can be selected.) Mix Decay control can improve accuracy of motor current wave form. yBuilt -in low voltage detection If supply voltage lowers less than the range of operating supply voltage, low voltage detection operates and all phases of motor drive output are turned OFF. yBuilt-in thermal protection If chip junction temperature rises and reaches setup temperature, all phases of motor drive output are turned OFF. y1 power supply with built-in 5 V power supply (accuracy ±5%) Motor can be driven by only 1 power supply because of built-in 5 V power supply. yBuilt-in standby function Operation of standby function can lower current consumption of IC. yBuilt-in Home Position function Home Position function can detect the position of a motor. „ Applications yIC for stepping motor drives „ Package y34 pin Plastic Small Outline Package With Heat Sink (SOP Type) „ Type yBi-CDMOS IC

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700408020 2008-02-20 „ Application Circuit Example Notes) y This application circuit is shown as an example but does not guarantee the design for mass production set. 0.01 μF 0.01 μF 0.1 μF 0.1 μF

15 VPUMP

6 BOUT2

8 BOUT1

12 AOUT1

10 AOUT2

R S Q 7 RCSB Gate Circuit

11 RCSA

17 VM1

47 μF PHA 28 DIR 32 ST2 30 ST3 29 R QS ST1 31 S5VOUT AMP STBY 22 DACB TEST 25

27 GND

4 GND

100 kΩ only TEST = High-level input DACA Micro Step Decoder

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700508020 2008-02-20 „ Block Diagram Note) This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified. R S Q 7 RCSB Gate Circuit R QS ST1 31 S5VOUT AMP STBY 22 DAC2 TEST 25

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700608020 2008-02-20 „ Pin Descriptions ——N.C.34 Step select 1InputST131 Step select 2InputST230 Step select 3InputST329 Internal reference voltage (output 5 V)OutputS5VOUT24 Torque reference voltage inputInputVREF23 StandbyInputSTBY22 Mix Decay setup 1InputDECAY121 Mix Decay setup 2InputDECAY220 Enable / disable CTL InputENABLE19 ——N.C.18 Motor power supply 1Power supplyVM117 PWM OFF period selection inputInputPWMSW33 Rotation directionInputDIR32 Clock input InputPHA28 Signal groundGroundGND27 Die pad groundGroundGND26 Test modeInputTEST25 ——N.C.16 Charge pump circuit outputOutputVPUMP15 Charge pump capacitor connection 2OutputBC214 Charge pump capacitor connection 1OutputBC113 Phase A motor drive output 1OutputAOUT112 Phase A current detectionInput / OutputRCSA11 Phase A motor drive output 2OutputAOUT210 Die pad groundGroundGND9 Phase B motor drive output 1OutputBOUT18 Phase B current detection Input / OutputRCSB7 Phase B motor drive output 2OutputBOUT26 ——N.C.5 groundGroundGND4 VBE monitor / Test output / Home Position outputOutputTJMON3 ——N.C.2 Motor power supply 2Power supplyVM21 DescriptionTypePin namePin No.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700708020 2008-02-20 „ Absolute Maximum Ratings *5, *6A±2.5IOUTMotor drive current (Pin 6, 8, 10, 12) 6 *4V37VOUTOutput pin voltage (Pin 6, 8, 10, 12)5 *2W0.466PDPower dissipation2 NotesUnitRatingSymbolParameterA No. *5, *6A2.5IfFlywheel diode current (Pin 6, 8, 10, 12)7 *3°C–55 to +150TstgStorage temperature4 *3°C–20 to +70ToprOperating ambient temperature3 *1V37VMSupply voltage (Pin 1, 17)1 Notes) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : The power dissipation shown is the value at T a = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the PD-Ta diagram of the package standard and design the heat radiation with sufficient margin so that the allowable value might not be exceeded based on the conditions of power supply voltage, load, and ambient temperature. *3 : Except for the power dissipation, operating ambient temp erature, and storage temperature, all ratings are for Ta = 25°C. *4 : This is output voltage rating and do not a pply input voltage from outside to these pins. Set not to exceed allowable range at any time. *5 : Do not apply external currents to any pin specially mentioned. For circuit currents, (+) denotes current flowing into the IC and (–) denotes current flowing out of the IC. *6 : Rating when cooling fin on the back side of the IC is connected to the GND pattern of the glass epoxy 4-layer board. (GND area : 2nd-layer or 3rd-layer : more than 1 500 mm2 ) In case of no cooling fin on the back side of the IC, rating current is 1.5 A on the glass epoxy 2-layer board. Note) Absolute maximum ratings are limit values which are not dest ructed, and are not the values to which operation is guaranteed. „ Operating supply voltage range Supply voltage range * NotesUnitRangeSymbolParameter V10.0 to 34.0VM Notes) * : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700808020 2008-02-20 —V2.5RCSB7 —V2.5RCSA11 *1V(VM –1 ) t o4 3BC214 *1V(VM –2 )t o4 3VPUMP15 —V–0.3 to 6ENABLE19 —V–0.3 to 6DECAY220 —V–0.3 to 6DECAY121 —V–0.3 to 6STBY22 —V–0.3 to 6VREF23 —V–0.3 to 6TEST25 —V–0.3 to 6PHA28 —V–0.3 to 6ST329 —V–0.3 to 6ST230 —V–0.3 to 6ST131 —V–0.3 to 6DIR32 —V–0.3 to 6PWMSW33 NotesUnitRatingPin namePin No. *2mA1TJMON3 —mA–7 to 0S5VOUT24 NotesUnitRatingPin namePin No. „ Allowable Current and Voltage Range Notes) y Voltage values, unless otherwise specified, are with respect to GND. y Do not apply external currents or voltages to any pin not specifically mentioned. y For the circuit currents, "+" denotes current flowing into the IC, and "−" denotes current flowing out of the IC. y Voltages and currents below show the limit value of nondestructive range which must not be exceeded in a moment. 注) *1 : These are pins not applied voltage from outside. Set so that the rating must not be exceeded transiently. *2 : In case of TEST = High-level input, TJMON voltage is only Low-level. (Detail : refer to Electrical Characteristics No.52 described in Page 10).

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406700908020 2008-02-20 —μA1508340PWMSW = 5 V1IPWMSWH High-level PWMSW input current23 —V0.6—0—1VPWMSWL Low-level PWMSW input voltage22 —mA105.5—ENABLE = High, STBY = High1IMSupply current (Active)5 —μA–18–36–70PWMSW = 0 V1IPWMSWL Low-level PWMSW input current24 —V1.7—1.3—1VPWMSWM Middle-level PWMSW input voltage21 —V5.5—2.3—1VPWMSWH High-level PWMSW input voltage20 —μA2—–2ENABLE = 0 V1IENABLEL Low-level ENABLE input current19 —μA1005025ENABLE = 5 V1IENABLEH High-level ENABLE input current18 —V0.6—0—1VENABLEL Low-level ENABLE input voltage17 —V5.5—2.1—1VENABLEH High-level ENABLE input voltage16 —kHz100———1fPHA Highest-level PHA input frequency15 —μA2—–2PHA = 0 V1IPHALLow-level PHA input current14 —V1.71.51.3—1VPWMSWOPWMSW voltage at open25 —μA1005025PHA = 5 V1IPHAHHigh-level PHA input current13 —V0.6—0—1VPHALLow-level PHA input voltage12 —V5.5—2.1—1VPHAHHigh-level PHA input voltage11 —μA2—–2STBY = 0 V1ISTBYLLow-level STBY input current10 —μA1005025STBY = 5 V1ISTBYHHigh-level STBY input current9 —V0.6—0—1VSTBYLLow-level STBY input voltage8 —V5.5—2.1—1VSTBYHHigh-level STBY input voltage7 I/O Block VM = 37 V, VRCS = 0 V I = 1.2 A —V1.51.00.5I = 1.2 A2VDIFlywheel diode forward voltage3 —μA2010—2ILEAKOutput leakage current 4 —μA5025—STBY = Low1IMSTBYSupply current (STBY)6 Output Drivers —V—VM –0 . 4 2 VM –0 . 7 5I = –1.2 A2VOH High-level output saturation voltage1 —V0.8250.54—2VOL Low-level output saturation voltage2 Limits Typ Unit Max Test circuits Notes Min ConditionsSymbolParameterB No. „ Electrical Characteristics at VM = 24.0 V Note) T a = 25°C±2°C unless otherwise specified.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701008020 2008-02-20 Reference Voltage Block —mV525500475VREF = 5 V1VTCMPComp threshold49 —μs1.00.70.4VREF = 0 V1TBPulse blanking time48 —μs11.38.14.9PWMSW = High1TOFF3PWM OFF time 347 —μs21.315.29.1PWMSW = Middle1TOFF2PWM OFF time 246 —V5.255.04.75IS5VOUT = 0 mA1VS5VOUTReference voltage50 —μs39.22816.8PWMSW = Low1TOFF1PWM OFF time 145 —μA2—–2VREF = 0 V1IREFLInput bias current 244 —μA5—–15VREF = 5 V1IREFHInput bias current 143 —V0.30.1—Pull up TJMON pin to 5 V with 100 kΩ.1VTJL At TEST High-level input TJMON output Low-level voltage Home Position Block —Ω10——I S5VOUT = –7 mA1ZS5VOUTOutput impedance51 Torque Control Block —μA2—–2TEST = 0 V1ITESTLLow-level TEST input current42 —μA1005025TEST = 5 V1ITESTHHigh-level TEST input current41 —V0.6—0—1VTESTLLow-level Test input voltage40 —V2.7—2.3—1VTESTMMiddle-level TEST input voltage39 —V5.5—4.0—1VTESTHHigh-level TEST input voltage38 —μA5 ——VTJMON = 5 V1ITJ(leak) At TEST High-level input TJMON output leakage current53 —μA2—–2ST1 = ST2 = ST3 = 0 V1ISTLLow-level ST input current37 —μA1005025ST1 = ST2 = ST3 = 5 V1ISTHHigh-level ST input current36 —V0.6—0—1VSTLLow-level ST input voltage35 —V5.5—2.1—1VSTHHigh-level ST input voltage34 —μA2—–2DIR = 0 V1IDIRLLow-level DIR input current33 —μA1005025DIR = 5 V1IDIRHHigh-level DIR input current32 —V0.6—0—1VDIRLLow-level DIR input voltage31 DECAY1 = DECAY2 = 0 V —μA1005025DECAY1 = DECAY2 = 5 V1IDECAYH High-level DECAY input current28 —μA2—–21IDECAYL Low-level DECAY input current29 —V5.5—2.1—1VDIRHHigh-level DIR input voltage30 —V5.5—2.1—1VDECAYH High-level DECAY input voltage26 —V0.6—01VDECAYL Low-level DECAY input voltage27 Limits Typ Unit Max Test circuits Notes Min ConditionsSymbolParameterB No. „ Electrical Characteristics (continued) at VM = 24.0 V Note) T a = 25°C±2°C unless otherwise specified.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701108020 2008-02-20 „ Electrical Characteristics (Reference values for design) at VM = 24 V Notes) T a = 25°C±2°C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. Low voltage Protection —V—8.7———VUVLO2Protection releasing voltage60 Output voltage fall Thermal Protection Thermal protection operating temperature57 —°C—40——ΔTSDThermal protection hysteresis width58 Output Drivers —V/μs—220—Output voltage rise—VTrOutput slew rate 154 —V/μs—200——VTfOutput slew rate 255 —V—7.9——VUVLO1Protection operating voltage59 Reference values Typ Unit Max Test circuits Notes Min ConditionsSymbolParameterB No.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701208020 2008-02-20 1. Test Circuit 1 „ Test Circuit Diagram

31 ST1

25 TEST

34 N.C. RCSB 7 BOUT2 6 N.C. 2 VM2 1 GND 4 GND 9 RCSA 11

26 GND

22 STBY

28 PHA

23 VREF

30 ST2

18 N.C.

32 DIR

24 S5VOUT

33 PWMSW

N.C. 16 19 ENABLE TJMON 3 N.C. 5

20 DECAY2

21 DECAY1

29 ST3

V IVM VM = 24 V A 0.01 μF ISTBY VSTBY AA IPWMSW VPWMSW A VS5OUT IS5VOUT V VREF IREF A VST2IST2 AAIST1 VST1 AIDIR VDIR 0.01 μF VRCSB VST3IST3 A IDECAY2 VDECAY2 A IDECAY1 VDECAY1 A ITEST VTEST A 5 V S6100 kΩ 1 kΩ S82 1 3 5 V A ITJMON 12 V 75 Ω S1 S2 S3 S4 VAOUT1 V 12 V 75 Ω VAOUT2 V 12 V 75 Ω VBOUT1 V 12 V 75 Ω VBOUT2 V 10kΩ 10kΩ 21 3 5.6 Ω VRCSA 1 kΩ 21 3 5.6 Ω

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701308020 2008-02-20 2. Test Circuit 2 „ Test Circuit Diagram 34 N.C. RCSB 7 BOUT2 6 N.C. 2 VM2 1 GND 4 GND 9 RCSA 11 18 N.C. N.C. 16 19 ENABLE TJMON 3 N.C. 5 V VSAOUT1 IAOUT1 A VAOUT1V VSBOUT2 IBOUT2 ISBOUT2 A VBOUT2 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V 2.1 V 0.6 V 21 21 ISAOUT1 VENABLE 0.01 μF0.01 μF VSBOUT1 IBOUT1 ISBOUT1 A VBOUT1 V

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701408020 2008-02-20 1. Test Circuit 1 OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Hi-Z0 V0 V0 V0 V0 VHi-Z0 V2.1 V0 V0 V11ON13325 Hi-Z5 V 0.6 V, 2.3 V, 2.7 V, 4.0 V 0.6 V0.6 V0 V0.6 V0.6 V5 V VDECAY1 = 0.6 V VDECAY2 = 2.1 V

2.1 V11 or 2ON23, 6, 8,

10, 12, 25 38, 39, S7, 0.6 V το 2.1 V 200 kHz pulse ON26, 8, 10, 12, 28 11, 12,15 Hi-Z5 V0 V0.6 V0.6 V0.475 V, 0.525 V0 V0.6 V2.1 V0 V5 VOFF36, 7, 8, 10, 11, 1249 Hi-Z5 V0 V0.6 V0.6 V0 V0 V2.1 V2.1 V0 V0 VON26, 8, 10, 12, 1916 0 V 0 V 0 V 0 V 0 V 5 V 5.5 V 5.5 V VPWMSW Hi-Z5 V0 V0.6 V0.6 V0 V0.6 V2.1 V0 V0 VON26, 8, 10, 12, 1917 Hi-Z0 V0 V0 V0 V0 V0 V2.1 V0 V0 VON12344 Hi-Z5 V0 V0 V0 V0 V0 V2.1 V0 V0 VON12343 Hi-Z5 V0 V0 V0 V0 V0 V0 V0 V0 VON32210 IS5VOUTVREFVTEST VST1 VST2 VST3 VDIR VRCSA VRCSB VENABLEVSTBY VDECAY1 VDECAY2 VPHAS5 to ON ON ON ON Hi-Z Hi-Z –7 mA Hi-Z Measuring pin C No. 5 V 5 V 5 V

5 V5 V5 V0 V5 V5 V5 V5 V

19 to 22, 25, 28 to 33 13, 18, 23, 28, 32, 36,

0 V0 V0 V0 V0 V5 V0 V0 V

19 to 21, 25, 28 to 33 14, 19, 24, 29, 33, 37, „ Electrical Characteristics Test Procedures

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701508020 2008-02-20 16) ENABLE High-level input voltage V ENABLEH 17) ENABLE Low-level input voltage V ENABLEL VENABLE 0.6 V VAOUT1 /VBOUT1 2.1 V VENABLEHVENABLEL 12 V SPEC 24 V SPEC 0 V Region (A) Region (B) 49) Comp threshold VT CMP VRCSA / VRCSB VAOUT2 /VBOUT2 12 V 24 V 0 V Region (A) Region (B) Check the conditions by measuring VAOUT2 and VBOUT2 voltage with the input voltage set to 0.475 V and 0.525 V respectively. Region (A) : Always output Low-level Region (B) : Output Low-level with minimum duty 51) Output impedance Z S5VOUT VS5OUT IS5VOUT 0 mA –7 mA VS5VOUT VA ZS5VOUT = 7m A VS5VOUT –V A VENABLE 0.6 V VAOUT2 /VBOUT2 2.1 V VENABLEHVENABLEL 12 V SPEC 24 V SPEC 0 V Region (A) Region (B) 0.475 V 0.525 V SPEC SPEC „ Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701608020 2008-02-20 11) PHA High-level input voltage V PHAH 12) PHA Low-level input voltage V PHAL 15) PHA Highest input frequency f PHA VPHA VAOUT1 24 V 12 V 0 V 2.1 V 0.6 V 24 V 12 V 0 V VBOUT1 VAOUT2 24 V 12 V 0 V 24 V 12 V 0 V VBOUT2 200 kHz fAOUT1 fAOUT2 fBOUT1 fBOUT2 Check PHA High, Low and Highest input voltage in case of input of the pulse of 200 kHz (Low-level voltage = 0.6 V, High-level voltage = 2.1 V) to PHA and the frequency of V AOUT1,V AOUT2, VBOUT1, V BOUT2 = 50 kHz as the timing chart in the right figure. 38) TEST High-level input voltage V TESTH 39) TEST Middle-level input voltage V TESTM 40) TEST Low-level voltage V TESTL Check that output status follows as the below chart when Low-level (0.6 V), Middle-level (2.3 V, 2.7 V) and High-level ( 4.0 V) are applied to TEST pin. 4.0 V 2.3 V / 2.7 V 0.6 V TEST pin voltage conditions TJMON pin = Home Position output (For detail, refer to Page 36, 37) TEST High-level input voltage Output transistor：all OFF VAOUT1, VAOUT2, VBOUT1, VBOUT2 = 12 V TJMON pin = VBE monitor Status TEST Low-level input voltage TEST Middle-level input voltage Parameter Chart Output status at input vo ltage of Low, Middle, High-level „ Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701708020 2008-02-20 OFF OFF OFF Hi-Z0 V0.6 V0.6 V0.6 V— Refer to the next page 0.6 V2.1 VRefer to the next page Pulse input31ON2 6, 8, 10, 12, 20, 21, 28, 33 20, 21, 22, 26, 27, 45, 46, 47, Hi-Z5 V4 V V ST1 =VST2 = 0.6 V VST3 = 2.1 V 0.6 V0 V0.6 V0.6 V2.1 V VDECAY1 = 2.1 V VDECAY2 = 2.1 V Pulse input12 or 3ON1352, S7, Hi-Z5 V0.6 V Refer to below chart Refer to below chart 0 V0.6 V0.6 V2.1 V VDECAY1 = 2.1 V VDECAY2 = 2.1 V Pulse input1ON2 6, 8, 10, 12, 28 to 32 30, 31, 34, S6 V PWMSW IS5VOUT VRE F VTEST VST1 VST2 VST3 VDIR VRCSA VRCSB VENABLE VSTB Y VDECAY1 VDECAY2 VPHAS5 to Measuring pin C No. 30) DIR High -level input voltage V DIRH 31) DIR Low-level input voltage V DIRL 34) ST High-level input voltage V STH 35) ST Low-level input voltage V STL Check the DIR Low/High input voltage and ST Low/High input voltage by setting the voltages of DIR, ST1, ST2, ST3 to voltages following to the above chart and checking the operation of each excitation mode (Page 31 to 34). Half-step drive (8-step sequence) / Reverse0.6 V2.1 V0.6 V2.1 V W1-2 phase drive (16-step sequence) / Reverse0.6 V2.1 V2.1 V2.1 V 1-2-phase excitation (8-step sequence) / Reverse0.6 V0.6 V2.1 V2.1 V 2.1 V 2.1 V 0.6 V 0.6 V 0.6 V 0.6 V 0.6 V DIR 0.6 V 0.6 V 0.6 V 2.1 V 2.1 V 0.6 V 0.6 V ST1 2.1 V 0.6 V 2.1 V 2.1 V 0.6 V 2.1 V 0.6 V ST2 2.1 V 0.6 V 2.1 V 0.6 V 0.6 V 0.6 V 0.6 V ST3 2W1-2-phase driver (32-step sequence) / Reverse 2 phase excitation drive (4-step sequence) / Reverse 2W1-2-phase drive (32-step sequence) / Forward W1-2-phase drive (16-stepsequence) / Forward 1-2 phase excitation drive (8-step sequence) / Forward Half-step drive (8-step sequence) / Forward 2 phase excitation drive (4-step sequence) / Forward Exciting mode „ Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701808020 2008-02-20 20) PWMSW High-level input voltage V PWMSWH 21) PWMSW Middle-level input voltage V PWMSWM 22) PWMSW Low-level input voltage V PWMSWL 26) DECAY High-level input voltage V DECAYH 27) DECAY Low-level input voltage V DECAYL 45) PWM OFF time 1 T OFF1 46) PWM OFF time 2 T OFF2 47) PWM OFF time 3 T OFF3 48) Pulse blanking time T B Each value is obtained by the timing chart of VAOUT1(VBOUT1) and VAOUT2(VBOUT2) at VREF = 0 V The timing chart of VAOUT1(VBOUT1)/VAOUT2(VBOUT2) is shown as below. ・For 20) to 22), 45) to 47), check TOFF1 /TOFF2/TOFF3 on the input conditions of PWMSW pin in the below chart. ・For 26), 27), check TDECAY / TOFF on the conditions of DECAY1/DECAY2 in the below chart in case of PWMSW High, Middle, Low-level input voltage. ・For 48), check Low-level interval of VAOUT1(VBOUT1) : TB in the below chart. TOFF2 = 15.2 μs1.3 V TOFF2 = 15.2 μs1.7 V VPWMSWH / VPWMSWM / VPWMSWL TOFF3 = 8.1 μs TOFF1 = 28 μs0.6 V PWMSW 2.3 V Status Voltage conditions Input pin TB t[μs] VAOUT1 / (VBOUT1) VAOUT2 / (VBOUT2) TB 24 V 24 V 12 V 12 V 0 V 0 V TOFF1 / TOFF2 / TOFF3 TDECAY t[μs] TDECAY 100% mode 50% mode 25% mode 0% mode (Slow Decay) Decay control (T DECAY / TOFF) 2.1 V0.6 V 0.6 V2.1 V 2.1 V DECAY2 0.6 V0.6 V 2.1 V DECAY1 Chart TOFF to PWMSW input voltage Chart Decay control to DECAY1/2 input voltage „ Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406701908020 2008-02-20 52) TJMON pin output Low-level volt age at TEST pin High-level input V TJL 53) TJMON pin output leakage curr ent at TEST pin High-level input I TJ(leak) Check when TJMON pin in Home Position output timing chart is Low and High-level. ・ TJMON pin output Low-level voltage at TEST pin High-level input V TJL → Check TJMON pin voltage by connection pull-up resister 100 kΩ (to 5 V) to TJMON pin. ・TJMON pin output leakage current at TEST High-level input ITJ(leak) → Check the leakage current after applying 5 V to TJMON pin. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 1710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 PHA 2W1-2 phase excitation TJMON IAOUT1 IBOUT1 Home Position output timing chart (DIR = Low-level) +100% –100% „ Electrical Characteristics Test Procedures (continued) 1. Test Circuit 1 (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702008020 2008-02-20 1) Output saturation voltage High-level V OH 2) Output saturation voltage Low-level V OL OFFOFFOFFOFFOFFOFFOFFOFFS6 0.6 V 24 V ON ISBOUT2 = +1.2 A BOUT2/ VBOUT2 (h) 0.6 V 24 V ON ISBOUT1 = +1.2 A BOUT1/ VBOUT1 (g) 0.6 V 24 V ON ISAOUT2 = +1.2 A AOUT2/ VAOUT2 (f) 0.6 V 24 V ON ISAOUT1 = +1.2 A AOUT1/ VAOUT1 (e) ONONONONS5

24 V24 V24 V24 VVM

= –1.2 A ISBOUT1 = –1.2 A ISAOUT2 = –1.2 A ISAOUT1 = –1.2 A Applying conditions BOUT2/ VBOUT2 BOUT1/ VBOUT1 AOUT2/ VAOUT2 AOUT1/ VAOUT1 Applying pin/ measuring voltage 0.6 V (a) 0.6 V0.6 V0.6 VVENABLE (b) (c) (d) VPHA AOUT1 24 V 12 V 0 V 5 V 0 V 24 V 12 V 0 V BOUT1 AOUT2 24 V 12 V 0 V 24 V 12 V 0 V BOUT2 (a) (b) (c) (e) (f) (h) (d) (g) Check output saturation voltage High and Low-level on the below conditions „ Electrical Characteristics Test Procedures (continued) 2. Test Circuit 2

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702108020 2008-02-20 4) Output leakage current I LEAK 5 V 37 V OFF ON VSAOUT1 = VSAOUT2 = VSBOUT1 = VSBOUT2 = 0 V AOUT1, AOUT2, BOUT1, BOUT2 / IAOUT1, IAOUT2, IBOUT1, IBOUT2 (e), (f), (g), (h) ONONONONS6 OFFOFFOFFOFFS5 1111S1 to S4

37 V37 V37 V37 VVM

VSBOUT2 = 37 VVSBOUT1 = 37 VVSAOUT2 = 37 VVSAOUT1 = 37 VApplying conditions BOUT2 / IBOUT2 BOUT1 / IBOUT1 AOUT2 / IAOUT2 AOUT1 / IAOUT1 Applying pin/ measuring current 0 V (a)

0 V0 V0 VVENABLE

(b) (c) (d) 3) Flywheel diode forward voltage V DI ONONONONS6 ONONONONS5

0 V0 V0 V0 VVM

ISBOUT2 = 1.2 AISBOUT1 = 1.2 AISAOUT2 = 1.2 AISAOUT1 = 1.2 AApplying conditions BOUT2 / VBOUT2 BOUT1 / VBOUT1 AOUT2 / VAOUT2 AOUT1 / VAOUT1 Applying pin/ Measuring voltage 2.1 V 2.1 V2.1 V2.1 VVENABLE VPHA 37 V 0 V 5 V 0 V 37 V 0 V 37 V 0 V 37 V 0 V (a) (c) (d) AOUT1 BOUT1 AOUT2 BOUT2 Check Flywheel diode forward voltage VDI on the above conditions Check output leakage current I LEAK *1 of each output pin on the above conditions Note) *1 I LEAK : Electrical characteristics No.4 shows absolute values. VENABLE 5 V 0 V (b) (e) (f) (g) (h) „ Electrical Characteristics Test Procedures (continued) 2. Test Circuit 2 (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702208020 2008-02-20 Pin 6 : Phase B motor drive output 2 7 : Phase B current detection 8 : Phase B motor drive output 1 10 : Phase A motor drive output 2 11 : Phase A current detection 12 : Phase A motor drive output 1 Pin 3 : VBE monitor /TEST output /Home Position output ——3 Impedance DescriptionInternal circuitWaveform and voltage Pin No. 800 Pin3 TJMON Pin 6 BOUT2 „ Technical Data 1. I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702308020 2008-02-20 Pin 14 : Charge pump capacitor connection 2 15 : Charge pump circuit output ——14 Pin 13 : Charge pump capacitor connection 1——13 Impedance DescriptionInternal circuitWaveform and voltage Pin No. 1514 300k 125 Pin15 VPUMPPin14 BC2 150 125 Pin13 BC1 „ Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702408020 2008-02-20 Pin 22 : Standby100 kΩ—22 Pin 19 : Enable/disable CTL 20 : Mix Decay setup 2 21 : Mix Decay setup 1 28 : Clock input 29 : Step select 3 30 : Step select 2 31 : Step select 1 32 : Rotation direction 100 kΩ— Impedance DescriptionInternal circuitWaveform and voltage Pin No. Pin19 ENABLE „ Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702508020 2008-02-20 Pin 24 : Internal reference voltage (Output 5 V)——24 Pin 23 : Torque reference voltage input——23 Impedance DescriptionInternal circuitWaveform and voltage Pin No. Pin23 VREF 4k 4k Pin24 S5VOUT 50k 48k 100 „ Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702608020 2008-02-20 Pin 33 : PWM OFF period selection input——33 Pin 25 : TEST mode100 kΩ—25 Impedance DescriptionInternal circuitWaveform and voltage Pin No. 60k 140k Pin33 PWMSW 100k Pin25 TEST „ Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702708020 2008-02-20 ———— Impedance DescriptionInternal circuitWaveform and voltage Pin No. S5VOUT (Pin 24) VM(Pin1, Pin 17) Diode Zener diode Ground „ Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702808020 2008-02-20 OFFONHighHigh Low ENABLE High Low STBY ONON OFFOFF Output transistorControl /Charge pump circuit 1) Truth table (Step select) High High Low Low ST1 High Low High Low ST2 Output OFF——High Half-step drive (8-step sequence)Low High Low High High High High DIR Low Low Low Low ENABLE W1-2 phase drive (16-step sequence)Low 2W1-2 phase drive (32-step sequence)High 1-2 phase excitation drive (8-step sequence)Low Low ST3 2 phase excitation drive (4-step sequence) Output excitation mode (Phase B 90° advance：to Phase A) High High Low Low ST1 High Low High Low ST2 Output OFF——High Half-step drive (8-step sequence)LowLowLow Low Low Low Low DIR Low Low Low Low ENABLE W1-2 phase excitation drive (16-step sequence)Low 2W1-2 phase excitation drive (32-step sequence)High 1-2 phase excitation drive (8-step sequence)Low Low ST3 2 phase excitation drive (4-step sequence) Output excitation mode (Phase B 90° delay ： to Phase A) 2) Truth table (Control/Charge pump circuit) 8.1 μsHigh 15.2 μs 28.0 μs PWM OFF period Low Middle PWMSW 4) Truth table (Decay selection) Note) For each PWM OFF period, Fast Decay is applied according to the above table. 50%LowHigh High High Low DECAY2 Slow DecayLow 25%Low High DECAY1 100% Decay control 3) Truth table (PWM OFF period selection) Home Position outputHigh Test output (Output transistor：OFF) VBE monitor TJMON Low Middle TEST 5) Truth table (Test mode) „ Technical Data (continued) 2. Control mode

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406702908020 2008-02-20 –83.2–55.629 –70.7–70.728147 –55.6–83.227 0–10024126 19.5–98.123 38.3–92.42211 55.6–83.221 70.7–70.720105 –100032168 –98.1–19.531 –92.4–38.33015 –38.3–92.42613 –19.5–98.125 83.2–55.619 92.4–38.3189 98.1–19.517 10001684 98.119.515 92.438.3147 83.255.613 70.770.71263 55.683.211 38.392.4105 19.598.19 0100842 –19.598.17 –38.392.463 –55.683.25 –70.770.7421 –83.255.63 –92.438.321 –98.119.51 Phase B current (%)Phase A current (%)2W1-2 phase (32 Step) W1-2 phase (16 Step) 1-2 phase (8 Step) „ Technical Data (continued) 3. Each phase current value 1) 1-2 phase, W1-2 phase, 2W1-2 phase DIR = Low Note) The definition of Phase A and B current「100%」: (VREF × 0.1) / Current detection resistance

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703008020 2008-02-20 Phase B current (%)Phase A current (%)2W1-2 phase (32 Step) W1-2 phase (16 Step) 1-2 phase (8 Step) –83.255.629 –70.770.728147 –55.683.227 010024126 19.598.123 38.392.42211 55.683.221 70.770.720105 –100032168 –98.119.531 –92.438.33015 –38.392.42613 –19.598.125 83.255.619 92.438.3189 98.119.517 10001684 98.1–19.515 92.4–38.3147 83.2–55.613 70.7–70.71263 55.6–83.211 38.3–92.4105 19.5–98.19 0–100842 –19.5–98.17 –38.3–92.463 –55.6–83.25 –70.7–70.7421 –83.2–55.63 –92.4–38.321 –98.1–19.51 „ Technical Data (continued) 3. Each phase current value (continued) 1) 1-2 phase, W1-2 phase, 2W1-2 phase DIR = High Note) The definition of Phase A and B current「100%」: (VREF × 0.1) / Current detection resistance

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703108020 2008-02-20 „ Technical Data (continued) 4. Each phase current (Timing chart) 1) 2 phase excitation drive (4-step sequence) (ST1 = Low, ST2 = Low, ST3 = Low) 2) Half-step drive (8-step sequence) (ST1 = Low, ST2 = High, ST3 = Low) FWD (DIR = Low) REV (DIR = High) 123412341 IAOUT1 IBOUT1 CLK 123412341 IAOUT1 IBOUT1 CLK 123456781 IAOUT1 IBOUT1 CLK 123456781 IAOUT1 IBOUT1 CLK FWD (DIR = Low) REV (DIR = High) +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% +100% –100%

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703208020 2008-02-20 123456781 3) 1-2 phase excitation (8-step sequence) (ST1 = High, ST2 = Low, ST3 = Low) IAOUT1 IBOUT1 CLK FWD (DIR = Low) 123456781 IAOUT1 IBOUT1 CLK REV (DIR = High) +100% –100% +100% –100% +100% –100% +100% –100% „ Technical Data (continued) 4. Each phase current (Timing chart) (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703308020 2008-02-20 4) W1-2 phase excitation (16-step sequence) (ST1 = High, ST2 = High, ST3 = Low) 123456789 11 12 13 14 15 16 110 IAOUT1 IBOUT1 CLK FWD (DIR = Low) 123456789 11 12 13 14 15 16 110 IAOUT1 IBOUT1 CLK REV (DIR = High) +100% –100% +100% –100% +100% –100% +100% –100% „ Technical Data (continued) 4. Each phase current (Timing chart) (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703408020 2008-02-20 5) 2W1-2 phase excitation (32-step sequence) (ST3 = High) 1 2 3 4 5 6 7 8 9 1 11 21 31 41 51 61 710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 126 IAOUT1 IBOUT1 CLK FWD (DIR = Low) +100% –100% +100% –100% REV (DIR = High) 123456789 1 1 1 2 1 3 1 4 1 5 1 6 1 710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 126 IAOUT1 IBOUT1 CLK +100% –100% +100% –100% „ Technical Data (continued) 4. Each phase current (Timing chart) (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703508020 2008-02-20 „ Technical Data (continued) 5. Timing chart at change of DIR (Ex.1) Timing chart at 1-2 phase excitation (DIR：Low → High) PHA A-ch. motor current B-ch. motor current DIR At change of DIR, the state before the change is held and the operation is continued. State ： 5 6 7 6 7 6 5 (Ex.2) Timing chart at 1-2 phase excitation (DIR：High → Low) PHA A-ch. motor current B-ch. motor current DIR State ： 3 4 5 4 3 2 1 At change of DIR, the state before the change is held and the operation is continued.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703608020 2008-02-20 This LSI has built-in Home Position function to reduce the displacement of motor current state at change of excitation mode while a motor is driving. Home Position function , following as the below chart, outputs Low-level voltage to TJMON pin at the timing when the displacement of motor current state is minimum at change of excitation mode in case of TEST = High-level input. At other timing, Home Position function outputs High-level voltage (in case the pull-up resister (recommendation : 100 kΩ to 5 V) is connected because TJMON pin is made with open drain) at TJMON pin. –100% –100% 2 phase excitation –100% 1-2 phase excitation –100% Half-step –100%–100%Phase B current 0%0%Phase A current 2W1-2 phase excitation W1-2 phase excitation Table Output current of each excitation mo de at Home Position = Low (DIR = Low) 123456789 1 1 1 2 1 3 1 4 1 5 1 6 1 710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 126 PHA 2W1-2 phase TJMON IAOUT1 IBOUT1 W1-2 phase IAOUT1 IBOUT1 1-2 phase IAOUT1 IBOUT1 2 phase IAOUT1 IBOUT1 Half-step IAOUT1 IBOUT1 1) Home Position output timing chart (DIR = Low) +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% „ Technical Data (continued) 6. Home Position function

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703708020 2008-02-20 –100% –100% 2 phase excitation –100% 1-2 phase excitation –100% Half-step –100%–100%Phase B current 0%0%Phase A current 2W1-2 phase excitation W1-2 phase excitation Table Output current of each excitation mo de at Home Position = Low (DIR = High) 1 2 3 4 5 6 7 8 9 1 11 21 31 41 51 61 710 18 19 20 21 22 23 24 25 27 28 29 30 31 32 126 PHA 2W1-2 phase TJMON IAOUT1 IBOUT1 W1-2 phase IAOUT1IBOUT1 1-2 phase IAOUT1 IBOUT1 2 phase IAOUT1 IBOUT1 Half-step IAOUT1 IBOUT1 2) Home Position output timing chart (DIR = High) +100% –100% +100% –100% +100% –100% +100% –100% +100% –100% „ Technical Data (continued) 6. Home Position function (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703808020 2008-02-20 1. Special attention and precaution in using 1. This IC is intended to be used for ge neral electronic equipment [stepping motor]. Consult our sales staff in advance for information on the following applications: x Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body. x Any applications other than the standard applications intended. (1) Space appliance (such as artificial satellite, and rocket) (2) Traffic control equipment (such as for automobile, airplane, train, and ship) (3) Medical equipment for life support (4) Submarine transponder (5) Control equipment for power plant (6) Disaster prevention and security device (7) Weapon (8) Others : Applications of which reliability equivalent to (1) to (7) is required 2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might smoke or ignite. 3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 4. Perform a visual inspection on the PCB be fore applying power, otherwise damage might happen due to problems such as a solder- bridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin- V CC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short) . Especially, for the pins below, take notice Power supply fault, Ground fault, load short and short between the pin below and current detection pin. (1) AOUT1(Pin 12), AOUT2(Pin 10), BOUT1(Pin 8), BOUT2(Pin 6) (2) BC1(Pin 13), BC2(Pin 14), VPUMP(Pin 15) (3) VM1(Pin 17), VM2(Pin 1), S5VOUT(Pin 24) (4) RCSA(Pin 11), RCSB(Pin 7) And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6. When using the LSI for new models, verify the safe ty including the long-term reliability for each product. 7. When the application system is designed by using this LSI, be sure to confirm notes in this book. Be sure to read the notes to descriptions and the usage notes in the book. 8. Connect the metallic plate (fin) on the back side of the IC with the GND potential. The thermal resistance and the electrical characteristics are guaranteed only when the metallic plate (fin) is connected with the GND potential. 9. Confirm characteristics fully when using the LSI. Secure adequate margin after considering variation of external part and this IC including not only static characteristics but transient characteristics. Especially, Pay attention that abnormal current or voltage must not be applied to external parts because the pins (Pin 6, 8, 10, 12, 13, 14, 15) output high current or voltage. „ Usage Notes

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406703908020 2008-02-20 „ Usage Notes (continued) 2. Notes of Power LSI. 1. Design the heat radiation with sufficient margin so that Po wer dissipation must not be exceeded base on the conditions of power supply voltage, load and ambient temperature. (It is recommended to design to set connective parts to 70% to 80% of maximum rating) 2. The protection circuit is for maintainin g safety against abnormal operation. Therefore, the protection circuit should not work during normal operation. Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to VM short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be damaged before the thermal protection circuit could operate. 3. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven. 4. The product which has specified ASO (Area of Safe Operation) should be operated in ASO. 5. Verify the risks which might be cause d by malfunctions of external parts. 6. Set capacitance value between VPUMP and GND so that VPUMP (Pin 15) must not exceed 43 V transiently at the time of motor standby to motor start. 7. This IC employs a PWM drive method that switches the high-current output of the output transistor. Therefore, the IC is apt to generate noise that may cause the IC to malfunction or have fatal damage. To prevent these problems, the power supply must be stable enough. Therefore, the capacitance between the S5VOUT and GND pins must be a minimum of 0.1 μF and the one between the VM and GND pins must be a minimum of 47 μF and as close as possible to the IC so that PWM noise will not cause the IC to malfunction or have fatal damage.

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406704008020 2008-02-20 3. Notes 1) Pulse blanking time This IC has pulse blanking time (0.7 μs/Typ.value)to prevent erroroneous current detection caused by noise. Therefore, the motor current value will not be less than current determined by pulse blanking time. Pay attention at the time of minimum current control. The relation between pulse blanking time and minimum current value is shown as Chart 1. In addition, increase-decrease of motor current value is determined by L value, wire wound resistance, induced voltage and PWM on Duty inside a motor. TB TPWM At normal operation In case of setting less than minimum current value Setup current value Setup current value Minimum current value TPWM : PWM OFF period TB : Pulse blanking time (Refer to ■Electrical Characteristics No.48) Chart 1. RCS current waveform 2) VREF voltage When VREF voltage is set to Low-level, erroroneous detection of current might be caused by noise because threshold of motor current detection comparator becomes low (= VREF/10 × motor current ratio [%] (Refer to Page 29, 30). Use this IC after confirming no misdetection with setup REF voltage. 3) Notes on interface Absolute maximum of Pin 19 to Pin 23 and Pin 28 to Pin 33 is –0.3 V to 6 V. When the setup current for a motor is large and lead line of GND is long, GND pin potential might rise. Take notice that interface pin potential is negative to difference in potential between GND pin reference and interface pin in spite of inputting 0 V to the interface pin. At that time, pay attention allowable voltage range must not be exceeded. 4) Notes on test mode When inputting voltage of above 0.6 V and below 4.0 V to TEST (Pin 25), this LSI might become test mode. When disturbance noise etc. makes this LSI test mode, motor output pin might be Hi-Z. Therefore, use this LSI on condition that TEST pin is shorted to GND or S5VOUT at normal motor operation. „ Usage Notes (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406704108020 2008-02-20 3. Notes (continued) 5) Notes on Standby mode release / Low voltage protection release This LSI has all phases OFF period of about 140 μs (typ) owing to release of Standby and Low voltage protection (Refer to the below figure). This is why restart from Standby and Low voltage protection is performed after booster voltage rises sufficiently because booster operation stops at Standby and Low voltage protection. When the booster voltage does not rise sufficiently during all phases OFF period due to that capacitance voltage between VPUMP and GND becomes large etc., the IC might overheat. In this case, release Standby and Low voltage protection at ENABLE = High-level, and restart at ENABLE = Low-level after the booster voltage rises sufficiently. Moreover, take notice that state of motor current becomes default position at Standby and Low voltage protection operation following as 3. Notes No.8. Motor output Standby Standby All phases OFF Start (At ENABLE = Low) All phases OFF (At ENABLE = High) STBY About 140 μs(typ) Low High All phases OFF Motor output All phases OFF Restart (At ENABLE = Low) All phases OFF (At ENABLE = High) VM About 140 μs(typ) Low High All phases OFF (Low voltage protection) 【At Standby release】 【At Low voltage protection release】 Standby release Ground fault detection Ground fault detection About 5.5 μs(typ) About 5.5 μs(typ)6) Ground fault protection function This IC has built-in ground fault protection function to detect ground fault of motor output pin at board mounting. As the above figure, ground fault detection function will operate after release of Low voltage protection and Standby, and check ground fault of motor output pins. If ground fault is detected, this function makes motor output all phases OFF and motor operation stop. If ground fault is not detected, this function makes motor start. However, take notice that IC might be destroyed before ground fault protection function operates in case that ASO ( Area of Safe Operation ) of device or maximum rating are exceeded in a moment. In addition, this function might not detect ground fault when starting VM at STBY = High-level. It is recommended that VM is started at STBY = Low-level. In case of release of ground fault detection, restart IC after inputting low voltage to STBY pin or making VM voltage OFF. 7) Notes on release of thermal protection The release of thermal protection operation will restart after all phases OFF of about 140 μs and ground fault detection operation as 3. Notes No.5, 6. Moreover, take notice that the state of motor current will become default position after release of thermal protection operationa s 3. Notes No.8 „ Usage Notes (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406704208020 2008-02-20 Default electrical angleExcitation mode 0°1-2 phase excitation (8 step) 0°W1-2 phase excitation (16 step) 0°2W1-2 phase excitation (32 step) 0°Half-step (8 step) –45°2 phase excitation (4 step) AOUT1 current BOUT1 currentDefault：0°→ Default of Half/ 1-2/W1-2/2W1-2 phases excitation Default： –45°→ Default of 2 phase excitation DIR = Low DIR = High DIR = Low DIR = High Table default position of each excitation mode 3. Notes (continued) 8) Default of motor current state Default of motor current follows as the below figure after release of Low voltage protection, Standby and thermal protection on each excitation mode. A BCD PHA DIR 9) PHA input signal and DIR input signal The set/hold time of PHA and DIR input signals, PHA input minimum pulse width (High/Low) are shown as the below figure. Input signals after securing set/hold time. 5 μs or morePHA input minimum pulse width (High)A 5 μs or morePHA input minimum pulse width (Low)B DIR hold time DIR set time Contents TimePeriod 2 μs or moreD 2 μs or moreC „ Usage Notes (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406704308020 2008-02-20 PHA A-ch. motor current Ex.) 1-2 phase excitation ENABLE A-ch. motor current ENABLE PHA 7 8 1 2 1 2 3 4 5 6 3 4 5 6 7 8 In spite of stop at state[6] , because PHA is input at ENABLE = High, the motor will restart after ENABLE = Low at state [3]. 1 2 3 4 5 6 6 7 8 1 2 3. Notes (continued) 10) PHA input at ENABLE = High As the below figure (Ex. 1-2 phase excitation), when inputting PHA at the time of motor stop and ENABLE = High (All phases are OFF → Motor current = 0 A), the setup value of motor current will proceed at PHA input. Therefore, in case of restart at ENABLE = Low, take notice that the position of restart is where the current state just before motor stop gains PHA input. Low Low Low Low High High In spite of stop at state [6] , because PHA is not input at ENABLE = High, the motor will restart after ENABLE = Low at state [6] just before stop. Motor stop Motor stop „ Usage Notes (continued)

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.214406704508020 2008-02-20 Temp[°C] VBE[V] ΔVBE / Δtemp = –1.86 [mV / °C] 1500 TJMON pin temperature characteristics 3. Notes (continued) 13) IC junction temperature In case of measuring chip temperature of this IC, measure the voltage of TJMON pin (Pin 3) and estimate the chip temperature from the data below. However, because this data is technical reference data, conduct a sufficient reliability test of the IC and evaluate the product with the IC incorporated. 14) Speed of supply and cut of power When supplying to VM pin (Pin 1, 17) , set the rise speed of VM voltage to less than 0.1 V/μs and fall speed to less than 0.1 V/μs. If the speed of rise and fall of power supply is too rapid, that might cause malfunction and destruction of the IC. In this case, conduct a sufficient reliability test and also check a sufficient evaluation for a product. Supply voltage VM Time less than 0.1 V/μs, rise less than 0.1 V/μs, fall „ Usage Notes (continued)

Semiconductor Company, Panasonic Corporation Package Code Regulations No. Revised Semiconductor Company Panasonic Corporation Package Standards Established by Applied by Checked by Prepared by HSOP034-P-0300A SC3S0829 61 M.ItohM.OkajimaH.YoshidaH.Shidooka Established: 2004-03-18 Revised : 2009-06-26

Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards Unit:mm Lead Finish Method : Pd Plating Lead Material : Cu Alloy Body Material : Epoxy Resin 1. Outline Drawing Established: 2004-03-18 Revised : 2009-06-26

Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 2. Package Structure (Technical Report : Reference Value) Method Material Method Material Method Material 23 1 6 45 7 Si Transfer molding Epoxy resin Wirebond Outer lead surface Au Cu alloy Pd plating Leadframe material Inner lead surface Chip Material Resin adhesive method Mass 250 mg Pd plating Adhesive material Thermo-compression bonding Molding Chip mount Established: 2004-03-18 Revised : 2009-06-26

Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 3. Mark Layout Product Name Brand Mark Date Code 1-pin direction Established: 2004-03-18 Revised : 2009-06-26

Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 4. Power Dissipation (Technical Report) 0.000 0.200 0.400 0.600 0.800 1.000 1.200 1.400 1.600 0 25 50 75 100 125 150 Ambient Temperature ( o C ) Power Dissipation( Ｗ ) Without PWB Rth(j-a) = 171.6 ℃/W 1.453 0.728 Mount On PWB ［Glass-Epoxy:50X50X0.8t(mm)］ Rth(j-a) = 86.0 ℃/W Heat dissipation fin (Daipaddo) The state where it does not mount Established: 2004-03-18 Revised : 2009-06-26

Semiconductor Company, Panasonic Corporation RevisedEstablished Package Standards 5. Power Dissipation (Supplementary Explanation) Package Semiconductor element Rth(j-c) Rth(c-a) Rth(j-a) Ta Tc Tj PWB [Definition of each temperature and thermal resistance] Ta ：Ambient air temperature ˞The temperature of the air is defined at the position where the convection, radiation, etc. don’t affect the temperature value, and it’s separated from the heating elements. Tc ：It’s the temperature near the center of a package surface. The package surface is defined at the opposite side if the PWB. Tj ：Semiconductor element surface temperature (Junction temperature.) Rth(j-c)：The thermal resistance (difference of temperature of per 1 Watts) between a semiconductor element junction part and the package surface Rth(c-a)：The thermal resistance (difference of temperature of per 1 Watts) between the package surface and the ambient air Rth(j-a)：The thermal resistance (difference of temperature of per 1 Watts) between a semiconductor element junction part and the ambient air [Supplementary information of PWB to be used for measurement] The supplement of PWB information for Power Dissipation data (Technical Report）are shown below. FR-44-layer4-layer FR-41-layerGlass-Epoxy Resin MaterialTotal LayerIndication [Notes about Power Dissipation（Thermal Resistance）] Power Dissipation values（Thermal Resistance）depend on the conditions of the surroundings, such as specification of PWB and a mounting condition , and a ambient temperature. (Power Dissipation (Thermal Resistance) is not a fixed value.) The Power Dissipation value（Technical Report）is the experiment result in specific conditions (evaluation environment of SEMI standard conformity) ,and keep in mind that Power Dissipation values (Thermal resistance) depend on circumference conditions and also change. [Experiment environment] Power Dissipation（Technical Report）is a result in the experiment environment of SEMI standard conformity. （Ambient air temperature (Ta) is 25 degrees C） [Definition formula] Rth(j-c) = Tj-Tc P Rth(c-a) = Tc-Ta P Rth(j-a) = Tj-Ta P (ˆ/W) (ˆ/W) (ˆ/W) Tj={Rth(j-c)+Rth(c-a)}ʷP+Ta =Rth(j-a)ʷP+Ta P:power(W)Fig1. Definition image = Rth(j-c)＋Rth(c-a) Established: 2004-03-18 Revised : 2009-06-26

In case that the semiconductor packages are mounted on the PCB, the soldering should be performed under the following conditions. ① Reflow soldering ＊Peak temperature : less than 260 ℃ ＊Temperature is measured at package surface point ② Wave soldering (Flow soldering) ＊Temp. of solder : 260 ℃ or less ＊Soak time : within 5 s ＊Number of flow : only 1 time ③ Manual soldering ＊Iron Temperature : 350 ℃ or less (Device lead temperature : 270 ℃､10 s max.) ＊Soldering time : within 3 s ＊Number of manual soldering : only 1 time No. 11-184 Product name : Package : AN44067A-VF HSOP034-P-0300A 8- Number of reflow within 2 times 7b Down rate 2 ℃/s～5 ℃/s 6t w High temp. region hold time within 60 s (≧220 ℃) 5t p Peak temp. hold time 10 s±3 s 4T p Peak temp. 255 ℃+5 ℃､-0 ℃ 3a Rising rate 2 ℃/s～5 ℃/s 2 ｔ１ Pre-heating temp. hold time 60 s～120 s 1T 1 Pre-heating temp. 150 ℃～180 ℃ Recommended Soldering Conditions Total pages page Industrial Devices Company, Panasonic Corporation 2012/3/7 Prepared Revised No． mark contents value １．Recommended Soldering Conditions max. 260 ℃Reflow peak temp. : 140 160 180 200 220 240 255 ℃ Time tw tp Tp 220 ℃ 260 ℃ a b 260

※ Because the taping and the magazine materials are not the heat-resistant materials, the bake at 125℃ cannot be done. Therefore, please solder everything or control everything in the rule time. Please keep them in an equal environment with the moisture-proof packaging or dry box. (Temperature: room temperature, relative humidity: 30% or less. ) To control storage time, when bake in the taping and the magazine is necessary, it is necessary for each type to set a bake condition. Please inquire of our company. ① Storage environment conditions: keep the following conditions Ta=5 ℃～30 ℃､RH=30 %～70 %. ② Storage period before opening dry pack shall be 1year from a shipping day under Ta=5 ℃～30 ℃､ RH=30 %～70 %. When the storage exceeds, Bake at 125 ℃ with 15 h to 25 h. ③ Baking cycle should be only one time. Please be cautious of solderability at baking. ④ In case that use reflow two times, 2nd reflow must be finished within 168 hours. ⑤ Remove flux sufficiently from product in the washing process. ( Flux : Chlorineless rosin flux is recommended.) ⑥ In case that use ultrasonic for product washing, There is the possibility that the resonance may occur due to the frequency and shape of PCB. It may be affected to the strength of lead. Please be cautious of this matter. No. ☆ AN44067A-VF limitation, low temperature bake condition ： 40 ℃ / 25 %RH or less / 192 h 11-184 2．Storage environment after dry pack opening Open dry pack Storage environment kept up to soldering (at 30 ℃/70 %RH max. , within 168h) Soldering Bake at 125 ℃ with 15 h to 25 h *Please refer to the following when doing at the low temperature bake. When the storage time exceeds 3．Note Recommended Soldering Conditions Total pages page Industrial Devices Company, Panasonic Corporation 2012/3/7 Prepared Revised

Industrial Devices Company, Panasonic Corporation 2012.03.13 Prepared Revised Recommended Land Pattern Total pages page

Specifications of packing by the embossment tape ( Specifications for dampproof packing of the reel without the inner carton) Total pages Packing Specification page Revised Semiconductor Company，Panasonic Corporation Prepared 2009.03.09 AN12345A-NB 3000pcs. (3N)AN12345A-NB 1000 (3N)2 10N112200-NB 108010 AN12345A-NB AN12345A-NB 1.23-45 410N112300 2058 USP4B42516 AN12345A-NB 12345678 3000 23456789 3000 34567890 3000 45678901 3000 307 150000 Panasonic M MADE IN JAPAN Embossment carrier tape Top cover tape AN12345A-NB 90000pcs. (3N)AN12345A-NB 1000 (3N)2 10N112200-NB 108010 AN12345A-NB AN12345A-NB 1.23-45 410N112300 2058 USP4B42516 AN12345A-NB 12345678 3000 23456789 3000 34567890 3000 45678901 3000 307 150000 Panasonic M MADE IN JAPAN Corrugated cardboard for partition Outer box Laminated aluminum bag Inner frame C3 Label (Sampl)Reel Desiccant C3 Label (Sampl)

3000 Pcs Reel × 1Pcs

Packing case 15000 Pcs Reel × ５Pcs V F Form IC quantity Contents Packing quantity 2) Reel 3) Packing case Unit : mm Packing 1) Tape Reel Total pagesPacking Specification page Revised Semiconductor Company，Panasonic Corporation Prepared Draw out direction Emboss carrier tape 25.5 330 360 360 220

Semiconductor Company，Panasonic Corporation Unit : mm Prepared Revised Packing Specification Total pages page Dimensions & Tolerance Top-coverd-tape Range

Industrial Devices Company, Panasonic Corporation

1 Kotari-yakemachi, Nagaokakyo City, Kyoto 617-8520, Japan

Tel:075-951-8151

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