Driver IC

AN32058A

Panasonic Semiconductor

7 x 7 Dots Matrix LED Driver LSI

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AN32058A PANASONIC

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AN32058A is 49 Dots Matrix LED Driver. It can drive up to 16 RGB LEDs.  7 x 7 LED Matrix Driver (Total LED that can be driven = 49)  Built-in memory (ROM and RAM)  LDO : 2-ch  SPI Interface : 1-ch  Driver for RGB color unit : 1-ch  44 pin Plastic Quad Flat Non-leaded package (QFN Type)

APPLICATIONS

X0~X6 VB VLED1 VLED2 Y0~Y6 LDO2 Battery INT RGBGND PGND AGND 1.0 F DI DO RSTB 27 k  CE CLK LEDCTL IREF B G R LDOCNT LED LDO1 1.0 F VREFD 1.0 F CPU I/F http://www.semicon.panasonic.co.jp/en/ 7 x 7 Dots Matrix LED Driver LSI  Mobile Phone  Smart Phone  PCs  Game Consoles  Home Appliances etc. TYPICAL APPLICATION Note) The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of t he above illustrated application circuit in the design of the equipment. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—V– 0.3 to 3.4LEDCTL, RSTB, CE, CLK, DIInput Voltage Range —V– 0.3 to 6.0LDOCNT —V– 0.3 to 3.4INT, DO Output Voltage Range —V– 0.3 to 6.5 R, G, B, LDO1, LDO2, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 —kV2.0HBM (Human Body Model)ESD *2C– 30 to + 85ToprOperating ambience temperature *2C– 30 to + 125TjOperating junction temperature *2C–5 5t o+1 2 5TstgStorage temperature *1V6.5VLEDMAX NoteUnitRatingSymbolParameter *1V6.0VBMAX Supply voltage 0.557 W1.392 W71.8 C /W44 pin Plastic Quad Flat Non-leaded package (QFN Type) PD (Ta=85 C)PD (Ta=25 C) JAPACKAGE POWER DISSIPATION RATING Note) For the actual usage, please refer to the P D-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. CAUTION Although this IC has built-in ESD protection circuit, it may still sustain permanent damage if not handled properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1 VB MAX = VB, VLEDMAX = VLED1 = VLED2. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25 C. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

RECOMMENDED OPERATING CONDITIONS *1V4.63.73.1VB Supply voltage range *1V5.65.03.1VLED —V3.0—–0 . 3LEDCTL, RSTB, CE, CLK, DIInput Voltage Range *2VVB + 0.3—–0 . 3LDOCNT —V3.0—–0 . 3INT, DO Output Voltage Range *2VVLED + 0.3—–0 . 3 R, G, B, LDO1, LDO2, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 Typ.Min. NoteUnitMax.SymbolParameter Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. Do not apply external currents and voltages to any pin not spe cifically mentioned. Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, RGBGND and PGND. VB is voltage for VB. VLED is voltage for VLED1 and VLED2. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—mA20010050 LDOCNT = High REG18 = High VLDO1 = 0 V, IPT1 = ILDO1 IPT1Short circuit protection current —A128— At Standby mode LDOCNT = Low LDO2 is active. ICC2Current consumption (2) —V1.911.851.79ILDO1 = – 30 mAVL1Output voltage —dB–4 0–4 5— VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO1 = – 15 mA PSL11 = 20log (acVLDO1 / 0.2) PSL11Ripple rejection (1) —dB–2 5–3 5— VB = 3.6 V + 0.2 V[p-p] f = 10 kHz I LDO1 = – 15 mA PSL12 = 20log (acVLDO1 / 0.2) PSL12Ripple rejection (2) V V 0.64 1.27 Reference current —0.540.44I IREF = 0 AVIREFOutput voltage Voltage regulator (LDO1) —A2418—LDOCNT = High LDO1 and LDO2 are active.ICC3Current consumption (3) —1.241.21IVREF = 0 AVREFOutput voltage Reference voltage Current consumption —A10—At OFF mode LDOCNT = LowICC1Current consumption (1) Limits Typ UnitMax NoteMinCondition SymbolParameter

ELECTRICAL CHARACTERISTICS

VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—MHz1.441.200.96—FDCOscillation frequency —mA30010050 LDOCNT = High VLDO2 = 0V IPT2 = ILDO2 IPT2Short circuit protection current —V2.942.852.76ILDO2 = – 30 mAVL2Output voltage —4.82— IY0, Y1, Y2, Y3, Y4, Y5, Y6 = 5 mA RSCAN = VY0, Y1, Y2, Y3, Y4, Y5, Y6 / 5 mA RSCANResistance at the Switch ON —dB–1 5–2 5— VB = 3.6 V + 0.2 V[p-p] f = 10 kHz ILDO2 = – 15 mA PSL22 = 20log (acVLDO2 / 0.2) PSL22Ripple rejection (2) SCAN Switch Oscillator Voltage regulator (LDO2) —dB–3 0–3 5— VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO2 = – 15 mA PSL21 = 20log (acVLDO2 / 0.2) PSL21Ripple rejection (1) Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—A1—— Current OFF setup VX0, X1, X2, X3, X4, X5, X6 = 4.75 V IMXOFF = IX0, X1, X2, X3, X4, X5, X6 IMXOFFLeakage Current when matrix LED turns off *1mA8.9928.3267.660 At 8 mA setup V X0, X1, X2, X3, X4, X5, X6 = 1 V IMX8 = IX0, X1, X2, X3, X4, X5, X6 IMX8Output current (4) *1mA4.4904.1573.824 At 4 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX4 = IX0, X1, X2, X3, X4, X5, X6 IMX4Output current (3) *1mA2.2392.0731.907 At 2 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX2 = IX0, X1, X2, X3, X4, X5, X6 IMX2Output current (2) *1mA1.1161.0330.950 At 1mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX1 = IX0, X1, X2, X3, X4, X5, X6 IMX1Output current (1) —%5—–5 The average value of all channels, and the current error of each channel IMXCHThe error between channels Current generator (For 7  7 dots matrix LED) *1mA16.91415.66114.408 At 15 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX15 = IX0, X1, X2, X3, X4, X5, X6 IMX15Output current (5) Limits Typ Unit Max Note Min Condition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. *1 : Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—A1—— Current OFF setup VR, G, B = 4.75 V IRGBOFF = IR, G, B IRGBOFFLeakage Current when RGB turn off *1mA8.8168.1637.510At 8 mA setup V R, G, B = 1 VIRGB8Output current (4) *1mA4.4184.0913.764At 4 mA setup V R, G, B = 1 VIRGB4Output current (3) *1mA2.2202.0561.892At 2 mA setup VR, G, B = 1 VIRGB2Output current (2) *1mA1.1131.0310.949At 1mA setup V R, G, B = 1 VIRGB1Output current (1) —%5—–5 The average value of all channels, and the current error of each channel IRGBCHThe error between channels Current generator (For RGB color unit) Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. *1 : Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

0.2 (0.15) IINT = 2 mA VDDSEL = LDO2 (IINT = 0.5 mA ) VOL1Output voltage of Low-level (1) INT —V——LDO1  0.8 IINT = – 2 mA VDDSEL = LDO1VOH2Output voltage of High-level (2) —A10—VLEDCTL, RSTB, CSB, CLK, DI = 0 V IIL = ILEDCTL, RSTB, CE, CLK, DI IILInput current of Low-level —A10—VLEDCTL, RSTB, CE, CLK, DI = 1.85 V IIH = ILEDCTL, RSTB, CE, CLK, DI IIHInput current of High-level —V0.4—–0 . 3Low-level recognition voltageVILInput voltage range of Low- level —VLDO2 + 0.3—LDO1  0.8High-level recognition voltageVIHInput voltage range of High- level LDO1 0.3 (0.15) IINT = 2 mA VDDSEL = LDO1 (IINT = 0.5 mA ) VOL2Output voltage of Low-level (2) SPI I/F，LEDCTL，RSTB —V——LDO2  0.8 IINT = – 2 mA VDDSEL = LDO2VOH1Output voltage of High-level (1) Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—VLDO1  0.2——IDO = 2 mAVOLOutput voltage of Low-level —A10—VLDOCNT = 0 V IIL = ILDOCNT IILInput current of Low-level —A10—VLDOCNT = 3.6 V IIH = ILDOCNT IIHInput current of High-level —V0.4—–0 . 3Low-level recognition voltageVILInput voltage range of Low-level —VVB + 0.3—VB  0.7High-level recognition voltageVIHInput voltage range of High-level LDOCNT —V——LDO1  0.8IDO = – 2 mAVOHOutput voltage of High-level Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

MaxTyp NoteUnitLimitsCondition SymbolParameter Min *3ms—5—Time until output voltage reaches to 10%Tsd2Fall time ILDO1 = – 15 mA  – 50 A( 1 s) ILDO1 = – 50 A  – 15 mA (1 s) Time until output voltage reaches to 10% Time until output voltage reaches to 0 V to 90% *3ms—0.25—Time until output voltage reaches to 0 V to 90%Tsu2Rise time *3mA—15——IOMAX2Maximum load current *3mV—70—ILDO2 = – 50 A  – 15 mA (1 s)Vtr21Load transient response (1) *3mV—70—ILDO2 = – 15 mA  – 50 A( 1 s)Vtr22Load transient response (2) TSD (Thermal shutdown circuit) *3ms—0.25—Tsu1Rise time *3ms—5—Tsd1Fall time *3mA—15—IOMAX1Maximum load current *3mV—70—Vtr11Load transient response (1) *3mV—70—Vtr12Load transient response (2) *4C—160— Temperature which LDO1, LDO2, Constant current circuit, Matrix SW and RGB turns off. TdetDetection temperature *5C—110—Returning temperatureTsd11Return temperature Voltage regulator (LDO2) Output capacitor 1 F, Output capacitor’s ESR less than 0.1  Voltage regulator (LDO1) Output capacitor 1 F, Output capacitor’s ESR less than 0.1  ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. Note) *2 : Rise time and Fall time are defined as below. Actual evaluation result of rise time : LDO1 : 290 to 400 s, LDO2 : 220 to 310 s Actual evaluation result of fall time : LDO1 : 6.2 to 8.5 ms, LDO2 : 5.8 to 7.9 ms *3 : Typical Design Value *4 : LDO1, LDO2, Constant current circuit, and Matrix SW and RGB are turned off when TSD is High. When TSD is High, the register is set as 14hD1 = 1. However, data can be read only when the register is read immediately after INT occurs since internal regulator is turned off. *5 : Only LDO1 and LDO2 return after ON state of TSD. A logic part will be in Reset state. LDOCNT Serial LDO2 10% 90% Tsu2 Tsd2 LDO1 90% 10% Tsu1 Tsd1 Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

Microcomputer interface characteristic (Vdd = 1.85 V  3 %) Read access Timing *3ns—125——tscyc1CLK cycle time *3ns—60——twhc1CLK cycle time High period *3ns—60——twlc1CLK cycle time Low period *3ns—62——tss1Serial-data setup time *3ns—62——tsh1Serial-data hold time *3ns—62——tcsw1Transceiver interval *3ns—5——tcss1Chip enable setup time *3ns—5——tcgh1Chip enable hold time *3ns—25—Only read modetdodly1DC delay time *3ns—60——twlc1CLK cycle time Low period *3ns—5——tcgh1Chip enable hold time *3ns—62——tsh1Serial-data hold time *3ns—62——tcsw1Transceiver interval *3ns—5——tcss1Chip enable setup time *3ns—62——tss1Serial-data setup time Microcomputer interface characteristic (Vdd = 1.85 V  3 %) Write access Timing *3ns—125——tscyc1CLK cycle time *3ns—60——twhc1CLK cycle time High period twlc1 CLK DO DI Timing chart tscyc1 tsh1tss1 CE tcss1 tcsw1 tcgh1 tdodly1 twhc1 ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C  2 C unless otherwise specified. Note) *3 : Typical Design Value Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

R RGBGND G B DO DI CLK CE INT LDO2 N.C. N.C. LEDCTL VLED1 VLED2 N.C. N.C. N.C. PGND N.C. N.C. VB LDO1 RSTB IREF LDOCNT VREFD AGND N.C. N.C. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

No Connection—N.C. The power supply's connect terminal for BGR circuit and LDO circuit.Power supplyVB2 LDO1 ( 1.85 V ) output terminal.OutputLDO13 Reset input terminal ("L" active )InputRSTB4 The resistance connect terminal for constant current value setup.OutputIREF5 ON/OFF control terminal of LDO1 and LDO2.InputLDOCNT6 BGR circuit output terminal.OutputVREFD7 The GND terminal for Analog circuitry.GroundAGND8 The output terminal of matrix switching control. It connects with the G Column of matrix LED.OutputY69 The power supply's connect terminal for matrix LED. Connect with the output of battery or step-up DC/DC converterPower supplyVLED2 VLED1 The output terminal of matrix switching control. It connects with the F Column of matrix LED.OutputY514 The output terminal of matrix switching control. It connects with the E Column of matrix LED.OutputY415 The output terminal of matrix switching control. It connects with the D Column of matrix LED.OutputY316 The output terminal of matrix switching control. It connects with the C Column of matrix LED.OutputY217 The output terminal of matrix switching control. It connects with the B Column of matrix LED.OutputY119 The output terminal of matrix switching control. It connects with the A Column of matrix LED.OutputY020 LED's lighting ON/OFF control terminal. ( It is based on register 0Ah.)InputLEDCTL21 DescriptionTypePin namePin No. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

PIN FUNCTIONS (continued) Constant current circuit. The output terminal of PWM control. It connects with the 1st Row of matrix LED.OutputX024 Constant current circuit. The output terminal of PWM control. It connects with the 2nd Row of matrix LED.OutputX125 Constant current circuit. The output terminal of PWM control. It connects with the 3rd Row of matrix LED.OutputX226 Constant current circuit. The output terminal of PWM control. It connects with the 4th Row of matrix LED.OutputX327 The GND terminal for matrix LEDGroundPGND28 Constant current circuit. The output terminal of PWM control. It connects with the 5th Row of matrix LED.OutputX429 Constant current circuit. The output terminal of PWM control. It connects with the 6th Row of matrix LED.OutputX530 Constant current circuit. The output terminal of PWM control. It connects with the 7th Row of matrix LED.OutputX631 LED contact terminal.OutputR34 The GND terminal for RGB terminal.GroundRGBGND35 LED contact terminal.OutputG36 LED contact terminal.OutputB37 Data output terminal for SPI interface.OutputDO38 Data input terminal for SPI interface.InputDI39 Clock input terminal for SPI interface.InputCLK40 Chip-enable terminal for SPI1 interface. ("H" active )InputCE41 Interrupt output terminal.OutputINT42 LDO2 ( 2.85 V ) output terminal.OutputLDO243 DescriptionTypePin namePin No. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

G B DO DI CLK CE INT LDO2 R VLED2 IREF HTSD ON/OFF Level shift Pattern register RAMRegister ON/OFF STANDBY ON/OFF Constant current control (7-ch) PWM control (7-ch) ON/OFF N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. LDO2

2.85 V/30 mA

(7-ch)Level shift BGR TSD LDO1

1.85 V/30 mA

Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

The signal from serial interface is not received in LDOCNT = Low and the state of REG28 = Low or REG18 = Low.
It shifts to standby mode with LDOCNT = Low and REG28 = High.
The signal from serial interface is not received at Standby-mode. (Power supply for Logic is LDO1 and LDO2.) Therefore, standby release by the signal from serial interface cannot be performed.
In Standby-mode, if LDOCNT is switched to High from Low, it will return to the normal mode.
It cannot shift to OFF-mode from Standby-mode. Once returning to the normal mode, please shift to OFF-mode. REG28
Regardless of the value of REG18, LDO1 turns on at LDOCNT = High.
Regardless of the value of REG28, LDO2 turns on at LDOCNT = High.
Serial interface signal is not received at RSTB = Low
5 ms after being set to LDOCNT = High, the receptionist of serial interface signal is attained.
RSTB terminal prohibits the input signal of those other than a rectangle wave.
All register setting become default setting if RSTB = Low
(The default setting of REG18 and REG28 are [1]
If RSTB = Low before LDOCNT = Low, LDO1 and LDO2 can’t turn off. )
All register setting become default setting when LDO2 turn off.
The setting order to change off mode is as following.
REG18, 28 = [0] → LDOCNT = "L" → RSTB = "L" 0/1"H"
It is necessary to make it LDOCNT = High for the return from OFF-mode.0Low NoteREG18LDOCNT OPERATION 1. Explanation in each mode (Power supply starting sequence) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

It is a waveform in the case of applying reset to register setup at Standby mode. * Maintain the state of RSTB = High to hold the register setup.
Shift to the Normal mode from Standby mode Low power mode LDOCNT LDO1 LDO2 A register input is possible.Over 5 ms RSTB* over 3 ms REG18 [Address : 02h] REG28 [Address : 02h] LDOCNT LDO1 LDO2 REG18 [Address : 02h] REG28 [Address : 02h] A register input is possible.Over 5 ms RSTB Over 3 ms
Shift to the Normal mode from OFF-mode OPERATION (continued) 1. Explanation in each mode (Power supply starting sequence) (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

Set REG18 and REG28 to Low before LDOCNT. Over 1 ms REG18 [Address : 02h] REG28 [Address : 02h] RSTB A register input is possible. Over 3ms

Shift to the OFF-mode from Normal mode Low power mode Set REG18 to Low before LDOCNT. LDOCNT LDO1 LDO2 A register input is possible. Over 1 ms REG18 [Address : 02h] REG28 [Address : 02h] RSTB
Shift to the Standby mode from Normal mode OPERATION (continued) 1. Explanation in each mode (Power supply starting sequence) (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

"H" "H" "L" "L" VBAT Prohibition"H" ON"H" OFF"L" OFF"L" MODELDOCNT Note) "L" in column of VBAT and LDOCNT means 0 V, "H" means 3.1 to 4.6 V ( operating supply voltage range ).

Logic pin condition Note)*: Logic state for pins indicated as “Output” under Pin state shows the output level. Logic state for pins indicated as “Input” under Pin state shows the input level to be set to the pins. Depends on each modeInputLDOCNT "L"InputLEDCTL "L"OutputDO "L"InputDI "L"InputCLK "L"InputCE "L"OutputINT Logic*Pin statePin name The following setting is common for OFF, Standby and Normal mode. The pin setting when RSTB = Low, under Normal mode is as follows.
Shift to the OFF-mode from Normal mode OPERATION (continued) 1. Explanation in each mode (Power supply starting sequence) (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

The following waveform is an internal signal. In following Yx = Xx = Low, the waveform of actual Yx terminal is set to Hi-Z.
It is controlled by internal 1.2 MHz clock in default condition.
Y side switches from Y0 to Y6 in that order. The turning on term of each pin is constant 945clock (787.5 s) and each turning on term includes 8clock (6.67 s) interval.
"*" mark shows the turning on term and D3, D6 is the turning off term in the following figure.
7 7 matrix display is controlled by X0 to X6 with Yx switching timing. X0 to X6 6671clk (About 180.83 Hz) 8clk (6.67 s) 945clk (787.5 s) PWM Minimum width 63clk (52.5 s) D0 D1 D2 D3 D4 D5 D6 D0
Matrix part operation waveform OPERATION (continued) 2. Explanation of operation Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

All the logic portions to which the power supply is not connected are connected to VB as power supplies. REG28 BGR VBATT TSD LDOCNT VB CE CLK DI DO LEVEL SHIFT Register RST RSTB LDO2 2.85 V 1 F 1 F LDO2 LDO1 LDO1 1.85 V REG18 LEVEL SHIFT ON/OFF ON/OFF STANDBY ON/OFF HTSDON/OFF 1 F VREFD LEVEL SHIFT LDO1 LDO2LDO1 LDO2 LDO2 VBLDO2

RESET part block configuration OPERATION (continued) 3. Block configuration Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

LED’s number LED‘s number

LED matrix driver circuit can display character and pattern by controlling the 77 matrix LED individually.
In this specification, LED’s number controlled by each terminal can be matched off against the following figure.
It is controlled by internal 1.2 MHz clock in default condition.
In the scroll mode, LED matrix can move the display of character from right to left as the following arrangement.
Explanation of matrix LED part, matrix LED’s number OPERATION (continued) 3. Block configuration (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

V(IREF) = 0.54 V R(IREF) = 27 k 20 A VLED Ibl1 Panasonic ERJ2RHD273X Q1 Q2 1.24 V VB 245 k 187 k X0 terminal case

The reference current for constant current driver is calculated by the following formula. V(IREF) / R(IREF) = 0.54 V / 27 k = 20 A
The LED driver current can be set from 0 mA to 30 mA by register setting via serial interface.
The constant current value can be changed by the external resistor value of IREF terminal, but the accuracy in case of that setting is not guaranteed.
ERJ2RHD273X is recommended for the external resistor of IREF terminal to keep the constant current accuracy.
Equivalent circuit of matrix LED driver OPERATION (continued) 3. Block configuration (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

Register Map OPERATION (continued) 4. Register and Address For test TSDCPUWRERFRMINTRAM ACT———FACGD1IOFACTORR14h —DISRGBDISMTX————LEDACTLEDCTLW0Ah W/R For test For test For test For test For test For test For test For test For test For test For test For test For test For test For test W W R/W ——— 08h 18h 17h 16h 15h ————INTVSELVDDSEL1Ah 19h 10h 09h 07h 06h 05h 04h 03h Data nameSub address 13h 12h 11h D5D6D7 Data D0D1D2D3D4 Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

Access the address from 6Bh to 77h is prohibited. For test6Bh For test6Dh For test6Fh For test2Eh RAMNUM RGBDATA[5:0]RGBDATAR/W2Dh For test2Bh SETTIME[1:0]SETTIMER/W28h REPON  SETTO[7:0]SETTOR/W26h For test75h For test70h For test71h For test72h For test73h For test74h For test76h For test R/W R/W R/W R/W R/W R/W R/W R/W 77h SETFROM[7:0]SETFROM25h REPON27h COPYSTARTSELRAMRAMCOPY24h SELROM[7:0]ROMSEL23h Data NameSub Address MTXDATA[7:0]MTXDATA21h D5D6D7 DATA D0D1D2D3D4
Register Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DLA1[1:0]FRA1[1:0]BLA1[3:0]A131h DLA2[1:0]FRA2[1:0]BLA2[3:0]A232h DLA3[1:0]FRA3[1:0]BLA3[3:0]A333h DLA4[1:0]FRA4[1:0]BLA4[3:0]A434h DLA5[1:0]FRA5[1:0]BLA5[3:0]A535h DLA6[1:0]FRA6[1:0]BLA6[3:0]A636h DLA7[1:0]FRA7[1:0]BLA7[3:0]A737h DLB1[1:0]FRB1[1:0]BLB1[3:0]B138h DLB2[1:0]FRB2[1:0]BLB2[3:0]B239h DLB3[1:0]FRB3[1:0]BLB3[3:0]B33Ah DLB4[1:0]FRB4[1:0]BLB4[3:0]B43Bh DLB5[1:0]FRB5[1:0]BLB5[3:0]B53Ch DLB6[1:0]FRB6[1:0]BLB6[3:0]B63Dh DLB7[1:0]FRB7[1:0]BLB7[3:0]B73Eh DLC1[1:0]FRC1[1:0]BLC1[3:0]C13Fh DLC2[1:0]FRC2[1:0]BLC2[3:0]C240h DLC3[1:0]FRC3[1:0]BLC3[3:0]C341h DLC4[1:0]FRC4[1:0]BLC4[3:0]C442h DLC5[1:0]FRC5[1:0]BLC5[3:0]C543h DLC6[1:0]FRC6[1:0]BLC6[3:0]C644h DLC7[1:0]FRC7[1:0]BLC7[3:0]C745h DLD1[1:0]FRD1[1:0]BLD1[3:0]D146h DLD2[1:0]FRD2[1:0]BLD2[3:0]D247h DLD3[1:0]FRD3[1:0]BLD3[3:0]D348h DLD4[1:0]FRD4[1:0]BLD4[3:0]D449h DLD5[1:0]FRD5[1:0]BLD5[3:0]D54Ah DLD6[1:0]FRD6[1:0]BLD6[3:0]D64Bh DLD7[1:0]FRD7[1:0]BLD7[3:0]D74Ch Data NameSub Address D5D6D7 DATA D0D1D2D3D4 OPERATION (continued) 4. Register and Address (continued) RAM address map Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DLG7[1:0]FRG7[1:0]BLG7[3:0]G761h DLLEDB[1:0] DLLEDG[1:0] DLLEDR[1:0] FRLEDB[1:0] FRLEDG[1:0] FRLEDR[1:0]BLLEDR[3:0]LEDR62h BLLEDG[3:0]LEDG63h BLLEDB[3:0]LEDB64h DLE1[1:0]FRE1[1:0]BLE1[3:0]E14Dh DLE2[1:0]FRE2[1:0]BLE2[3:0]E24Eh DLE3[1:0]FRE3[1:0]BLE3[3:0]E34Fh DLE4[1:0]FRE4[1:0]BLE4[3:0]E450h DLE5[1:0]FRE5[1:0]BLE5[3:0]E551h DLE6[1:0]FRE6[1:0]BLE6[3:0]E652h DLE7[1:0]FRE7[1:0]BLE7[3:0]E753h DLF1[1:0]FRF1[1:0]BLF1[3:0]F154h DLF2[1:0]FRF2[1:0]BLF2[3:0]F255h DLF3[1:0]FRF3[1:0]BLF3[3:0]F356h DLF4[1:0]FRF4[1:0]BLF4[3:0]F457h DLF5[1:0]FRF5[1:0]BLF5[3:0]F558h DLF6[1:0]FRF6[1:0]BLF6[3:0]F659h DLF7[1:0]FRF7[1:0]BLF7[3:0]F75Ah DLG1[1:0]FRG1[1:0]BLG1[3:0]G15Bh DLG2[1:0]FRG2[1:0]BLG2[3:0]G25Ch DLG3[1:0]FRG3[1:0]BLG3[3:0]G35Dh DLG4[1:0]FRG4[1:0]BLG4[3:0]G45Eh DLG5[1:0]FRG5[1:0]BLG5[3:0]G55Fh DLG6[1:0]FRG6[1:0]BLG6[3:0]G660h Data NameSub Address D5D6D7 DATA D0D1D2D3D4 OPERATION (continued) 4. Register and Address (continued) RAM address map (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DisplayContents of the patternPattern No. TAlphabetic character30 SAlphabetic character29 NothingAll putting out lights0 RAlphabetic character28 QAlphabetic character27 PAlphabetic character26 OAlphabetic character25 NAlphabetic character24 MAlphabetic character23 LAlphabetic character22 KAlphabetic character21 JAlphabetic character20 IAlphabetic character19 HAlphabetic character18 GAlphabetic character17 FAlphabetic character16 EAlphabetic character15 DAlphabetic character14 CAlphabetic character13 BAlphabetic character12 AAlphabetic character11 9Number10 8Number9 7Number8 6Number7 5Number6 4Number5 3Number4 2Number3 1Number2 0Number1 [00000000] - [10010101] : ROM(Only luminosity) 7  7 Pattern No.0 (default) to Pattern No.149 DisplayContents of the patternPattern No. wAlphabetic character59 xAlphabetic character60 yAlphabetic character61 vAlphabetic character58 uAlphabetic character57 tAlphabetic character56 sAlphabetic character55 rAlphabetic character54 qAlphabetic character53 pAlphabetic character52 oAlphabetic character51 nAlphabetic character50 mAlphabetic character49 lAlphabetic character48 kAlphabetic character47 jAlphabetic character46 iAlphabetic character45 hAlphabetic character44 gAlphabetic character43 fAlphabetic character42 eAlphabetic character41 dAlphabetic character40 cAlphabetic character39 bAlphabetic character38 aAlphabetic character37 ZAlphabetic character36 YAlphabetic character35 XAlphabetic character34 WAlphabetic character33 VAlphabetic character32 UAlphabetic character31

ROM Address Map OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DisplayContents of the patternPattern No. 29Number92 28Number91 zAlphabetic character62 27Number90 26Number89 25Number88 24Number87 23Number86 22Number85 21Number84 20Number83 19Number82 18Number81 17Number80 16Number79 15Number78 14Number77 13Number76 12Number75 11Number74 10Number73 09Number72 08Number71 07Number70 06Number69 05Number68 04Number67 03Number66 02Number65 01Number64 00Number63 DisplayContents of the patternPattern No. 58Number121 59Number122 60Number123 57Number120 56Number119 55Number118 54Number117 53Number116 52Number115 51Number114 50Number113 49Number112 48Number111 47Number110 46Number109 45Number108 44Number107 43Number106 42Number105 41Number104 40Number103 39Number102 38Number101 37Number100 36Number99 35Number98 34Number97 33Number96 32Number95 31Number94 30Number93 [00000000] - [10010101] : ROM(Only luminosity) 77 Pattern No.0 (defaul t) to Pattern No.149

ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DisplayContents of the patternPattern No. Symbol144 Symbol145 Symbol146 Symbol147 Symbol148 Symbol149 DisplayContents of the patternPattern No. Zero antennaSymbol124 Symbol143 /Symbol142 -Symbol141 +Symbol140 →Symbol139 ←Symbol138 Symbol137 Symbol136 ?Symbol135 !Symbol134 :Symbol133 <<Symbol132 >>Symbol131 ||Symbol130 Symbol129 Symbol128 Three antennaSymbol127 Two antennaSymbol126 One antennaSymbol125 [00000000] - [10010101] : ROM(Only luminosity) 77 Pattern No.0 (defaul t) to Pattern No.149

ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

[10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7  7 Pattern No.150 to Pattern No.208 DisplayContents of the patternPattern No. Gradation150 Gradation158 Gradation157 Gradation156 Gradation155 Gradation154 Gradation153 Gradation152 Gradation151 DisplayContents of the patternPattern No. Gradation159 Gradation160 Gradation161 Gradation162 Gradation163 Gradation164 Gradation165 Gradation166 Gradation167

ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DisplayContents of the patternPattern No. Gradation177 Gradation178 Gradation179 Gradation180 Gradation181 Gradation182 Gradation183 Gradation184 Gradation185 [10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7  7 Pattern No.150 to Pattern No.208 DisplayContents of the patternPattern No. Gradation168 Gradation176 Gradation175 Gradation174 Gradation173 Gradation172 Gradation171 Gradation170 Gradation169

ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DisplayContents of the patternPattern No. Gradation195 Gradation196 Gradation197 Gradation198 Gradation199 Gradation200 Gradation201 Gradation202 Gradation203 [10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7  7 Pattern No.150 to Pattern No.208 DisplayContents of the patternPattern No. Gradation186 Gradation194 Gradation193 Gradation192 Gradation191 Gradation190 Gradation189 Gradation188 Gradation187

ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

[10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7  7 Pattern No.150 to Pattern No.208 DisplayContents of the patternPattern No. Gradation204 Gradation208 Gradation207 Gradation206 Gradation205

ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

RGBDATA[5:0]——RGBDATAR/W2Dh SCLTIME[1:0]——————SCLTIMER/W2Bh SETTIME[1:0]——————SETTIMER/W28h SETTO[7:0]SETTOR/W26h SETFROM[7:0]SETFROMR/W25h COPY STARTSELRAM——————RAMCOPYR/W24h SELROM[7:0]ROMSELR/W23h MTXDATA[7:0]MTXDATAR/W21h TSDCPU WRERFRMINTRAM ACT———FACG D1IOFACTORR14h W R/W Data NameSub Address D5D6D7 DATA D0D1D2D3D4 About the following addresses, even if an internal clock or an external clock does not exist, Read / Write is possible in the data to register. However, it cannot be given to operation finally needed.

Register table which needs a clock OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DLA1[1:0]FRA1[1:0]BLA1[3:0]A131h DLA2[1:0]FRA2[1:0]BLA2[3:0]A232h DLA3[1:0]FRA3[1:0]BLA3[3:0]A333h DLA4[1:0]FRA4[1:0]BLA4[3:0]A434h DLA5[1:0]FRA5[1:0]BLA5[3:0]A535h DLA6[1:0]FRA6[1:0]BLA6[3:0]A636h DLA7[1:0]FRA7[1:0]BLA7[3:0]A737h DLB1[1:0]FRB1[1:0]BLB1[3:0]B138h DLB2[1:0]FRB2[1:0]BLB2[3:0]B239h DLB3[1:0]FRB3[1:0]BLB3[3:0]B33Ah DLB4[1:0]FRB4[1:0]BLB4[3:0]B43Bh DLB5[1:0]FRB5[1:0]BLB5[3:0]B53Ch DLB6[1:0]FRB6[1:0]BLB6[3:0]B63Dh DLB7[1:0]FRB7[1:0]BLB7[3:0]B73Eh DLC1[1:0]FRC1[1:0]BLC1[3:0]C13Fh DLC2[1:0]FRC2[1:0]BLC2[3:0]C240h DLC3[1:0]FRC3[1:0]BLC3[3:0]C341h DLC4[1:0]FRC4[1:0]BLC4[3:0]C442h DLC5[1:0]FRC5[1:0]BLC5[3:0]C543h DLC6[1:0]FRC6[1:0]BLC6[3:0]C644h DLC7[1:0]FRC7[1:0]BLC7[3:0]C745h DLD1[1:0]FRD1[1:0]BLD1[3:0]D146h DLD2[1:0]FRD2[1:0]BLD2[3:0]D247h DLD3[1:0]FRD3[1:0]BLD3[3:0]D348h DLD4[1:0]FRD4[1:0]BLD4[3:0]D449h DLD5[1:0]FRD5[1:0]BLD5[3:0]D54Ah DLD6[1:0]FRD6[1:0]BLD6[3:0]D64Bh DLD7[1:0]FRD7[1:0]BLD7[3:0]D74Ch Data NameSub Address D5D6D7 DATA D0D1D2D3D4 About the following addresses, when an internal clock or an external clock does not exist, data cannot be Read / Write in at register.

Register table which needs a clock (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DLG7[1:0]FRG7[1:0]BLG7[3:0]G761h DLLEDB[1:0] DLLEDG[1:0] DLLEDR[1:0] FRLEDB[1:0] FRLEDG[1:0] FRLEDR[1:0]BLLEDR[3:0]LEDR62h BLLEDG[3:0]LEDG63h BLLEDB[3:0]LEDB64h DLE1[1:0]FRE1[1:0]BLE1[3:0]E14Dh DLE2[1:0]FRE2[1:0]BLE2[3:0]E24Eh DLE3[1:0]FRE3[1:0]BLE3[3:0]E34Fh DLE4[1:0]FRE4[1:0]BLE4[3:0]E450h DLE5[1:0]FRE5[1:0]BLE5[3:0]E551h DLE6[1:0]FRE6[1:0]BLE6[3:0]E652h DLE7[1:0]FRE7[1:0]BLE7[3:0]E753h DLF1[1:0]FRF1[1:0]BLF1[3:0]F154h DLF2[1:0]FRF2[1:0]BLF2[3:0]F255h DLF3[1:0]FRF3[1:0]BLF3[3:0]F356h DLF4[1:0]FRF4[1:0]BLF4[3:0]F457h DLF5[1:0]FRF5[1:0]BLF5[3:0]F558h DLF6[1:0]FRF6[1:0]BLF6[3:0]F659h DLF7[1:0]FRF7[1:0]BLF7[3:0]F75Ah DLG1[1:0]FRG1[1:0]BLG1[3:0]G15Bh DLG2[1:0]FRG2[1:0]BLG2[3:0]G25Ch DLG3[1:0]FRG3[1:0]BLG3[3:0]G35Dh DLG4[1:0]FRG4[1:0]BLG4[3:0]G45Eh DLG5[1:0]FRG5[1:0]BLG5[3:0]G55Fh DLG6[1:0]FRG6[1:0]BLG6[3:0]G660h Data NameSub Address D5D6D7 DATA D0D1D2D3D4 About the following addresses, when an internal clock or an external clock does not exist, data cannot be Read / Write in at register.

Register table which needs a clock (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

——— OSCEN— Default ———Data Name 01h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D2 : OSCEN ON/OFF bit for internal oscillators [0] : Internal oscillating circuit is OFF (default) [1] : Internal oscillating circuit is ON  The variation width of an internal oscillator is set to 0.96MHz - 1.44 MHz.  The variation width of an internal clock is set to 694.4 ns - 1042 ns. REG28———— Default REG18——Data Name 02h W W W DATA mode Sub Address WWWWW 11000 D0D1D2D3D4 D1 : REG18 The ON/OFF control for LDO1(When LDOCNT terminal is Low) [0] : LDO1 OFF [1] : LDO1 ON (default) D0 : REG28 The ON/OFF control for LDO2( When LDOCNT terminal is Low ) [0] : LDO2 OFF [1] : LDO2 ON (default)  When LDOCNT terminal is High, regardless of the state of REG18, LDO1 will be activated.  When LDOCNT terminal is High, regardless of the state of REG28, LDO2 will be activated.  Set LDOCNT to Low after setting REG28 to Low to put into OFF mode.

Register map detailed explanation OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 Default For testData Name 04h R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 Default For testData Name 05h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 Default For testData Name 06h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 Default For testData Name 07h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 *Don’t access to address from 03h to 07h.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 *Don’t access to address from 08h to 09h. Default For testData Name 09h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 Default LEDACTData Name 0Ah W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D7 : LEDACT A putting-out-lights setup of LED by LEDCTL terminal. [0] : The light is switched on at LEDCTL = Low(default) [1] : The light is switched on at LEDCTL = High D2 : DISMTX A putting-out-lights ON/OFF setup of 7  7 dots matrix LED by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D1 : DISRGB A putting-out-lights ON/OFF setup of R, G and B terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

*Don’t access to address from 10h to 13h.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

TSDCPUWRERFRMINTRAMACT——— Default FACGD1Data Name 14h R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 D7 : FACGD1 [0] : Normal operation (default) [1] : No read clearance D3 : RAMACT Internal RAM access judgment [0] : RAM is not accessed. (default) [1] : RAM is accessed. D2 : FRMINT Frame display end judgment during scroll display [0] : Under frame display (default) [1] : Frame display end D1 : CPUWRER CPU access error judgment [0] : CPU access error does not occur. (default) [1] : CPU access error occurs. D0 : TSD Abnormal detection of TSD error [0] : TSD abnormal detection does not occur. (default) [1] : TSD abnormal detection occurs.

CPUWRER indicates the error when CPU writes the data to 31h to 64h during copying from ROM to RAM1 or RAM2.
The WRITE contents from CPU are not reflected in this LSI at CPUWRER = High. Write from CPU again.
The interval of FACGD1 = "1" is maximum 1.93 s (at the internal clock operation) from the renewal time of data.
At FACGD1 = "1", if address 14h data is read, data of D0 to D6 are cleared.
RAM access from CPU cannot be performed at RAMACT = "1" .
When each address 14h register is set to High, the pulse in a cycle of 4 ms is output from INT.
The pulse output from INT continues an output until address 14h is read.
RSTB terminal = Low can reset to stop the INT pulse signal in case of that the serial read function is not used.
The states for RAMACT = "1" are shown below. 1. While copying to RAM from ROM. 2. While clearing RAM
Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 Default For testData Name 16h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 Default For testData Name 17h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 Default For testData Name 18h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 Default For testData Name 19h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 *Don’t access to address from 15h to 19h.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

D7 : INTVSEL The voltage setup of INT terminal [0] : 1.85 V (default) [1] : 2.85 V

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—Data Name 20h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : MTXON ON/OFF setup of matrix LED [0] : OFF (default) [1] : ON

During MTXON = "1", subsequent ROM, RAM, and the control contents to a register are sequentially processed and lit up.
Wait 5 ms when MTXON is set to "1" after address 01h OSCEN is set to "1".
Set MTXON to "1", and then set up other addresses to display the matrix part. Default MTXDATA[7:0]Data Name 21h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : MTXDATA[7:0] Address setup of ROM/RAM of the data to read [00000000] - [10010101] : ROM ( Only luminosity ) 77 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM ( Luminosity + Cycle + Delay ) 77 pattern No. 150 to No.208 [11010001] : RAM ( Luminosity + Cycle + Delay ) 77 pattern RAM No.1 [11010010] : RAM ( Luminosity + Cycle + Delay ) 77 pattern RAM No.2  The pattern No.0 of ROM is all "0" data of matrix LED.  Accessing to 21h is disabled while copying from ROM to RAM (COPYSTART 24h = "1").
Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—Data Name 22h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : ROM77[1:0] Lighting control of the 77 (LED No.A1-G7) fixed pattern of ROM [00] : ROM data is displayed. [01] : ROM data is displayed by firefly lighting in 1 s. [10] : ROM data is displayed by firefly lighting in 2 s. [11] : ROM data is displayed by firefly lighting in 3 s  During display of repetition (REPON = "1"), ROM77 must not be changed. A B C D EFG t t1 t3 t2 t4 t1 = t2 = t4 = 249.2 ms t3 = 265.8 ms The peak value of luminosity is a value set up by ROM. Luminosity Firefly lighting cycle : T LED’s number LED’s number

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

SELROM[7:0]Data Name 23h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : SELROM[7:0] Address setup of ROM copied to RAM [00000000] - [10010101] : ROM (Only luminosity) 77 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity + Cycle + Delay) 77 pattern No.150 to No.208  Accessing to 23h is disabled while copying from ROM to RAM (COPYSTART 24h = "1"). Default —Data Name 24h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1 : SELRAM RAM number setup of a copy place. [0] : RAM No.1 [1] : RAM No.2 D0 : COPYSTART Copy start ON/OFF control to RAM from ROM [0] : OFF [1] : The copy set up by SELROM and SELRAM is started. (It returns to 0 by internal 51 CLK.)  Address 24h is only for copying data to RAM and never start LED display. (However, if this RAM is copied when LED display is showing, LED display is updated.)  Writing in address 21h-MTXDATA, 2Ah-SCLON, and 27h-REPON is disabled while copying. (RAMACT flag is raised.)  Accessing to SELRAM is disabled while copying from ROM to RAM (COPYSTART 24h = "1")  Don’t write address 29h (RAM-clear ) while copying. (The waiting time for over 1 ms is required after COPYSTART.)

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

SETFROM[7:0]Data Name 25h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : SETFROM[7:0] An address setup of the ROM frame data at the repetition display start. [00000000] - [10010101] : ROM (Only luminosity) 77 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity + Cycle + Delay) 77 pattern No.150 to No.208  During display of repetition (REPON = "1"), Don’t change the setting of SETFROM. Default SETTO[7:0]Data Name 26h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : SETTO[7:0] Address setup of the ROM frame data at the repetition display end [00000000] - [10010101] : ROM (Only luminosity) 77 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity + Cycle + Delay) 77 pattern No.150 to No.208  During display of repetition (REPON = "1"), don’t change the setting of SETTO.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—Data Name 27h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : REPON Repetition display ON/OFF control [0] : Repetition display OFF (default) [1] : Repetition display ON  During display of repetition, display of set-up ROM is continued.  A repetition display is started in the state of MTXON = "1" and REPON = "1".  Accessing to 27h is disabled while copying from ROM to RAM (COPYSTART 24h = "1").  When the setting of SCLON is changed from Low to High while REPON = "1", REPON becomes "0" and it shifts to scroll function.  During display of repetition (REPON = "1"), don’t change the setting of SETFROM and SETTO. Default —Data Name 28h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : SETTIME[1:0] A frame display time setup of repetition display [00] : 1 s (default) [01] : 2 s [10] : 3 s [11] : 4 s

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—Data Name 29h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1 : RAM1 The data in 77 RAM1 is cleared. 0 : Overwrite is possible. (default) 1 : The data in 77 RAM1 is cleared. (It returns to 0 by internal 2 CLK.) D0 : RAM2 The data in 77 RAM2 is cleared. 0 : Overwrite is possible. (default) 1 : The data in 77 RAM2 is cleared. (It returns to 0 by internal 2 CLK.)  Don’t set the RAM-clear operation for RAM1 or RAM2 during display of repetition (SCLON = "1").  Don’t set the RAM-clear operation (29h) during the COPY operation (24h). (The waiting time for over 1 ms is required after COPYSTART.)

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—Data Name 2Ah W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : SCLON ON/OFF setup of scroll display [0] : OFF (default) [1] : ON

The scroll display displays the data which exists in the RAM No.1-2 of 77 in order of A-G column. The display travel time of a column is the preset value of SCLTIME.
During display of scroll, data can be written to RAM without specifying RAM number. (Writing is performed to empty RAM.)
The scroll display is started in the state of MTXON = "1" and SCLON.
Accessing to 2Ah is disabled while copying from ROM to RAM (COPYSTART 24h = "1").
When the setting of REPON is changed from "0" to "1" while SCLON = "1", SCLON becomes "0" and it shifts to repetition display function.
During display of scroll (SCLON = "1"), don’t change the setting of RAM1 and RAM2.
Once the scroll function was set, then the SCLON = "0" or MTXON = "0", RSTB terminal must be "L" to reset before the scroll function is set again. Default —Data Name 2Bh W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : SCLTIME[1:0] Frame display time setup of scroll display [00] : 0.1 s (default) [01] : 0.2 s [10] : 0.4 s [11] : 0.8 s  The display travel time of the column is the preset value of SCLTIME.
Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—Data Name 2Ch W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : RGBON ON/OFF setup of RGB lighting [0] : OFF (default) [1] : ON  Wait 5 ms when RGBON is set to "1" after address 01h OSCEN is set to "1". RGBDATA[5:0]— Default —Data Name 2Dh W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : RGBDATA[5:0] Address setup of ROM and register which read RGB data [000000] : Register is displayed. [000001] - [101010] : ROM (RGB pattern, Luminosity + Cycle + Delay) pattern No.1 to No.42 Default For testData Name 2Eh R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 *Don’t access to address 2Eh.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

—Data Name 30h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : RAMNUM[1:0] RAM number setup at the CPU access (READ and WRITE). [0] : RAM No.1 [1] : RAM No.2  Accessing to 30h is disabled during display of scroll (2Ah SCLON = "1").

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DLA1[1:0]FRA1[1:0] Default BLA1[3:0]Data Name 31h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-4 : BLA1[1:0] Luminosity setup of LED No.A1 [0000] : 0 mA (default) [0001] : 1 mA [0010] : 2 mA [0011] : 3 mA [0100] : 4 mA [0101] : 5 mA [0110] : 8 mA [0111] : 11 mA [1000] : 15 mA [1001] : 17 mA [1010] : 19 mA [1011] : 21 mA [1100] : 24 mA [1101] : 26 mA [1110] : 28 mA [1111] : 30 mA D3-2 : FRA1[1:0] Firefly operation and cycle setup of the LED No.A1 [00] : Lighting mode (default) [01] : Firefly lighting cycle 1 s [10] : Firefly lighting cycle 2 s [11] : Firefly lighting cycle 3 s D1-0 : DLA1[1:0] Firefly operation delay setup of the LED No.A1 [00] : No delay (default) [01] : Delay 25% [10] : Delay 50% [11] : Delay 75%

The operation is the same as above for the addresses to 61h corresponding to each LED number.
The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 31h to 61h is written in. Please input other serial commands after that. A B C D EFG LED‘s number 7LED‘s number
Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DLLEDR[1:0]FRLEDR[1:0] Default BLLEDR[3:0]Data Name 62h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-4 : BLLEDR1[1:0] Luminosity setup of R1 terminal [0000] : 0 mA (default) [0001] : 1 mA [0010] : 2 mA [1110] : 14 mA [1111] : 15 mA D3-2 : FRLEDR1[1:0] Firefly operation and cycle setup of R1 terminal [00] : Lighting mode (default) [01] : Firefly lighting cycle 1 s [10] : Firefly lighting cycle 2 s [11] : Firefly lighting cycle 3 s D1-0 : DLLEDR1[1:0] Firefly operation delay setup of R1 terminal [00] : No delay (default) [01] : Delay 25% [10] : Delay 50% [11] : Delay 75%  The operation is the same as above for the addresses to 64h corresponding to G and B terminal.  The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 62h to 64h is written in. Please input other serial commands after that.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

*Address from 6Bh onwards are registers for test. Don't write into these addresses.

Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

The interface with microcomputer consists of 16 bit-serial register (8-bit of command, 8-bit of address), and address decoder and transmitting register (8-bit).
Serial interface consists of four terminals of serial clock terminal (CLK), serial-data input terminal (DI), serial-data output terminal (DO), and chip enable input terminal (CE). (1) Write operation
Data is taken into internal shift register by the rising edge of CLK. (Maximum 13 MHz of frequency of CLK can be used)
Serial interface consists of four terminals of serial clock terminal (CLK), serial-data input terminal (DI), serial- data output terminal (DO), and chip enable input terminal (CE).
Data is transmitted at MSB first in order of a control register address (8-bit) and control command (8-bit). CLK DI W D0D1D2D3D4D5D6D7A0A1A2A3A4A5A6 CE DO 0 Write access Timing (2) Transmission operation
Data is taken into internal shift register by the rising edge of CLK. (A maximum of 6 MHz of frequency of CLK can be used)
It is not possible to read RAM data.
In High interval of CE, reception of data becomes ENABLE. (active : High)
Data is transmitted at MSB first in order of a control register address (8-bit) and control command (max 8-bit). Read access Timing CLK DO CE DI D0D1D2D3D4D5D6D7 RA 0 A1A2A3A4A5A6 0 0
SPI format OPERATION (continued) 5. Serial interface format Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

LOGICI/O*BGR TSD VLED1 VLED2 AGND PGND RGBGND OSC MTX RGB SCAN *CLK, CE, DI, DO, LEDCTL

Power supply distribution diagram OPERATION (continued) 6. Signal distribution diagram Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

Oscillator 1.2 MHz REGMAP Matrix RGB * Matrix, RGB operation PWM control Read / Write of memory data (ROM and RAM) 14h RAMACT, FRMINT, CPUWRER SPI (PAD) CLK (PAD) CE (PAD) DI (PAD) DO * Serial  Parallel conversion SCLK Serial  Parallel conversion (input) SCLK_N Parallel  Serial conversion (output) REGCLK Serial  Parallel conversion output is latched in a standup. SCLK SCLK_N REGCLK

Control / Clock distribution diagram OPERATION (continued) 6. Signal distribution diagram (continued) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

DLA1[1:0]FRA1[1:0]BLA1[3:0] 000000 01 Example of initial setting for lighting DLA1[1:0]FRA1[1:0]BLA1[3:0] 011110 01 Firefly lighting setup 1 s DLA1[1:0]FRA1[1:0]BLA1[3:0] 001110 11 Change to cycle 1 s to 2 s DLA1[1:0]FRA1[1:0]BLA1[3:0] 101110 11 Change to delay 0  25 % 30 mA t Firefly lighting cycle T2 = 2.0268 s FRA1 = [10] DLA1 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms Current value Serial ON 15 mA t Firefly lighting cycle T = 1.0134 s FRA1 = [01] Current value 30 mA Serial ON t Firefly lighting cycle T2 = 2.0268 s FRA1 = [10] Current value BLA1 = [1000] BLA1 = [1111] t 30 mA Current value BLA1 = [1111] BLA1 = [1111] Serial ON Serial ON

Example of firefly lighting 1 OPERATION (continued) 7. Example of firefly lighting Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

Example of firefly lighting 2 OPERATION (continued) 7. Example of firefly lighting (continued) t Luminance Firefly lighting cycle T1 = 3.040 2 s FRA1 = [11] t1 t3t2 t4 t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms BLA1A1 t Luminance Firefly lighting cycle T2 = 2.026 8 s FRC5 = [10] BLC5C5 t Luminance Firefly lighting cycle T3 = 1.013 4 s FRF3 = [01] t9 = t10 = t12 = 249.2 ms t11 = 265.8 ms BLF3 DLC5 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms DLF3 = [10] t10 t11 t12 t Luminance Firefly lighting cycle T1 = 3.040 2 s FRE7 = [11] t1 t3t2 t4 BLE7E7 DLE7 = [11] t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms 1. Normally, it is not possible to control data when RGBGND pin voltage is undefined. Therefore, please keep the RGBGND pin voltage at the lowest voltage. 2. Please check the input waveform to the CLK pin. When inputting clock into the CLK pin, if the input clock is ringing with input voltage between 0.4 V to LDO1  0.8 V (input voltage indefinite range), it will result in serial data not able to be written to or be read out from a register. (It is recommended to smooth the rising and falling edge of the input clock by connecting input capacitance (a capacitor, etc.) to the CLK pin.) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

PACKAGE INFORMATION ( Reference Data ) Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

When using the LSI for new models, verify the safety including the long-term reliability for each product. 2. When the application system is designed by using this LSI, please confirm the notes in this book. Please read the notes to descriptions and the usage notes in the book. 3. This LSI is intended to be used for general electronic equipment. Consult our sales staff in advance for information on the following applications: Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this LSI may directly j eopardize life or harm the human body. Any applications other than the standard applications intended. (1) Space appliance (such as artificial satellite, and rocket) (2) Traffic control equipment (such as for automobile, airplane, train, and ship) (3) Medical equipment for life support (4) Submarine transponder (5) Control equipment for power plant (6) Disaster prevention and security device (7) Weapon (8) Others : Applications of which reliability equivalent to (1) to (7) is required Our company shall not be held responsible for any damage incurred as a result of or in connection with the LSI being used for any special application, unless our company agrees to the use of such special application. 4. This LSI is neither designed nor intended for use in automotive applications or environments unless the speci fic product is designated by our company as compliant with the ISO/TS 16949 requirements. Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in connection with the LSI being used in automotive application, unless our company agrees to such application in this book. 5. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of control led substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage incurred as a result of our LSI being used by our customers, not complying with the applicable laws and regulations. 6. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it migh t emit smoke or ignite. 7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins . In addition, refer to the Pin Description for the pin configuration. 8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as solder-bridge between the pins of the semiconductor device. Also, perform full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 9. Take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short). Safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not w ork during normal operation. Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be damaged before the thermal protection circuit could operate. 11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical p ick-up is being driven. 12. Verify the risks which might be caused by the malfunctions of external com ponents. Doc No. TA4-EA-04725 Revision. Established 2007-05-24 Revised 2013-04-15

Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) The products and product specifications described in this book are subject to change without notice for modification and/or im- provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202

Selected Specification

Panasonic Semiconductor AN32058A overview.

Overview

AN32058A is listed in the Driver IC category. Available datasheets include documents from Panasonic Semiconductor. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

7 x 7 Dots Matrix LED Driver LSI

Description

7 x 7 Dots Matrix LED Driver LSI

Source title AN32058A Datasheet(PDF) - Panasonic Semiconductor

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