AN32055A PANASONIC
Document overview
- Manufacturer or author: Provided By digicamel.com
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Technical content
Datasheet sections
7 x 7 Dots Matrix LED Driver LSI with Step-up DC/DC Converter for White LED AN32055A is a 6-ch LED driver for LCD backlights, and a driver for LED matrix. They supply voltage by step-up DC/DC converter. 7 x 7 LED Matrix Driver (Total LED that can be driven = 49) Built-in memory (ROM and RAM) Step-up DC/DC converter LDO : 2-ch GPIO : 2-ch GPI : 3-ch (3pins from GPI1 to GPI3 are in common with SPI2) GPO : 2-ch SPI Interface : 2-ch (SPI2 is only receiving. It is possible to control only address 05h by SPI2.) Driver for LED (Main LED : 4-ch, Sub LED : 2-ch, LED for Photo flash : 2-ch, RGB color unit : 1-ch) 80 pin Wafer level chip size package (WLCSP)
APPLICATIONS
X0~X6 LX VB VBLED VBDCDC Y0~Y6 LDO2 Battery INT TEST1 TEST2 LEDGND1 LEDGND2 RGBGND1 RGBGND2 PGND1 PGND2 AGND DGND VIBCTL 1.0 F 22 F 4.7 H GPI [ 3ch ] DI DO EXTCLK RSTB 27 k 100 CSB CLK LEDCTL DCDCGND FB VLED1 VLED2 IREF CHGGND 10 F 0.3 GPO [ 2ch ] GPIO [ 2ch ] BLS [ 2ch ] LDOCNT LEDCNT BL [ 4ch ] PL [ 2ch ] 242 LED LDO1 1.0 F VREFD 1.0 F CPU I/F http://www.semicon.panasonic.co.jp/en/ Mobile Phone Smart Phone PCs Game Consoles Home Appliances etc. Note) The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of t he above illustrated application circuit in the design of the equipment. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—V– 0.3 to 6.5 BL1, BL2, BL3, BL4, BLS1, BLS2, PL1, PL2, R1, G1, B1, R2, G2, B2, LDO1, LDO2, LX, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 —V– 0.3 to 6.0LDO1, LDO2 —V– 0.3 to 6.0LEDCNT, LDOCNT, FB *1V6.5VLEDMAX —V– 0.3 to 3.4GPO1, GPO2, INT, DO Output Voltage Range *2C– 30 to + 125TjOperating junction temperature —V– 0.3 to 3.4 LEDCTL, RSTB, CSB, CLK, DI, EXTCLK, VIBCTL, GPI1, GPI2, GPI3, GPIO1, GPIO2 Input Voltage Range *2C–5 5t o+1 2 5TstgStorage temperature —kV1 . 0t o1 . 5HBMESD NoteUnitRatingSymbolParameter *2C–30 to + 85ToprOperating ambience temperature *1V6.0VBMAX Supply voltage 0.335 W0.837 W119.4 C /W80 pin Wafer level chip size package (WLCSP) PD (Ta=85 C)PD (Ta=25 C) JAPACKAGE POWER DISSIPATION RATING Note) For the actual usage, please refer to the P D-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. This value is based on the data LSI mount on PCB Grass Epoxy : 50 X 50 X 0.8 t ( mm ). CAUTION Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1: VBMAX = VBDCDC = VBLED = VB, VLEDMAX = VLED1 = VLED2. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25 C. Although this LSI has built-in ESD protection circuit, it may still sustain permanent damage if not handled properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
RECOMMENDED OPERATING CONDITIONS *2VVLED + 0.3—–0 . 3 BL1, BL2, BL3, BL4, BLS1, BLS2, PL1, PL2, R1, G1, B1, R2, G2, B2, LDO1, LDO2, LX, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 4.63.1 *1V3.7VB *2VVB + 0.3—–0 . 3LEDCNT, LDOCNT, FB 5.0 Typ. —V3.0–0 . 3 LEDCTL, RSTB, CSB, CLK, DI, EXTCLK, VIBCTL, GPI1, GPI2, GPI3, GPIO1, GPIO2 Input Voltage Range –0 . 3 3.1 Min. *1V5.6VLED Supply voltage range —V3.0GPO1, GPO2, INT, DO Output Voltage Range NoteUnitMax.SymbolParameter Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. Do not apply external currents and voltages to any pin not specifically mentioned. Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, DGND, LEDGND1, LEDGND2, RGBGND1, RGBGND2, DCDCGND, PGND1 and PGND2. VB is voltage for VBDCDC, VBLED and VB. VLED is voltage for VLED1 and VLED2. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—A1 LDOCNT = High REG18 = Low V LDO1 = 0 V, IOFF1 = ILDO1 IOFF1Leakage Current when LDO1 turns off —A128 At Standby mode LDOCNT = Low LDO2 is active. ICC2Current consumption (2) —V1.911.851.79ILDO1 = – 30 mAVL1Output voltage —mA20010050 LDOCNT = High REG18 = High VLDO1 = 0 V, IPT1 = ILDO1 IPT1Short circuit protection current —dB–4 0–4 5 VB = 3.6 V + 0.2 V[p-p] f = 1 kHz I LDO1 = – 15 mA PSL11 = 20log(acVLDO1 / 0.2) PSL11Ripple rejection (1) —dB–2 5–3 5 VB = 3.6 V + 0.2 V[p-p] f = 10 kHz I LDO1 = – 15 mA PSL12 = 20log(acVLDO1 / 0.2) PSL12Ripple rejection (2) V V 0.64 1.27 Reference current —0.540.44I IREF = 0 AVIREFOutput voltage Voltage regulator (LDO1) —A2418LDOCNT = High LDO1 and LDO2 are active.ICC3Current consumption (3) —1.241.21IVREF = 0 AVREFOutput voltage Reference voltage Current consumption —A10At OFF mode LDOCNT = LowICC1Current consumption (1) Limits Typ UnitMax NoteMinCondition SymbolParameter
ELECTRICAL CHARACTERISTICS
VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
ms30133Time when INT is set to High from Low, after short detection.TSCPShort detection delay time *1MHz1.441.200.96OSCEN = [1] , DDSW = [1]FDCOscillation frequency V5.575.35.03Mode 2 Iout = – 400 mAVDC2Output voltage (2) V5.164.894.62Mode 1 Iout = – 400 mAVDC1Output voltage (1) dB–3 0–3 5 VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO2 = – 15 mA PSL21 = 20log(acVLDO2 / 0.2) PSL21Ripple rejection (1) mA30010050 LDOCNT = High VLDO2 = 0V IPT2 = ILDO2 IPT2Short circuit protection current A1 LDOCNT = Low REG28 = Low V LDO2 = 0 V IOFF2 = ILDO2 IOFF2Leakage Current when LDO2 turns off V2.942.852.76ILDO2 = – 30 mAVL2Output voltage 4.82 IY0, Y1, Y2, Y3, Y4, Y5, Y6 = – 5 mA RSCAN = VY0, Y1, Y2, Y3, Y4, Y5, Y6 / 5 mA RSCANResistance at the Switch ON SCAN Switch Step-up DC/DC converter Voltage regulator (LDO2) dB–1 5–2 5 VB = 3.6 V + 0.2 V[p-p] f = 10 kHz ILDO2 = – 15 mA PSL22 = 20log(acVLDO2 / 0.2) PSL22Ripple rejection (2) Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. *1: Make sure to set both bits of OSCEN and DDSW to [1]. During OSCEN = [1] , DDSW must be set to [1]. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—A1 At current OFF setup VBL1, BL2, BL3, BL4 = 4.75 V IBLSOFF = IBL1, BL2, BL3, BL4 IBLOFFLeakage Current when BL1 ~ BL4 turn off *2mA8.9578.2947.630 At 8 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS8 = IBL1, BL2, BL3, BL4 IBL8Output current (4) *2mA4.4704.1393.808 At 4 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS4 = IBL1, BL2, BL3, BL4 IBL4Output current (3) *2mA2.2232.0581.894 At 2 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS2 = IBL1, BL2, BL3, BL4 IBL2Output current (2) *2mA1.1091.0270.945 At 1mA setup V BL1, BL2, BL3, BL4 = 1 V IBLS1 = IBL1, BL2, BL3, BL4 IBL1Output current (1) —5–5 At 15 mA setup The average value of all channels, and the current error of each channel IBLCHThe error between channels Current generator (For backlights) *2mA18.21416.86515.516 At 16 mA setup VBL1, BL2, BL3, BL4 = 1 V IBLS16 = IBL1, BL2, BL3, BL4 IBL16Output current (5) Limits Typ UnitMax NoteMinCondition SymbolParameter *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—A1 At current OFF setup VBLS1, BLS2 = 4.75 V IBLSOFF = IBLS1, BLS2 IBLSOFFLeak current at the time of OFF *2mA9.0118.3447.677 At 8 mA setup VBLS1, BLS2 = 1 V IBLS8 = IBLS1, BLS2 IBLS8Output current (4) *2mA4.4804.1493.818 At 4 mA setup VBLS1, BLS2 = 1 V IBLS4 = IBLS1, BLS2 IBLS4Output current (3) *2mA2.2442.0781.912 At 2 mA setup VBLS1, BLS2 = 1 V IBLS2 = IBLS1, BLS2 IBLS2Output current (2) *2mA1.1141.0320.949 At 1mA setup V BLS1, BLS2 = 1 V IBLS1 = IBLS1, BLS2 IBLS1Output current (1) —5–5 At 15 mA setup The average value of all channels, and the current error of each channel IBLSCHThe error between channels Current generator (For sub backlights) *2mA17.99816.66515.331 At 16 mA setup V BLS1, BLS2 = 1 V IBLS16 = IBLS1, BLS2 IBLS16Output current (5) Limits Typ UnitMax NoteMinCondition SymbolParameter *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
*2mA17.86116.53815.215 At 16 mA setup VPL1, PL2 = 1 V IPL16 = IPL1, PL2 IPL16Output current (5) —A1 At current OFF setup VPL1, PL2 = 4.75 V IPLOFF = IPL1, PL2 IPLOFFLeak current at the time of OFF *2mA8.8358.1807.526 At 8 mA setup VPL1, PL2 = 1 V IPL8 = IPL1, PL2 IPL8Output current (4) *2mA4.4104.0833.757 At 4 mA setup VPL1, PL2 = 1 V IPL4 = IPL1, PL2 IPL4Output current (3) *2mA2.2152.0511.887 At 2 mA setup VPL1, PL2 = 1 V IPL2 = IPL1, PL2 IPL2Output current (2) *2mA1.1051.0240.942 At 1mA setup V PL1, PL2 = 1 V IPL1 = IPL1, PL2 IPL1Output current (1) —%5–5 At 15 mA setup The average value of all channels, and the current error of each channel IPLCHThe error between channels Current generator (For photo flashes) *2mA33.15630.70028.244 At 30mA setup VPL1, PL2 = 1 V IPL30 = IPL1, PL2 IPL30Output current (6) Limits Typ UnitMax NoteMinCondition SymbolParameter *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
*2mA16.69315.45614.220 At 15 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX15 = IX0, X1, X2, X3, X4, X5, X6 IMX15Output current (5) 5–5 The average value of all channels, and the current error of each channel IMXCHThe error between channels *2mA8.7818.1317.480 At 8 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX8 = IX0, X1, X2, X3, X4, X5, X6 IMX8Output current (4) *2mA4.3934.0683.742 At 4 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX4 = IX0, X1, X2, X3, X4, X5, X6 IMX4Output current (3) *2mA2.1812.0191.858 At 2 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX2 = IX0, X1, X2, X3, X4, X5, X6 IMX2Output current (2) *2mA1.0801.0000.920 At 1mA setup V X0, X1, X2, X3, X4, X5, X6 = 1 V IMX1 = IX0, X1, X2, X3, X4, X5, X6 IMX1Output current (1) Current generator (For 7*7 dots matrix LED) A1 Current OFF setup VX0, X1, X2, X3, X4, X5, X6 = 4.75 V IMXOFF = IX0, X1, X2, X3, X4, X5, X6 IMXOFFLeak current at the time of OFF Limits Typ UnitMax NoteMinCondition SymbolParameter *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Switch of Pch-MOS (VLED1) 205 VBLED = 2.2 V VCHGGND = 0 V ILED1 = – 10 mA RVLED = ( 2.2 V – VLED1 ) / 10 mA RVLEDVBLED – VLED output impedance Switch of Nch-MOS (R1, R2, G2, B2) 5010 VB = 2.2 V VCHGGND = 0 V IR1 = 5 mA RR1 = VR1 / 5 mA RR1R1 output impedance 3010 Register : 19hD4 = High IR2 = 5 mA RR2 = VR2 / 5 mA RR2R2 output impedance 3010 Register : 19hD3 = High IG2 = 5 mA RG2 = VG2 / 5 mA RG2G2 output impedance A1 Current OFF setup VR1, G1, B1, R2, G2, B2 = 4.75 V IRGBOFF = IR1, G1, B1, R2, G2, B2 IRGBOFFLeak current at the time of OFF 3010 Register : 19hD2 = High IB2 = 5 mA RB2 = VB2 / 5 mA RB2B2 output impedance *2mA8.8818.2237.566At 8 mA setup VR1, G1, B1 = 1 VIRGB8Output current (4) *2mA4.4344.1053.777At 4 mA setup VR1, G1, B1 = 1 VIRGB4Output current (3) *2mA2.2342.0681.903At 2 mA setup V R1, G1, B1 = 1 VIRGB2Output current (2) *2mA1.1151.0320.950At 1mA setup V R1, G1, B1 = 1 VIRGB1Output current (1) Current generator (For RGB color unit) %5–5 The average value of all channels, and the current error of each channel IRGBCHThe error between channels Limits Typ UnitMax NoteMinCondition SymbolParameter *2: Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
VLDO1 + 0.31.4High-level recognition voltage (LDO1 mode)VIH1Input voltage range of High- level 1 VLDO2 + 0.32.1High-level recognition voltage (LDO2 mode)VIH2Input voltage range of High- level 1 V0.4–0 . 3Low-level recognition voltageVILInput voltage range of Low- level A10V GPI1, GPI2, GPI3, GPIO1, GPIO2 = 2.85 V IIH = IGPI1, GPI2, GPI3, GPIO1, GPIO2 IIHInput current of High-level A10VGPI1, GPI2, GPI3, GPIO1, GPIO2 = 0 V IIL = IGPI1, GPI2, GPI3, GPIO1, GPIO2 IILInput current of Low-level GPIO I/F, GPI I/F GPIO I/F, GPO I/F, INT VLDO2 0.8 IGPO1, GPO2, GPIO1, GPIO2, INT = – 2 mA VDDSEL = LDO2VOH1Output voltage of High-level (1) LDO2 0.2 (0.15) IGPO1, GPO2, GPIO1, GPIO2, INT = 2 mA VDDSEL = LDO2 (IGPO1, GPO2, GPIO1, GPIO2, INT = 0.5 mA ) VOL1Output voltage of Low-level (1) VLDO1 0.8 IGPO1, GPO2, GPIO1, GPIO2, INT = – 2 mA VDDSEL = LDO1VOL2Output voltage of High-level (2) LDO1 0.3 (0.15) IGPO1, GPO2, GPIO1, GPIO2, INT = 2 mA VDDSEL = LDO1 (IGPO1, GPO2, GPIO1, GPIO2, INT = 0.5 mA ) VOL2Output voltage of Low-level (2) A10VLEDCTL, RSTB, CSB, CLK, DI = 0 V IIL = ILEDCTL, RSTB, CSB, CLK, DI IILInput current of Low-level A10VLEDCTL, RSTB, CSB, CLK, DI = 1.85 V IIH = ILEDCTL, RSTB, CSB, CLK, DI IIHInput current of High-level V0.4–0 . 3Low-level recognition voltageVILInput voltage range of Low- level VLDO1 + 0.31.4High-level recognition voltageVIHInput voltage range of High- level SPI I/F, LEDCTL, RSTB Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
130k100k70k ITEST1, TEST2, GPI1, GPI2, GPI3 = 5 A RPD = VTEST1, TEST2, GPI1, GPI2, GPI3 / 5 A RPDPull-down resistance TEST1, TEST2, GPI1, GPI2, GPI3 V3.32.1High-level recognition voltageVIHInput voltage range of High- level V0.4–0 . 3Low-level recognition voltageVILInput voltage range of Low- level V10VVIBCTL = 3.0 V IIH = IVIBCTL IIHInput current of High-level A10VVIBCTL = 0 V IIL = IVIBCTL IILInput current of Low-level VIBCTL DO VLDO1 0.8IDO = – 2 mAVOH3Output voltage of High-level VLDO1 0.2IDO = 2 mAVOL3Output voltage of Low-level GPIO1, GPIO2 130k100k70k IGPIO1, GPIO2 = 0 A RPU1 = VGPIO1, GPIO2 IGPIO1, GPIO2 = – 5 A RPU = ( RPU1 – VGPIO1, GPIO2 ) / 5 A RPUPull-up resistance A10VLDOCNT, LEDCNT = 0 V IIL = ILDOCNT, LEDCNT IILInput current of Low-level A10VLDOCNT, LEDCNT = 3.6 V IIH = ILDOCNT, LEDCNT IIHInput current of High-level V0.4–0 . 3Low-level recognition voltageVILInput voltage range of Low- level VVB + 0.3VB 0.7High-level recognition voltageVIHInput voltage range of High- level LDOCNT, LEDCNT Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
mA3.01.2Current when DC/DC converter is active.IDC1DC/DC control current (1) mA1.40.7 Current when DC/DC converter is inactive and the automatic control circuit is operating IDC2DC/DC control current (2) Current consumption of DC/DC converter part V0.440.400.36 Voltage which DC/DC converter turns on when the voltage of BL1, BL2, BL3, BL4, BLS1, and BLS2 terminal falls VMONDetection voltage DC/DC converter automatic control part Limits Typ UnitMax NoteMinCondition SymbolParameter ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
MaxTyp NoteUnitLimitsCondition SymbolParameter Min ILDO1 = – 15 mA – 50 A( 1 s) ILDO1 = – 50 A – 15 mA (1 s) Time until output voltage reaches to 10 % Time until output voltage reaches to 0 V to 90 % *4s250Time until output voltage reaches to 0 V to 90 %Tsu2Rise time *4ms5Time until output voltage reaches to 10 %Tsd2Fall time *4mV70ILDO2 = – 50 A – 15 mA (1 s)Vtr21Load transient response (1) *4mV70ILDO2 = – 15 mA – 50 A( 1 s)Vtr22Load transient response (2) *4F1.0Cldo2Output capacity range *4s250Tsu1Rise time *4ms5Tsd1Fall time *4mV70Vtr11Load transient response (1) *4mV70Vtr12Load transient response (2) *4F1.0Cldo1Output capacity range *40.05Resr1Output capacity ESR tolerance level *5mA15Imax1Maximum output current *40.05Resr2Output capacity ESR tolerance level *5mA15Imax2Maximum output current Voltage regulator (LDO2) Voltage regulator (LDO1) *5 : This IC consumes each 5mA maximum from LDO1 and LDO2 for the internal circuit. When it is used to supply external components, it must be used within 25mA load current. Note) *3 : Rise time and Fall time are defined as below. *4 : Typical Design Value LDOCNT Serial LDO2 10% 90% Tsu2 Tsd2 LDO1 90% 10% Tsu1 Tsd1 ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
MaxTyp NoteUnitLimitsCondition SymbolParameter Min *4F22Cdc1Output capacity range *4V1IDCDCOUT = – 400 mA – 50 A( 1 s)Vtrdc2Load transient response (2) Time after the voltage of BL1 to 4 / BLS1 to 2 goes under 0.4 V until it detects coincidence 3 times and DC/DC converter operates. Time after excess voltage is detected until INT is set to High from Low VLED voltage which detects excess voltage IDCDCOUT Time until output voltage reaches to 3.8 V from 4.9 V IDCDCOUT = 0 mA Time until output voltage reaches to 90 % from battery voltage *7C160 Temperature which LDO1, LDO2, DC/DC, Constant current circuit, Matrix SW and RGB turns off. TdetDetection temperature *8C110Returning temperatureTsd11Return temperature *6ms1Tsu11Rise time *6s1Tsd11Fall time *4V1Vtrdc1Load transient response (1) *40.30Resr1Output capacity ESR tolerance level *4V6.2VOVPExcess voltage detection voltage *4ms12.75TOVPDelay time of Excess voltage detection voltage *4ms2.0TMONDelay time of Constant voltage circuit monitor TSD (Thermal shutdown circuit) Step-up DC/DC converter ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Note) *4 : Typical Design Value *6, *7, *8 : Refer to the next page Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Note) *6 : *7: LDO1, LDO2, DC/DC converter, Constant current circuit, and Matrix SW and RGB are turned off when TSD is High. When TSD is High, the register is set as 14hD 1 = 1. However, data can be read only when the register is read immediately after INT occurs since internal regulator is turned off. *8: Only LDO1 and LDO2 return after ON state of TSD. A logic part will be in Reset state. LX FBSerial 4.7 H 22 F VLED1 VLED2 DCDCGND DCDCOUT VBATT 0.3 VBDCDC 10 F VLF4012AT-4R7M1R1-7 CPH5811 Ceramics PSLA21A106M x 2 PSLB31A226M DCDC Serial DCDCOUT 90% 10% Rise time Fall time ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
*4ns—60——twlc1CLK cycle time Low period *4ns—25—Only READtdodly1DC delay time *4ns—5——tcgh1Chip enable hold time *4ns—62——tsh1Serial-data hold time *4ns—62——tcsw1Transceiver interval *4ns—5——tcss1Chip enable setup time *4ns—62——tss1Serial-data setup time Microcomputer interface characteristic (Vdd = 1.85 V 3%) *4ns—125——tscyc1CLK cycle time *4ns—60——twhc1CLK cycle time High period Microcomputer interface Timing chart twlc1 CLK DO DI tscyc1 tsh1tss1 CSB tcss1 tcsw1 tcgh1 tdodly1 twhc1 ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Note) *4 : Typical Design Value Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
*4ns—62——tcsw2Transceiver interval *4ns—60——Twlc2BLSCLK cycle time Low period *4ns—62——tsh2Serial-data hold time *4ns—5——tcss2BLSCE setup time *4ns—5——tcgh2BLSCE hold time *4ns—62——tss2Serial-data setup time SPI2 format Microcomputer interface characteristic (Vdd = 1.85 V 3%) *4ns—125——tscyc2BLSCLK cycle time *4ns—60—twhc2BLSCLK cycle time High period BLSDAT operation GPI3 operation GPI3 terminal SPI2 operationBLSCLK operationBLSCE operation1 GPIO operationGPI2 operationGPI1 operation0 OperationGPI2 terminalGPI1 terminalSERSEL BLSCLK BLSDAT BLSCE SPI1 SPI2 REG 05h Constant current circuit LCDMAIN SERSEL tcgh2tcss2 tcsw2 tsh2 tscyc2 tss2 D6 D5 D4 D3 D2 D1 D0 twhc2 twlc2 ELECTRICAL CHARACTERISTICS (continued) VB = VBDCDC = VBLED = 3.6 V, VLED1 = VLED2 = 4.9 V Note) T a = 25 C 2 C unless otherwise specified. Note) *4 : Typical Design Value Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
2 INT GPO
1 CLK
Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Constant current circuit. The output terminal of PWM control. It connects with the 1st Row of matrix LED.OutputX0G1(1) Constant current circuit. The output terminal of PWM control. It connects with the 2nd Row of matrix LED.OutputX1G2(2) Constant current circuit. The output terminal of PWM control. It connects with the 3rd Row of matrix LED.OutputX2F2(3) Constant current circuit. The output terminal of PWM control. It connects with the 4th Row of matrix LED.OutputX3E1(4) The GND terminal for matrix LEDGroundPGND1 PGND2 F1(5) D1(6) Constant current circuit. The output terminal of PWM control. It connects with the 5th Row of matrix LED.OutputX4E2(7) Constant current circuit. The output terminal of PWM control. It connects with the 6th Row of matrix LED.OutputX5D2(8) Constant current circuit. The output terminal of PWM control. It connects with the 7th Row of matrix LED.OutputX6C1(9) Constant current circuit. The output terminal of PWM control. It connects with the A Column of matrix LED.OutputY0A3(10) Constant current circuit. The output terminal of PWM control. It connects with the B Column of matrix LED.OutputY1B4(11) Constant current circuit. The output terminal of PWM control. It connects with the C Column of matrix LED.OutputY2A5(12) Constant current circuit. The output terminal of PWM control. It connects with the D Column of matrix LED.OutputY3B5(13) The power supply's connect terminal for matrix LED. Connect with the output of battery or step-up DC/DC converter.Power supplyVLED1 VLED2 A4(14) A6(15) Constant current circuit. The output terminal of PWM control. It connects with the E Column of matrix LED.OutputY4B6(16) Constant current circuit. The output terminal of PWM control. It connects with the F Column of matrix LED.OutputY5A7(17) Constant current circuit. The output terminal of PWM control. It connects with the G Column of matrix LED.OutputY6B7(18) DescriptionTypePin namePin No. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
PIN FUNCTIONS (Continued) The feedback terminal for step-up DC/DC converter.InputFBF9(19) The GND terminal for step-up DC/DC converter.GroundDCDCGNDH9(20) The terminal for External Nch-type MOS-Tr Gate driver.OutputLXG8(21) The power supply's connect terminal for step-up DC/DC converter. Power supplyVBDCDCG9(22) LED contact terminal. Control by LEDCNT terminal is also possible.OutputR1B3(23) LED contact terminal.OutputG1C5(24) LED contact terminal.OutputB1C4(25) The GND terminal for RGB terminal.GroundRGBGND1 RGBGND2 A2(26) B1(27) General-purpose output terminal.(Nch-MOS Open Drain)OutputR2C2(28) General-purpose output terminal.(Nch-MOS Open Drain)OutputG2C3(29) General-purpose output terminal.(Nch-MOS Open Drain)OutputB2D3(30) The resistance contact terminal for charge LED.(Connect current restriction resistance between this terminal and GND terminal.)OutputCHGGNDD4(31) Battery voltage's connect terminal. This terminal supplies Power supply to R1 terminal and R2 terminal. Power supplyVBLEDC6(32) ON/OFF control terminal of LED connected to R1 terminal and R2 terminal.InputLEDCNTC8(33) LDO2 (2.85 V) output terminal.OutputLDO2D9(34) The power supply's connect terminal for BGR circuit and LDO circuit. Power supplyVBE9(35) LDO1 (1.85 V) output terminal.OutputLDO1E8(36) ON/OFF control terminal of LDO1 and LDO2.InputLDOCNTF8(37) BGR circuit output terminal.OutputVREFDC9(38) The resistance connect terminal for constant current value setup.OutputIREFD8(39) DescriptionTypePin namePin No. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
PIN FUNCTIONS (Continued) The constant current output terminal for LED driver. (0 to 61 mA) This terminal is driven with the same current value as PL2 terminal.OutputPL1J3(40) The constant current output terminal for LED driver. (0 to 61 mA) This terminal is driven with the same current value as PL1 terminal.OutputPL2H3(41) The GND terminal for constant current circuits for LED driver.GroundLEDGND1 LEDGND2 J5(42) J2(43) The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL2, BL3 and BL4 terminal. OutputBL1H6(44) The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL1, BL3 and BL4 terminal. OutputBL2H5(45) The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL1, BL2 and BL4 terminal. OutputBL3J4(46) The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BL1, BL2 and BL3 terminal. OutputBL4H4(47) The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BLS2 terminal.OutputBLS1J7(48) The constant current output terminal for LED driver. (0 to 31 mA) This terminal is driven with the same current value as BLS1 terminal.OutputBLS2J6(49) The GND terminal for Analog circuitry.GroundAGNDB9(50) Interrupt output terminal.OutputINTG5(51) Test terminal.InputTEST1F3(52) Test terminal.InputTEST2D7(53) Chip-enable terminal for SPI1 interface.InputCSBE7(54) Clock input terminal for SPI1 interface.InputCLKE6(55) Data input terminal for SPI1 interface.InputDIF6(56) Data output terminal for SPI1 interface.OutputDOF7(57) Reset input terminalInputRSTBC7(58) DescriptionTypePin namePin No. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
External clock input terminal. (It can operate by the clock frequency of a maximum of 1.44 MHz.)InputEXTCLKG3(59) The GND terminal for Logic circuitry.GroundDGNDJ8(60) GPI input port terminal. (Chip-enable terminal for SPI2 interface.)InputGPI1E3(61) GPI input port terminal. (Clock input terminal for SPI2 interface.)InputGPI2F5(62) GPI input port terminal. (Data input terminal for SPI2 interface.)InputGPI3F4(63) GPO output port terminal. OutputGPO1G6(64) GPO output port terminal. OutputGPO2G4(65) GPIO input/output port terminal.Input / OutputGPIO1D6(66) GPIO input/output port terminal.Input / OutputGPIO2D5(67) LED's lighting ON/OFF control terminal. (It is based on register 0Ah.)InputLEDCTLH7(68) LED's lighting ON/OFF control terminal. (It is based on register 09h.)InputVIBCTLG7(69) DescriptionTypePin namePin No. PIN FUNCTIONS (Continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
E1(4) G1(1) G2(2) F2(3) E2(7) D2(8) C1(9) A5(12) A3(10) B4(11) B5(13) B6(16) A7(17) B7(18) Constant Current control (7-ch) PWM control (7-ch) SCAN switch (7-ch) G6(64) F4(63) F5(62) E3(61) E9(35) D9(34) E8(36) F8(37) C9(38) H6(44) H5(45) J4(46) H4(47) J7(48) J6(49) Back light Constant current control (6-ch) Photo flash Constant current control (2-ch) J8(60) G7(69) LDO2
2.85 V/30mA
1.85 V/30mA
D5(67) D6(66) G4(65) SPI2 Register Pattern register RAM Fixed pattern ROM Command decoding BLSDAT BLSCLK BLSCE DAC (2-ch) DAC (6-ch) C8(33) SPI1 G8(21) IREF G9(22) H7(68) A4(14) A6(15) D3(30) C3(29) C2(28) B3(23) C5(24) C4(25)RGB control F1(5) D1(6) H9(20) F9(19) B1(27) C6(32) J3(40) H3(41) J5(42) D8(39) J2(43) B9(50) G5(51) F3(52) D7(53) E7(54) E6(55) F6(56) F7(57) C7(58) G3(59) Level shift Level shift ON/OFF STANDBY ON/OFF HTSD ON/OFF A2(26) D4(31) ON/OFF Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—18N.C. (ON) N.C. (ON)Low High High : ON At Standby mode Low : OFF High : ON < 1 (OFF mode ) or 8 (Standby mode) < 1 Itotal typ ( A) Low : OFF At OFF mode N.C. (ON) OFF REG28
- Regardless of the value of REG18, LDO1 turns on at LDOCNT = High.
- Regardless of the value of REG28, LDO2 turns on at LDOCNT = High.
- Serial interface signal is not received at RSTB = Low
- 5 ms after being set to LDOCNT = High, the receptionist of serial interface signal is attained.
- To activate RSTB, RSTB should be kept low for more than one internal clock period.
- RSTB terminal prohibits the input signal of those other than a rectangle wave. N.C. (OFF) High Low
- The signal from serial interface is not received in LDOCNT = Low and the state of REG28 = Low or REG18 = Low.
- It shifts to standby mode with LDOCNT = Low and REG28 = High.
- The signal from serial interface is not received at Standby-mode. (Power supply for Logic is LDO1 and LDO2.) Therefore, standby release by the signal from serial interface cannot be performed.
- In Standby-mode, if LDOCNT is switched to High from Low, it will return to the normal mode.
- It cannot shift to OFF-mode from Standby- mode. Once returning to the normal mode, please shift to OFF-mode.
- RSTB = Low is prohibited in Standby-mode. (An internal circuit becomes unfixed.)
- Do not impress voltage to GPI1, GPI2, GPI3, GPIO1, and GPIO2 terminal in Standby-mode. N.C. (ON)High
- It is necessary to make it LDOCNT = High for the return from OFF-mode.
- RSTB = Low is forbidden at OFF-mode. (An internal circuit becomes unfixed.)
- Do not impress voltage to GPI1, GPI2, GPI3, GPIO1, and GPIO2 terminal at OFF-mode. OFF Low (Initial condition) NotesREG18LDOCNT OPERATION 1. Explanation of each mode ( Power supply startup sequence ) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
- This is the waveform in the case of applying reset to register setup at Standby mode. * Maintain the state of RSTB = High to hold the register setup. LDOCNT LDO1 LDO2 REG18 REG28 A register input is possible.over 5 ms LDOCNT LDO1 LDO2 REG18 REG28 A register input is possible. Shift to the Normal mode from Standby mode RSTB over 3 ms RSTB over 5 ms over 3 ms Low power mode Shift to the Normal mode from OFF-mode OPERATION (continued) 1. Explanation of each mode ( Power supply startup sequence ) (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Shift to the Standby mode from Normal mode LDOCNT LDO1 LDO2 REG18 REG28 Over 1 ms A register input is possible. Set REG18 to Low before LDOCNT. Low power mode RSTB LDOCNT LDO1 LDO2 REG18 REG28 Over 1 ms Set REG18 and REG28 to Low before LDOCNT. A register input is possible. RSTB Over 3 ms Shift to the OFF-mode from Normal mode OPERATION (continued) 1. Explanation of each mode ( Power supply startup sequence ) (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
(About 180.83 Hz) 8clk (6.67 s) 945clk (787.5 s) Minimum width of PWM 63clk (52.5 s) The following waveform is an internal signal. In following Yx = Xx = Low, the waveform of actual Yx terminal is set to Hi-Z. Matrix part operation waveform OPERATION (continued) 2. Explanation of operation Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
V DCDC Output 6.2 V V LDO2 0 V V Serial DDSW LDO2 0 V 0 V V LX VB 0 V 4.9 V FB terminal is open Latch release will be carried out if serial DDSW is set to Low. FB The shut after about 13 ms after DC/DC output voltage is set to about 6.2 V. VB Time Time Time Time About 8 ms About 13 ms Internal shutdown signal Explanation of excess voltage protection circuit of operation OPERATION (continued) 2. Explanation of operation (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
V 0 V LDO2 0 V LDO2 0 V 0 V LX VB 0 V 4.9V VB Time Time Time Time Time V V V V FB A shutdown is generated, when the output voltage of internal error amplifier goes up, and duty MAX state is set to about 13 ms or more. Latch release will be carried out if serial DDSW is set to Low. Serial DDSW DC/DC output is short-circuited to GND. DCDC Output About 8 ms Internal error amplifier output voltage Internal shutdown signal About 13 ms Explanation of over-current protection circuit of operation OPERATION (continued) 2. Explanation of operation (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
2.85 V 1 F 1 F LDO2 LDO1 LDO1 1.85 V REG18 All the logic portions to which the power supply is not connected are connected to VB as power supplies. LEVEL SHIFT ON/OFF ON/OFF STANDBY ON/OFF HTSDON/OFF 1 F VREFD LEVEL SHIFT LDO1 LDO2LDO1 LDO2 LDO2 VBLDO2 RESET part block configuration OPERATION (continued) 3. Block configuration Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
All the logic portions to which the power supply is not connected are connected to VB as power supplies. Adjust R value with the LED and current you use. VBATT VBLED 22 F VLED1 LX DC/DC LEDCNT[VB] 4.7 H 100 k 0.3 This function cannot be used when DC/DC converter is active. VLED2 FB DDSW GNDCHG DGND VLF4012 CPH5811 The LED part for charge block configuration OPERATION (continued) 3. Block configuration (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
The connected terminal name LED’s number LED’s number Explanation of matrix LED part, matrix LED’s number OPERATION (continued) 3. Block configuration (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
T RAMA CT——ERR2 EH FACG IOFAC TORR14h —DISRG DISMT X DISSU DISSU DISPL DISPL LEDA CT LEDCT LW0Ah W/R W/R W/R W/R W/R R W/R W/R W/R W/R W W W W W R W W W R/W IOVSE L2OVSEl2— IOSTA2IOSTA1ISTA3ISTA2 IOOUT IOOUT 1OOUT2OOUT1 IMSK2IOMSK 1IMSK3IMSK2 PWMC LKBLS2MBLS1MBL4MBL3MBL2MBL1M—PWMC NT08h IODET[1:0]IDET[1:0]————IODET18h IOCHAT2[1:0]IOCHAT1[1:0]————IOCHA T17h ICHAT3[1:0]ICHAT2[1:0]ICHAT1[1:0]——ICHAT16h ISTA1——STAG D IOSTA TE15h IOVSE OVSEL 1——INTVS EL VDDS EL1Ah IOPLU IOPLU D1B2ONG2ONR2ON———IOPLU D19h GPIOC NT10h —VIBRG VIBMT X VIBSU VIBSU VIBPL VIBPL VIBA CT VIBCT L09h PLCNT[4:0]HIEN——PLCNT07h LCDSUB[4:0]———LCDSU B06h LCDMAIN[4:0]———LCDM AIN05h LSIVER[7:0]LSIVE R04h SERSE EL03h Data Name Sub Address ————IOOUT13h IMSK1———IOMSK12h NT02h DDSWDCOSE LOSCENVFOFF——POWE RCNT01h D5D6D7 DATA D0D1D2D3D4 OPERATION (continued) 4. Register and Address Register Map Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
————PROT 2—— —PROT2R/W6Dh PROT 3PROT3R/W6Fh IOFAC2IOFA C1IFAC3IFAC2IFAC1OVPSCPFACG D2ERRORR2Eh RAMNUM— RGBDATA[5:0]——RGBDATAR/W2Dh SCLTIME[1:0] SETTIME[1:0]——————SETTIMER/W28h REPON ——— SETTO[7:0]SETTOR/W26h TEST6TEST6R/W75h TEST1TEST1R/W70h TEST2TEST2R/W71h TEST3TEST3R/W72h TEST4TEST4R/W73h TEST5TEST5R/W74h TEST6TEST7R/W76h R/W R/W R/W R/W R/W R/W R/W R/W R/W TEST7TEST877h SETFROM[7:0]SETFROM25h —REPON27h COPYSTA RT SELR AM——RAMCOPY24h SELROM[7:0]ROMSEL23h Data Name Sub Address MTXDATA[7:0]MTXDATA21h D5D6D7 DATA D0D1D2D3D4 Register Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DLA1[1:0]FRA1[1:0]BLA1[3:0]A131h DLA2[1:0]FRA2[1:0]BLA2[3:0]A232h DLA3[1:0]FRA3[1:0]BLA3[3:0]A333h DLA4[1:0]FRA4[1:0]BLA4[3:0]A434h DLA5[1:0]FRA5[1:0]BLA5[3:0]A535h DLA6[1:0]FRA6[1:0]BLA6[3:0]A636h DLA7[1:0]FRA7[1:0]BLA7[3:0]A737h DLB1[1:0]FRB1[1:0]BLB1[3:0]B138h DLB2[1:0]FRB2[1:0]BLB2[3:0]B239h DLB3[1:0]FRB3[1:0]BLB3[3:0]B33Ah DLB4[1:0]FRB4[1:0]BLB4[3:0]B43Bh DLB5[1:0]FRB5[1:0]BLB5[3:0]B53Ch DLB6[1:0]FRB6[1:0]BLB6[3:0]B63Dh DLB7[1:0]FRB7[1:0]BLB7[3:0]B73Eh DLC1[1:0]FRC1[1:0]BLC1[3:0]C13Fh DLC2[1:0]FRC2[1:0]BLC2[3:0]C240h DLC3[1:0]FRC3[1:0]BLC3[3:0]C341h DLC4[1:0]FRC4[1:0]BLC4[3:0]C442h DLC5[1:0]FRC5[1:0]BLC5[3:0]C543h DLC6[1:0]FRC6[1:0]BLC6[3:0]C644h DLC7[1:0]FRC7[1:0]BLC7[3:0]C745h DLD1[1:0]FRD1[1:0]BLD1[3:0]D146h DLD2[1:0]FRD2[1:0]BLD2[3:0]D247h DLD3[1:0]FRD3[1:0]BLD3[3:0]D348h DLD4[1:0]FRD4[1:0]BLD4[3:0]D449h DLD5[1:0]FRD5[1:0]BLD5[3:0]D54Ah DLD6[1:0]FRD6[1:0]BLD6[3:0]D64Bh DLD7[1:0]FRD7[1:0]BLD7[3:0]D74Ch Data Name Sub Address D5D6D7 DATA D0D1D2D3D4 RAM Address Map OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DLG7[1:0]FRG7[1:0]BLG7[3:0]G761h DLLEDB1[1:0] DLLEDG1[1:0] DLLEDR1[1:0] FRLEDB1[1:0] FRLEDG1[1:0] FRLEDR1[1:0]BLLEDR1[3:0]LEDR162h BLLEDG1[3:0]LEDG163h BLLEDB1[3:0]LEDB164h DLE1[1:0]FRE1[1:0]BLE1[3:0]E14Dh DLE2[1:0]FRE2[1:0]BLE2[3:0]E24Eh DLE3[1:0]FRE3[1:0]BLE3[3:0]E34Fh DLE4[1:0]FRE4[1:0]BLE4[3:0]E450h DLE5[1:0]FRE5[1:0]BLE5[3:0]E551h DLE6[1:0]FRE6[1:0]BLE6[3:0]E652h DLE7[1:0]FRE7[1:0]BLE7[3:0]E753h DLF1[1:0]FRF1[1:0]BLF1[3:0]F154h DLF2[1:0]FRF2[1:0]BLF2[3:0]F255h DLF3[1:0]FRF3[1:0]BLF3[3:0]F356h DLF4[1:0]FRF4[1:0]BLF4[3:0]F457h DLF5[1:0]FRF5[1:0]BLF5[3:0]F558h DLF6[1:0]FRF6[1:0]BLF6[3:0]F659h DLF7[1:0]FRF7[1:0]BLF7[3:0]F75Ah DLG1[1:0]FRG1[1:0]BLG1[3:0]G15Bh DLG2[1:0]FRG2[1:0]BLG2[3:0]G25Ch DLG3[1:0]FRG3[1:0]BLG3[3:0]G35Dh DLG4[1:0]FRG4[1:0]BLG4[3:0]G45Eh DLG5[1:0]FRG5[1:0]BLG5[3:0]G55Fh DLG6[1:0]FRG6[1:0]BLG6[3:0]G660h Data NameSub Address D5D6D7 DATA D0D1D2D3D4 RAM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
NothingAll putting out lights0 DisplayContents of the patternPattern No. RAlphabetic character28 QAlphabetic character27 PAlphabetic character26 OAlphabetic character25 NAlphabetic character24 MAlphabetic character23 LAlphabetic character22 KAlphabetic character21 JAlphabetic character20 IAlphabetic character19 HAlphabetic character18 GAlphabetic character17 FAlphabetic character16 EAlphabetic character15 DAlphabetic character14 CAlphabetic character13 BAlphabetic character12 AAlphabetic character11 9Number10 8Number9 7Number8 6Number7 5Number6 4Number5 3Number4 2Number3 1Number2 0Number1 wAlphabetic character59 xAlphabetic character60 yAlphabetic character61 DisplayContents of the patternPattern No. vAlphabetic character58 uAlphabetic character57 tAlphabetic character56 sAlphabetic character55 rAlphabetic character54 qAlphabetic character53 pAlphabetic character52 oAlphabetic character51 nAlphabetic character50 mAlphabetic character49 lAlphabetic character48 kAlphabetic character47 jAlphabetic character46 iAlphabetic character45 hAlphabetic character44 gAlphabetic character43 fAlphabetic character42 eAlphabetic character41 dAlphabetic character40 cAlphabetic character39 bAlphabetic character38 aAlphabetic character37 ZAlphabetic character36 YAlphabetic character35 XAlphabetic character34 WAlphabetic character33 VAlphabetic character32 UAlphabetic character31 [00000000] - [10010101] : ROM(Only luminosity) 7 7 Pattern No.0 (default) to Pattern No.149 ROM Address Map OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
ネKatakana92 ヌKatakana91 zAlphabetic character62 DisplayContents of the patternPattern No. ニKatakana90 ナKatakana89 トKatakana88 テKatakana87 ッKatakana86 ツKatakana85 チKatakana84 タKatakana83 ソKatakana82 セKatakana81 スKatakana80 シKatakana79 サKatakana78 コKatakana77 ケKatakana76 クKatakana75 キKatakana74 カKatakana73 ォKatakana72 オKatakana71 ェKatakana70 エKatakana69 ゥKatakana68 ウKatakana67 ィKatakana66 イKatakana65 ァKatakana64 アKatakana63 HeartSymbol121 MailSymbol122 TelephoneSymbol123 DisplayContents of the patternPattern No. ーSymbol120 ゜Symbol119 ゛Symbol118 ンKatakana117 ヲKatakana116 ワKatakana115 ロKatakana114 レKatakana113 ルKatakana112 リKatakana111 ラKatakana110 ョKatakana109 ヨKatakana108 ュKatakana107 ユKatakana106 ャKatakana105 ヤKatakana104 モKatakana103 メKatakana102 ムKatakana101 ミKatakana100 マKatakana99 ホKatakana98 へKatakana97 フKatakana96 ヒKatakana95 ハKatakana94 ノKatakana93 [00000000] - [10010101] : ROM(Only luminosity) 7 7 Pattern No.0 (default) to Pattern No.149 ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DisplayContents of the patternPattern No. ○Symbol143 ♪Symbol142 Clock markSymbol141 〒Symbol140 Symbol139 Symbol138 Symbol137 Symbol136 ?Symbol135 !Symbol134 :Symbol133 =Symbol132 Symbol131 Symbol130 Symbol129 +Symbol128 Three antennaSymbol127 Two antennaSymbol126 One antennaSymbol125 Symbol144 △Symbol145 □Symbol146 ◇Symbol147 ▽Symbol148 ¥Symbol149 DisplayContents of the patternPattern No. [00000000] - [10010101] : ROM(Only luminosity) 7 7 Pattern No.0 (default) to Pattern No.149 ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Square out 1 sGradation150 DisplayContents of the patternPattern No. Up 2 sGradation172 Up 1 sGradation171 Down 3 sGradation170 Down 2 sGradation169 Down 1 sGradation168 Slant left up 3 sGradation167 Slant left up 2 sGradation166 Slant left up 1 sGradation165 Slant right up 3 sGradation164 Slant right up 2 sGradation163 Slant right up 1 sGradation162 Slant left down 3 sGradation161 Slant left down 2 sGradation160 Slant left down 1 sGradation159 Slant right down 3 sGradation158 Slant right down 2 sGradation157 Slant right down 1 sGradation156 Square in 3 sGradation155 Square in 2 sGradation154 Square in 1 sGradation153 Square out 3 sGradation152 Square out 2 sGradation151 Right 1 sGradation174 Right 2 sGradation175 Right 3 sGradation176 Left 1 sGradation177 Left 2 sGradation178 Left 3 sGradation179 Slant right center 1 sGradation180 Slant right center 2 sGradation181 Slant right center 3 sGradation182 Slant left center 1 sGradation183 Slant left center 2 sGradation184 DisplayContents of the patternPattern No. Square right down 3 sGradation194 Square right down 2 sGradation193 Square right down 1 sGradation192 Side center 3 sGradation191 Side center 2 sGradation190 Side center 1 sGradation189 Vertical center 3 sGradation188 Vertical center 2 sGradation187 Vertical center 1 sGradation186 Slant left center 3 sGradation185 [10010110] - [11010000] : ROM(Luminosity Cycle Delay) 7 7 Pattern No.150 to Pattern No.208 ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Square left down 1 sGradation195 Square left down 2 sGradation196 Square left down 3 sGradation197 Square right up 1 sGradation198 Square right up 2 sGradation199 Square right up 3 sGradation200 Square left up 1 sGradation201 Square left up2 sGradation202 Square left up 3 sGradation203 Square crossing in 1 sGradation204 Square crossing in 2 sGradation205 Square crossing in 3 sGradation206 Square crossing out1 sGradation207 Square crossing out2 sGradation208 Display Contents of the pattern Pattern No. [10010110] - [11010000] : ROM(Luminosity Cycle Delay) 7 7 Pattern No.150 to Pattern No.208 ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Firefly 1 s : Color 9Color 9 Firefly 1 s21 Firefly 1 s : Color 10Color 10 Firefly 1 s22 Firefly 1 s : Color 11Color 11 Firefly 1 s23 Firefly 1 s : Color 12Color 12 Firefly 1 s24 Firefly 1 s : Color 8Color 8 Firefly 1 s20 Turn on : BlueColor 11 DisplayContents of the patternPattern No. Firefly 1 s : Color 7Color 7 Firefly 1 s19 Firefly 1 s : Color 6Color 6 Firefly 1 s18 Firefly 1 s : Color 5Color 5 Firefly 1 s17 Firefly 1 s : Color 4Color 4 Firefly 1 s16 Firefly 1 s : Color 3Color 3 Firefly 1 s15 Firefly 1 s : Color 2Color 2 Firefly 1 s14 Firefly 1 s : Color 1Color 1 Firefly 1 s13 Turn on : Red + Blue + GreenColor 1212 Turn on : Between 9 and 10Color 1111 Turn on : Red + BlueColor 1010 Turn on : RedColor 99 Turn on : Between 7 and 9Color 88 Turn on : Red + GreenColor 77 Turn on : Between 5 and 7Color 66 Turn on : GreenColor 55 Turn on : Between 3 and 5Color 44 Turn on : Green + BlueColor 33 Turn on : Between 1 and 3Color 22 Firefly 2 s : Color 1Color 1 Firefly 2 s25 Firefly 2 s : Color 2Color 2 Firefly 2 s26 Firefly 2 s : Color 3Color 3 Firefly 2 s27 Firefly 2 s : Color 4Color 4 Firefly 2 s28 Firefly 2 s : Color 5Color 5 Firefly 2 s29 Firefly 2 s : Color 6Color 6 Firefly 2 s30 Firefly 2 s : Color 7Color 7 Firefly 2 s31 Firefly 2 s : Color 8Color 8 Firefly 2 s32 DisplayContents of the patternPattern No. Gradation 6Gradation 642 Gradation 5Gradation 541 Gradation 4Gradation 440 Gradation 3Gradation 339 Gradation 2Gradation 238 Gradation 1Gradation 137 Firefly 2 s : Color 12Color 12 Firefly 2 s36 Firefly 2 s : Color 11Color 11 Firefly 2 s35 Firefly 2 s : Color 10Color 10 Firefly 2 s34 Firefly 2 s : Color 9Color 9 Firefly 2 s33 [000001] - [101010] : ROM(RGB pattern, Luminosity Cycle Delay )RGB pattern No.1 to No.42 ROM Address Map (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
ACT——ERR2EHFACGD 1IOFACTORR14h W/R W/R W/R R W/R W W W W R/W IOST A2IOSTA1ISTA3ISTA IMSK 2IOMSK1IMSK IMSK IODET[1:0]IDET[1:0]————IODET18h IOCHAT2[1:0]IOCHAT1[1:0]————IOCHAT17h ICHAT3[1:0]ICHAT2[1:0]ICHAT1[1:0]——ICHAT16h ISTA1——STAGDIOSTATE15h PLCNT[4:0]HIEN——PLCNT07h LCDSUB[4:0]———LCDSUB06h LCDMAIN[4:0]———LCDMAIN05h Data NameSub Address IMSK1———IOMSK12h DDS W DCO SEL OSC EN VF OFF——POWERCNT01h D5D6D7 DATA D0D1D2D3D4 About the following addresses, even if an internal clock or an external clock does not exist, Read / Write is possible in the data to register. However, it cannot be given to operation finally needed. Register table which needs a clock OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
1IFAC3IFAC2IFAC1OVPSCPFACGD2ERRORR2Eh RAMNUM— RGBDATA[5:0]——RGBDATAR/W2Dh SCLTIME[1:0] SETTIME[1:0]——————SETTIMER/W28h REPON ——— SETTO[7:0]SETTOR/W26h R/W R/W R/W R/W R/W R/W R/W R/W SETFROM[7:0]SETFROM25h —REPON27h COPY START SEL RAM——RAMCOPY24h SELROM[7:0]ROMSEL23h Data NameSub Address MTXDATA[7:0]MTXDATA21h D5D6D7 DATA D0D1D2D3D4 About the following addresses, even if an internal clock or an external clock does not exist, Read / Write is possible in the data to register. However, it cannot be given to operation finally needed. Register table which needs a clock (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DLA1[1:0]FRA1[1:0]BLA1[3:0]A131h DLA2[1:0]FRA2[1:0]BLA2[3:0]A232h DLA3[1:0]FRA3[1:0]BLA3[3:0]A333h DLA4[1:0]FRA4[1:0]BLA4[3:0]A434h DLA5[1:0]FRA5[1:0]BLA5[3:0]A535h DLA6[1:0]FRA6[1:0]BLA6[3:0]A636h DLA7[1:0]FRA7[1:0]BLA7[3:0]A737h DLB1[1:0]FRB1[1:0]BLB1[3:0]B138h DLB2[1:0]FRB2[1:0]BLB2[3:0]B239h DLB3[1:0]FRB3[1:0]BLB3[3:0]B33Ah DLB4[1:0]FRB4[1:0]BLB4[3:0]B43Bh DLB5[1:0]FRB5[1:0]BLB5[3:0]B53Ch DLB6[1:0]FRB6[1:0]BLB6[3:0]B63Dh DLB7[1:0]FRB7[1:0]BLB7[3:0]B73Eh DLC1[1:0]FRC1[1:0]BLC1[3:0]C13Fh DLC2[1:0]FRC2[1:0]BLC2[3:0]C240h DLC3[1:0]FRC3[1:0]BLC3[3:0]C341h DLC4[1:0]FRC4[1:0]BLC4[3:0]C442h DLC5[1:0]FRC5[1:0]BLC5[3:0]C543h DLC6[1:0]FRC6[1:0]BLC6[3:0]C644h DLC7[1:0]FRC7[1:0]BLC7[3:0]C745h DLD1[1:0]FRD1[1:0]BLD1[3:0]D146h DLD2[1:0]FRD2[1:0]BLD2[3:0]D247h DLD3[1:0]FRD3[1:0]BLD3[3:0]D348h DLD4[1:0]FRD4[1:0]BLD4[3:0]D449h DLD5[1:0]FRD5[1:0]BLD5[3:0]D54Ah DLD6[1:0]FRD6[1:0]BLD6[3:0]D64Bh DLD7[1:0]FRD7[1:0]BLD7[3:0]D74Ch Data NameSub Address D5D6D7 DATA D0D1D2D3D4 About the following addresses, when an internal clock or an external clock does not exist, data cannot be Read / Write in at register. Register table which needs a clock (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DLG7[1:0]FRG7[1:0]BLG7[3:0]G761h DLLEDB1[1:0] DLLEDG1[1:0] DLLEDR1[1:0] FRLEDB1[1:0] FRLEDG1[1:0] FRLEDR1[1:0]BLLEDR1[3:0]LEDR162h BLLEDG1[3:0]LEDG163h BLLEDB1[3:0]LEDB164h DLE1[1:0]FRE1[1:0]BLE1[3:0]E14Dh DLE2[1:0]FRE2[1:0]BLE2[3:0]E24Eh DLE3[1:0]FRE3[1:0]BLE3[3:0]E34Fh DLE4[1:0]FRE4[1:0]BLE4[3:0]E450h DLE5[1:0]FRE5[1:0]BLE5[3:0]E551h DLE6[1:0]FRE6[1:0]BLE6[3:0]E652h DLE7[1:0]FRE7[1:0]BLE7[3:0]E753h DLF1[1:0]FRF1[1:0]BLF1[3:0]F154h DLF2[1:0]FRF2[1:0]BLF2[3:0]F255h DLF3[1:0]FRF3[1:0]BLF3[3:0]F356h DLF4[1:0]FRF4[1:0]BLF4[3:0]F457h DLF5[1:0]FRF5[1:0]BLF5[3:0]F558h DLF6[1:0]FRF6[1:0]BLF6[3:0]F659h DLF7[1:0]FRF7[1:0]BLF7[3:0]F75Ah DLG1[1:0]FRG1[1:0]BLG1[3:0]G15Bh DLG2[1:0]FRG2[1:0]BLG2[3:0]G25Ch DLG3[1:0]FRG3[1:0]BLG3[3:0]G35Dh DLG4[1:0]FRG4[1:0]BLG4[3:0]G45Eh DLG5[1:0]FRG5[1:0]BLG5[3:0]G55Fh DLG6[1:0]FRG6[1:0]BLG6[3:0]G660h Data NameSub Address D5D6D7 DATA D0D1D2D3D4 About the following addresses, when an internal clock or an external clock does not exist, data cannot be Read / Write in at register. Register table which needs a clock (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—— DDSW OSCEN— Default DCOSELVFOFF—Data Name 01h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D3 : VFOFF DC/DC converter automatic control selection bit [0] : The automatic control of DC/DC converter is possible. (default) [1] : The automatic control of DC/DC converter is impossible. * The constant current terminal which acts as a monitor is chosen by BL1M, BL2M, BL3M, BL4M, BLS1M, and BLS2M bit of address 08h at VFOFF = Low. And if it is less than 0.4 V, DC/DC converter will be activated. D2 : OSCEN The ON/OFF bit for internal oscillators [0] : Internal oscillating circuit is OFF (default) [1] : Internal oscillating circuit is ON * The variation width of an internal oscillator is set to 0.96MHz - 1.44 MHz. * The variation width of an internal clock is set to 694.4 ns – 1042 ns. D1 : DCOSEL DC/DC converter output voltage setup [0] : Output voltage set to 4.9 V (default) [1] : Output voltage set to 5.3 V D0 : DDSW The ON/OFF bit for DC/DC converter [0] : DC/DC converter is OFF (default) [1] : DC/DC converter is ON * Set both bits of DDSW and OSCEN to [1] to operate DC/DC converter. * Make sure to set both bits of OSCEN and DDSW to [1]. * During OSCEN = [1] , DDSW must be set to [1]. Register map detailed explanation OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
REG28———— Default REG18——Data Name 02h W W W DATA mode Sub Address WWWWW 11000 D0D1D2D3D4 D1 : REG18 The ON/OFF control for LDO1(When LDOCNT terminal is Low) [0] : LDO1 OFF [1] : LDO1 ON (default) D0 : REG28 The ON/OFF control for LDO2( When LDOCNT terminal is Low ) [0] : LDO2 OFF [1] : LDO2 ON (default) * When LDOCNT terminal is High, regardless of the state of REG18, LDO1 will be activated. * When LDOCNT terminal is High, regardless of the state of REG28, LDO2 will be activated. * Set LDOCNT to Low after setting REG28 to Low to put into OFF mode. —18N.C. (ON) N.C. (ON)Low High High : ON At Standby mode Low : OFF High : ON <1 (OFF mode) or 8 (Standby mode) Itotal typ(mA) Low : OFF At OFF mode N.C. (ON) OFF REG28 N.C. (OFF) High Low *N.C. (ON)High *OFFLow (Initial condition) NoteREG18LDOCNT Note) * : Explanation in each mode (Power supply starting sequence) of Page 26. Refer to the note. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
SERSEL———— Default ———Data Name 03h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D0 : SERSEL The serial interface change which controls LCDMAIN luminosity control. [0] : GPIO operation (default) [1] : Serial control of address 05h (LCDMAIN) by SPI2 * GPI1 to GPI3 terminals serve as an input setup and an interruption mask compulsorily at SERSEL = High setup. SPI1 SPI2 REG 05h Constant current circuit LCDMAIN SERSEL BLSDAT operation GPI3 operation GPI3 terminal SPI2 operationBLSCLK operationBLSCE operation1 GPIO operationGPI2 operationGPI1 operation0 OperationGPI2 terminalGPI1 terminalSERSEL Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
LSIVER[7:0]Data Name 04h R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 D7-0 : LSIVER[7:0] The register showing the version of LSI [00000000] : ES1 [00000001] : ES2 Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
LCDMAIN[4:0]—— Default —Data Name 05h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D4-0 : LCDMAIN[4:0] Output current setup of BL1-BL4 terminal [00000] : 0 mA (default) [00001] : 1 mA [00010] : 2 mA [11110] : 30 mA [11111] : 31 mA The waveform of main LCD backlights current of operation * As for main LCD backlights part, output current changes stepwise for noise reduction. * By the time it reaches current setup value, there will be delay of setup value internal 32clk. * When internal CLK stops during state transition, the state at that time is held. * The following waveform is internal signal. 32clk (typ26.6 s) 00000 00001 00010 00011 00100 00101 00110 00111 01000 0000001000 01000 00011 Internal luminosity set point signal t 32clk 8step Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
LCDSUB[4:0]—— Default —Data Name 06h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D4-0 : LCDSUB[4:0] Output current setup of BLS1 - BLS2 terminal. [00000] : 0 mA (default) [00001] : 1 mA [00010] : 2 mA [11110] : 30 mA [11111] : 31 mA * D7, D6, and D5 must not be written. The waveform of sub LCD backlights current of operation 32clk (typ26.6 s) 00000 00001 00010 00011 00100 00101 00110 00111 01000 0000001000 01000 00011 t 32clk 8step Internal luminosity set point signal * As for sub LCD backlights part, output current changes stepwise for noise reduction. * By the time it reaches current setup value, there will be delay of setup value internal 32clk. * When internal CLK stops during state transition, the state at that time is held. * The following waveform is internal signal. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
PLCNT[4:0]HIEN— Default —Data Name 07h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D5 : HIEN Current large mode ON/OFF control of PL1 - PL2 terminal. [0] : OFF (default) [1] : ON (+30 mA) D4-0 : PLCNT[4:0] Output current setup of PL1 - PL2 terminal. [00000] : 0 mA (default) [00001] : 1 mA [00010] : 2 mA [11110] : 30 mA [11111] : 31 mA The waveform of Photo flashes current of operation 32clk (typ26.6 s) 00000 00001 00010 00011 00100 00101 00110 00111 01000 0000001000 01000 00011 t 32clk 8step Internal luminosity set point signal * As for Photo flashes part, output current changes stepwise for noise reduction. * By the time it reaches current setup value, there will be delay of setup value internal 32clk. * When internal CLK stops during state transition, the state at that time is held. * The following waveform is internal signal. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
PWMCLKBLS2MBLS1MBL4MBL3MBL2MBL1M Default —Data Name 08h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D6 : BL1M The automatic ON control monitor selection bit of DC/DC converter. (BL1 terminal) [0] : Monitor of BL1 terminal is possible.(default) [1] : Monitor of BL1 terminal is impossible. D5 : BL2M The automatic ON control monitor selection bit of DC/DC converter. (BL2 terminal) [0] : Monitor of BL2 terminal is possible.(default) [1] : Monitor of BL2 terminal is impossible. D4 : BL3M The automatic ON control monitor selection bit of DC/DC converter. (BL3 terminal) [0] : Monitor of BL3 terminal is possible.(default) [1] : Monitor of BL3 terminal is impossible. D3 : BL4M The automatic ON control monitor selection bit of DC/DC converter. (BL4 terminal) [0] : Monitor of BL4 terminal is possible.(default) [1] : Monitor of BL4 terminal is impossible. D2 : BLS1M The automatic ON control monitor selection bit of DC/DC converter. (BLS1 terminal) [0] : Monitor of BLS1 terminal is possible.(default) [1] : Monitor of BLS1 terminal is impossible. D1 : BLS2M The automatic ON control monitor selection bit of DC/DC converter. (BLS2 terminal) [0] : Monitor of BLS2 terminal is possible.(default) [1] : Monitor of BLS2 terminal is impossible. D0 : PWMCLK The PWM operation clock selection bit. [0] : It operates by an internal clock. (default) [1] : It operates by an EXTCLK clock. * Interruption of address 14h is generated only in the OSCEN = High state at PWMCLK = Low. * Interruption of address 14h is generated only in the state where a clock is input into EXTCLK terminal, at PWMCLK = High Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
VIBRGB2VIBRGB1VIBMTXVIBSUB2VIBSUB1VIBPL2VIBPL1 Default VIBACTData Name 09h W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D7 : VIBACT A putting-out-lights setup of LED by VIBCTL terminal. [0] : The light is switched on at VIBCTL = Low.(default) [1] : The light is switched on at VIBCTL = High. D6 : VIBPL1 A putting-out-lights ON/OFF setup of PL1 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D5 : VIBPL2 A putting-out-lights ON/OFF setup of PL2 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D4 : VIBSUB1 A putting-out-lights ON/OFF setup of BLS1 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D3 : VIBSUB2 A putting-out-lights ON/OFF setup of BLS2 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D2 : VIBMTX A putting-out-lights ON/OFF setup of 7*7 dots matrix LED by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D1 : VIBRGB1 A putting-out-lights ON/OFF setup of R1, G1 and B1 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. D0 : VIBRGB2 A putting-out-lights ON/OFF setup of R2, G2 and B2 terminal by VIBCTL terminal. [0] : Putting-out-lights control OFF by VIBCTL terminal. (default) [1] : Putting-out-lights control ON by VIBCTL terminal. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DISRGB2DISRGB1DISMTXDISSUB2DISSUB1DISPL2DISPL1 Default LEDACTData Name 0Ah W W W DATA mode Sub Address WWWWW 00000 D0D1D2D3D4 D7 : LEDACT A putting-out-lights setup of LED by LEDCTL terminal. [0] : The light is switched on at LEDCTL = Low(default) [1] : The light is switched on at LEDCTL = High D6 : DISPL1 A putting-out-lights ON/OFF setup of PL1 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D5 : DISPL2 A putting-out-lights ON/OFF setup of PL2 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D4 : DISSUB1 A putting-out-lights ON/OFF setup of BLS1 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D3 : DISSUB2 A putting-out-lights ON/OFF setup of BLS2 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D2 : DISMTX A putting-out-lights ON/OFF setup of 7*7 dots matrix LED by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D1 : DISRGB1 A putting-out-lights ON/OFF setup of R1, G1 and B1 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. D0 : DISRGB2 A putting-out-lights ON/OFF setup of R2, G2 and B2 terminal by LEDCTL terminal. [0] : Putting-out-lights control OFF by LEDCTL terminal. (default) [1] : Putting-out-lights control ON by LEDCTL terminal. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]ON100 ON OFF ON ON ON ON PL1 control signal OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]001 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]010 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]000 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]111 0mA101 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]011 Current valueVIBPL1VIBACTVIBCTL 0mAOFF110 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]ON100 ON OFF ON ON ON ON PL1 control signal OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]001 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]010 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]000 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]111 0mA101 OFF is PLCNT[4:0] = [00000] by PLCNT[4:0]011 Current valueDISPL1LEDAC T LEDCTL * When control signal is input from both VIBCTL terminal and LEDCTL terminal, the OFF state of each PL1 terminal control signal is processed in OR logic. * Same control for VIBPL2 and PL2 terminal * Same control for VIBSUB1 and BLS1 terminal * Same control for VIBSUB2 and BLS2 terminal * Same control for VIBMTX and X0 - X6 terminal * Same control for VIBRGB1 and R1, G1 and B1 terminal * Same control for VIBRGB2 and R2, G2 and B2 terminal * Same control for DISPL2 and PL2 terminal * Same control for DISSUB1 and BLS1 terminal * Same control for DISSUB2 and BLS2 terminal * Same control for DISMTX and X0 - X6 terminal * Same control for DISRGB1 and R1, G1 and B1 terminal * Same control for DISRGB2 and R2, G2 and B2 terminal Ex.)In the case of PL1 terminal Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 10h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : GPIOCLK Change of the clock for GPIO control. [0] : It operates by an internal clock. (default) [1] : It operates by an EXTCLK clock. * At GPIOCLK = Low, register (IOFACTOR, IOSTATE, ICHAT, IOCHAT), interruption of address 2Eh, and INT terminal operate in the state of OSCEN = High. * At GPIOCLK = High, register (IOFACTOR, IOSTATE, ICHAT, IOCHAT), interruption of address 2Eh, and INT terminal operate, where clock is input into EXTCLK terminal. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 11h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1 : IOSEL1 An input/output setup of GPIO1 terminal [0] : Input (default) [1] : Output D0 : IOSEL2 An input/output setup of GPIO2 terminal [0] : Input (default) [1] : Output Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
IOMSK2IOMSK1IMSK3IMSK2IMSK1—— Default —Data Name 12h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D4 : IMSK1 GPI1 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output ISTA1 by change-of-state detection of GPI1 terminal is carried out. D3 : IMSK2 GPI2 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output ISTA2 by change-of-state detection of GPI2 terminal is carried out. D2 : IMSK3 GPI3 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output ISTA3 by change-of-state detection of GPI3 terminal is carried out. D1 : IOMSK1 GPIO1 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output IOSTA1 by change-of-state detection of GPIO1 terminal is carried out. D0 : IOMSK2 GPIO2 terminal change-of-state detection mask setup. [0] : Interruption output mask (default) [1] : Interruption output enable * The mask of the interruption detection output IOSTA2 by change-of-state detection of GPIO2 terminal is carried out. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
IOOUT2IOOUT1OOUT2OOUT1——— Default —Data Name 13h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D3 : OOUT1 An output logic setup of GPO1 terminal [0] : Output is Low (default) [1] : Output is High D2 : OOUT2 An output logic setup of GPO2 terminal [0] : Output is Low (default) [1] : Output is High D1 : IOOUT1 An output logic setup of GPIO1 terminal [0] : Output is Low (default) [1] : Output is High * Effective only at IOSEL1 = High (output mode). D0 : IOOUT2 An output logic setup of GPIO2 terminal [0] : Output is Low (default) [1] : Output is High * Effective only at IOSEL2 = High (output mode). Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
TSDCPUWRERFRMINTRAMACT——ERR2EH Default FACGD1Data Name 14h R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 D7 : FACGD1 [0] : Normal operation (default) [1] : No Read clearance D6 : ERR2EH Unusual detection of address 2Eh 0 : It is NOT unusual detection to address 2Eh. (default) 1 : It is unusual detection to address 2Eh. Read to address 2Eh. D3 : RAMACT Internal RAM access judgment 0 : RAM is NOT accessed. (default) 1 : RAM is accessed. D2 : FRMINT An one-frame display end judging scroll on display. 0 : Under a frame display (default) 1 : Frame display end D1 : CPUWRER CPU access error judgment 0 : CPU access error does NOT occur. (default) 1 : CPU access error occurs. D0 : TSD Unusual detection of TSD error. 0 : TSD unusual detection does NOT occur. (default) 1 : TSD unusual detection occurs. * The WRITE contents from CPU are not reflected in this IC at CPUWRER = High. Write from CPU again. * The interval of FACGD1 = High is maximum 1.93 s (at the internal clock operation) from the renewal time of data. * At FACGD1 = Low, if address 14h data is read, data of D0 - D6 are cleared. * RAM access from CPU cannot be performed at RAMACT = High . * When each address 14h register is set to High, the pulse in a cycle of 4 ms is output from INT. * The pulse output from INT continues an output until address 14h is read. * The pulse output from INT continues an output until address 2Eh is also read in ERR2EH = High . * The states for RAMACT = High are shown below. 1. While copying to RAM from ROM. 2. While clearing RAM Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
IOSTA2IOSTA1ISTA3ISTA2ISTA1—— Default STAGDData Name 15h R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 D7 : STAGD [0] : Normal operation (default) [1] : Data interruption disregard D4 : ISTA1 The state after chattering removal of GPI1 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D3 : ISTA2 The state after chattering removal of GPI2 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D2 : ISTA3 The state after chattering removal of GPI3 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D1 : IOSTA1 The state after chattering removal of GPIO1 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. D0 : IOSTA2 The state after chattering removal of GPIO2 terminal. [0] : The terminal state after chattering is 0. (default) [1] : The terminal state after chattering is 1. * The interval of STAGD = High is maximum 1.93 s (at internal clock operation) from the time at which data was updated. * At IOSEL1 = High or IOSEL2 = High, the data of IOOUT1 or IOOUT2 is stored. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
ICHAT3[1:0]ICHAT2[1:0]ICHAT1[1:0]— Default —Data Name 16h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D5-4 : ICHAT1[1:0] An interruption chattering processing time setup of GPI1 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms D3-2 : ICHAT2[1:0] An interruption chattering processing time setup of GPI2 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms D1-0 : ICHAT3[1:0] An interruption chattering processing time setup of GPI3 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms *The times shown above are for when the internal clock operates. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
— IOCHAT2[1:0]IOCHAT1[1:0]—— Default —Data Name 17h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D3-2 : IOCHAT1[1:0] An interruption chattering processing time setup of GPIO1 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms D1-0 : IOCHAT2[1:0] An interruption chattering processing time setup of GPIO2 terminal. [00] : 4800CLK 0 No chattering processing time (default) [01] : 4800CLK (4-1) Chattering processing time is 10.58 ms to 18.47 ms [10] : 4800CLK (9-1) Chattering processing time is 28.23 ms to 41.54 ms [11] : 4800CLK (16-1) Chattering processing time is 52.94 ms to 73.85 ms *The times shown above are for when the internal clock operates. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
— IODET[1:0] IDET[1:0]—— Default —Data Name 18h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D3-2 : IDET[1:0] The interruption detection method setup of GPI1, GPI2 and GPI3 terminal. [00] : Change-of-state detection is impossible. (default) [01] : Change of the terminal state from Low to High is detected. [10] : Change of the terminal state from High to Low is detected. [11] : Both the edge of change of a terminal state is detected. (Low High and High Low ) D1-0 : IODET[1:0] The interruption detection method setup of GPIO1 and GPIO2 terminal. [00] : Change-of-state detection is impossible. (default) [01] : Change of the terminal state from Low to High is detected. [10] : Change of the terminal state from High to Low is detected. [11] : Both the edge of change of a terminal state is detected. (Low High and High Low ) Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
IOPLUD2B2ONR2ON IOPLUD1G2ON—— Default —Data Name 19h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D4 : R2ON ON/OFF control of R2 terminal [0] : OFF (default) [1] : ON D3 : G2ON ON/OFF control of G2 terminal [0] : OFF (default) [1] : ON D2 : B2ON ON/OFF control of B2 terminal [0] : OFF (default) [1] : ON D1 : IOPLUD1 A terminal processing setup of GPIO1 terminal [0] : PULL-UP processing (default) [1] : NOT PULL-UP processing D0 : IOPLUD2 A terminal processing setup of GPIO2 terminal [0] : PULL-UP processing (default) [1] : NOT PULL-UP processing * IOPLUD1 and IOPLUD2 are effective only when IOSEL1 and IOSEL2 are input modes. * In the case of the state of IOPLUD1 = Low and IOVSEL1 = High, the power of 2.85 V cannot be applied to GPIO1. * In the case of the state of IOPLUD2 = Low and IOVSEL2 = High, the power of 2.85 V cannot be applied to GPIO2. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
IOVSEL2OVSEL2— IOVSEL1OVSEL1—— Default INTVSELData Name 1Ah W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7 : INTVSEL A terminal voltage setup of INT terminal [0] : 1.85 V (default) [1] : 2.85 V D3 : OVSEL1 A terminal voltage setup of GPO1 terminal [0] : 2.85 V (default) [1] : 1.85 V D2 : OVSEL2 A terminal voltage setup of GPO2 terminal [0] : 2.85 V (default) [1] : 1.85 V D1 : IOVSEL1 A terminal voltage setup of GPIO1 terminal [0] : 2.85 V (default) [1] : 1.85 V D0 : IOVSEL2 A terminal voltage setup of GPIO2 terminal [0] : 2.85 V (default) [1] : 1.85 V Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 20h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : MTXON An ON/OFF setup of matrix LED [0] : OFF (default) [1] : ON * During MTXON = High, subsequent ROM, RAM, and the control contents to a register are sequentially processed and lit up. * When address 08h PWMCLK is Low, set MTXON to High 5 ms after setting address 01h OSCEN to High. * When address 08h PWMCLK is High, set MTXON to High 5 ms after inputting clocks to EXTCLK terminal. * Set MTXON to High, and then set up other addresses to display the matrix part. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
MTXDATA[7:0]Data Name 21h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : MTXDATA[7:0] An address setup of ROM/RAM of the data to read [00000000] - [10010101] : ROM ( Only luminosity ) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM ( Luminosity Cycle Delay ) 7*7 pattern No. 150 to No.208 [11010001] - [11010010] : RAM ( Luminosity Cycle Delay ) 7*7 pattern RAM No.1, 2 * The pattern No.0 of ROM is all 0 data of matrix LED. * Accessing to 21h is disabled while copying from ROM to RAM (COPYSTART = High of 24h). Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 22h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : ROM77[1:0] Lighting control of the 7x7 (LED No.A1-G7) fixed pattern of ROM [00] : ROM data is displayed. [01] : ROM data is displayed by firefly lighting in 1 s. [10] : ROM data is displayed by firefly lighting in 2 s. [11] : ROM data is displayed by firefly lighting in 3 s. * During display of repetition (REPON = High), ROM77 must not be changed. A B C D EFG t t1 t3 t2 t4 t1 = t2 = t4 = 249.2 ms t3 = 265.8 ms The peak value of luminosity is a value set up by ROM. Luminosity Firefly lighting cycle : T LED’s number LED’s number Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
SELROM[7:0]Data Name 23h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : SELROM[7:0] An address setup of ROM copied to RAM. [00000000] - [10010101] : ROM (Only luminosity) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity Cycle Delay) 7*7 pattern No.150 to No.208 * Accessing to 23h is disabled while copying from ROM to RAM (COPYSTART = High of 24h). Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 24h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1 : SELRAM A RAM number setup of a copy place. 0 : RAM No.1 1 : RAM No.2 D0 : COPYSTART Copy start ON/OFF control to RAM from ROM [0] : OFF [1] : The copy set up by SELROM and SELRAM is started. (It returns to 0 by internal 51 CLK.) * Address 24h is only for copying data to RAM and never start LED display. (However, if this RAM is copied when LED display is showing, LED display is updated.) * Writing in address 21h-MTXDATA, 2Ah-SCLON, and 27h-REPON is disabled while copying. (RAMACT flag is raised.) * Accessing to SELRAM is disabled while copying from ROM to RAM (COPYSTART = High of 24h) * Don’t write address 29h (RAM-clear ) while copying. (The waiting time for 1 ms or more is required after COPYSTART.) Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
SETFROM[7:0]Data Name 25h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : SETFROM[7:0] An address setup of the ROM frame data at the repetition display start. [00000000] - [10010101] : ROM (Only luminosity) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity Cycle Delay) 7*7 pattern No.150 to No.208 * During display of repetition (REPON = High), Don’t change the setting of SETFROM. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
SETTO[7:0]Data Name 26h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : SETTO[7:0] An address setup of the ROM frame data at the repetition display end. [00000000] - [10010101] : ROM (Only luminosity) 7*7 pattern No.0 (default) to No.149 [10010110] - [11010000] : ROM (Luminosity Cycle Delay) 7*7 pattern No.150 to No.208 * During display of repetition (REPON = High), don’t change the setting of SETTO. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 27h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : REPON Repetition display ON/OFF control 0 : Repetition display OFF (default) 1 : Repetition display ON * During display of repetition, display of set-up ROM is continued. * A repetition display is started in the state of MTXON = High and REPON = High. * Accessing to 27h is disabled while copying from ROM to RAM (COPYSTART = High of 24h). * When the setting of SCLON is changed from Low to High while REPON = High, REPON becomes Low and it shifts to scroll function. * During display of repetition (REPON = High), don’t change the setting of SETFROM and SETTO. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 28h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : SETTIME[1:0] A frame display time setup of repetition display [00] : 1 s (default) [01] : 2 s [10] : 3 s [11] : 4 s Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 29h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1 : RAM1 The data in 7*7 RAM1 is cleared. 0 : Overwrite is possible. (default) 1 : The data in 7*7 RAM1 is cleared. (It returns to 0 by internal 2 CLK.) D0 : RAM2 The data in 7*7 RAM2 is cleared. 0 : Overwrite is possible. (default) 1 : The data in 7*7 RAM2 is cleared. (It returns to 0 by internal 2 CLK.) * Don’t set the RAM-clear operation for RAM1 or RAM2 during display of repetition (SCLON = High). * Don’t set the RAM-clear operation (29h) during the COPY operation (24h). (The waiting time for 1 ms or more is required after COPYSTART.) Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 2Ah W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : SCLON ON/OFF setup of scroll display 0 : OFF (default) 1 : ON * A scroll display displays the data which exists in the RAM No.1-2 of 7*7 in order of A-G column. The display travel time of a column is the preset value of SCLTIME. * During display of scroll, data can be written to RAM without specifying RAM number. (Writing is performed to empty RAM.) * A scroll display is started in the state of MTXON = High and SCLON. * Accessing to 2Ah is disabled while copying from ROM to RAM (COPYSTART = High of 24h). * When the setting of REPON is changed from Low to High while SCLON = High, SCLON becomes Low and it shifts to repetition display function. * During display of scroll (SCLON = High), don’t change the setting of RAM1 and RAM2. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 2Bh W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : SCLTIME[1:0] A frame display time setup of scroll display [00] : 0.1 s (default) [01] : 0.2 s [10] : 0.4 s [11] : 0.8 s * The display travel time of the column is the preset value of SCLTIME. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 2Ch W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D0 : RGBON ON/OFF setup of RGB lighting 0 : OFF (default) 1 : ON * When address 08h PWMCLK is Low, set RGBON to High 5 ms after setting address 01h OSCEN to High. * When address 08h PWMCLK is High, set RGBON to High 5 ms after inputting clocks to EXTCLK terminal. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
RGBDATA— Default —Data Name 2Dh W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-0 : RGBDATA[5:0] An address setup of ROM and register which read RGB data [000000] : Register is displayed. [000001] - [101010] : ROM (RGB pattern, Luminosity Cycle Delay) pattern No.1 to No.42 Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
IOFAC2IOFAC1IFAC3IFAC2IFAC1OVPSCP Default FACGD2Data Name 2Eh R R R DATA mode Sub Address RRRRR 00000 D0D1D2D3D4 D7 : FACGD [0] : Normal operation (default) [1] : No read clearance D6 : SCP An interruption factor register when short comparator operates while the DC/DC converter operated. [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D5 : OVP An interruption factor register when over-voltage detection comparator operates while the DC/DC converter operated. [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D4 : IFAC1 The interruption factor register of GPI1 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D3 : IFAC2 The interruption factor register of GPI2 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D2 : IFAC3 The interruption factor register of GPI3 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D1 : IOFAC1 The interruption factor register of GPIO1 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. D0 : IOFAC2 The interruption factor register of GPIO2 terminal [0] : An interrupt does NOT occur. (default) [1] : An interrupt occurs. * The interval of FACGD2 = High is maximum 1.93 s (at internal clock operation) from the renewal time of data. * At FACGD2 = Low, if the data of address 2Eh is read, data of D0 - D6 are cleared. * Only at IOSEL1 = Low or IOSEL2 = Low, an interruption factor is generated. * In the case of IOSEL1 = High or IOSEL2 = High, status and register in chattering removal circuit is reset. * When each address 2Eh register is set to High, the pulse in a cycle of 4 ms is output from INT. * The pulse output from INT continues an output until address 14h is read. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 30h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D1-0 : RAMNUM[1:0] A RAM number setup at the CPU access (READ and WRITE). 0 : RAM No.1 1 : RAM No.2 * Accessing to 30h is disabled during display of scroll (2Ah SCLON = High). Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DLA1[1:0]FRA1[1:0] Default BLA1[1:0]Data Name 31h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-4 : BLA1[1:0] Luminosity setup of LED No.A1 [0000] : 0 mA (default) [0001] : 1 mA [0010] : 2 mA [0011] : 3 mA [0100] : 4 mA [0101] : 5 mA [0110] : 8 mA [0111] : 11 mA [1000] : 15 mA [1001] : 17 mA [1010] : 19 mA [1011] : 21 mA [1100] : 24 mA [1101] : 26 mA [1110] : 28 mA [1111] : 30 mA D3-2 : FRA1[1:0] Firefly operation and cycle setup of the LED No.A1 [00] : Lighting mode (default) [01] : Firefly lighting cycle 1 s [10] : Firefly lighting cycle 2 s [11] : Firefly lighting cycle 3 s D1-0 : DLA1[1:0] Firefly operation delay setup of the LED No.A1 [00] : No delay (default) [01] : Delay 25 % [10] : Delay 50 % [11] : Delay 75 % * The operation is the same as above for the addresses to 61h corresponding to each LED number. * The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 31h to 61h is written in. Please input other serial commands after that. A B C D EFG LED’s number LED’s number Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DLLEDR1[1:0]FRLEDR1[1:0] Default BLLEDR1[1:0]Data Name 62h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 D7-4 : BLLEDR1[1:0] Luminosity setup of R1 terminal [0000] : 0 mA (default) [0001] : 1 mA [0010] : 2 mA [1110] : 14 mA [1111] : 15 mA D3-2 : FRLEDR1[1:0] Firefly operation and cycle setup of R1 terminal [00] : Lighting mode (default) [01] : Firefly lighting cycle 1 s [10] : Firefly lighting cycle 2 s [11] : Firefly lighting cycle 3 s D1-0 : DLLEDR1[1:0] Firefly operation delay setup of R1 terminal [00] : No delay (default) [01] : Delay 25 % [10] : Delay 50 % [11] : Delay 75 % * The operation is the same as above for the addresses to 67h corresponding to G1 and B1 terminal. * The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 62h to 64h is written in. Please input other serial commands after that. Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
—Data Name 6Bh W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 6BhD0(PROT1), 6DhD4(PROT2), 6FhD7(PROT3) * Please don’t access to address 6Bh to 6Fh. * Addresses to 77h are for test. * When all the three above bits are set to High, it is allowed to write in Addresses [ 70h - 77h ]. (For test. Do not setup these addresses.) D7-0 : TEST1[7:0] The register for test * Addresses to 77h are for test. * Please don’t access to address 70h to 77h. Default —Data Name 6Dh W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 Default PROT3Data Name 6Fh W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 Default TEST1[7:0]Data Name 70h W/R W/R W/R DATA mode Sub Address W/RW/RW/RW/RW/R 00000 D0D1D2D3D4 Register map detailed explanation (continued) OPERATION (continued) 4. Register and Address (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
The interface with microcomputer consists of 16 bit-serial register (8-bit of command, 8-bit of address), and address decoder and transmitting register (8-bit). Serial interface consists of four terminals of serial clock terminal (CLK), serial-data input terminal (DI), serial- data output terminal (DO), and chip enable input terminal (CE). CLK DI W D0D1D2D3D4D5D6D7A0A1A2A3A4A5A6 CE DO Hi-Z CLK DO CE DI D0D1D2D3D4D5D6D7 RA 0 A1A2A3A4A5A6 Hi-ZHi-Z (1) Reception operation Data is taken into internal shift register by the rising edge of CLK. (A maximum of 13 MHz of frequency of CLK can be used) In High interval of CE, reception of data becomes ENABLE. (active : High) Data is transmitted at MSB first in order of a control register address (8-bit) and control command (8-bit). Timing of reception (2) Transmission operation Data is taken into internal shift register by the rising edge of CLK. (A maximum of 6 MHz of frequency of CLK can be used) * It is not possible to read RAM data. In High interval of CE, reception of data becomes ENABLE. (active : High) Data is transmitted at MSB first in order of a control register address (8-bit) and control command (max 8-bit). Timing of transmission SPI1 format OPERATION (continued) 5. Serial interface format Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Power supply distribution diagram OPERATION (continued) 6. Signal distribution diagram Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Oscillator 1.2MHz Selector (PAD) EXTCLK (Register) PWMCLK Selector (Register) GPIOCLK REGMAP GPIO Matrix RGB * Step change of states of output current 05h LCDMAIN 06h LCDSUB 07h PLCNT * Matrix, RGB operation PWM control Read / Write of memory data (ROM and RAM) 14h RAMACT, FRMINT, CPUWRER * GPIO operation 4 ms sampling control 4 ms pulse control of interruption 14h interruption generating 2Eh interruption generating SPI1 (PAD) CLK (PAD) CSB (PAD) DI Selector (Register) SERSEL (PAD) GPI1 SPI2 (PAD) GPI2 (PAD) GPI3 BLSCLK BLSDAT BLSCE (PAD) DO *S e r i a l ⇔ Parallel conversion SCLK Serial ⇔ Parallel conversion (input) SCLK_N Parallel Serial conversion (output) REGCLK Serial Parallel conversion output is latched in a standup. * Serial ⇔ Parallel conversion Only 05h BLSCLK Serial Parallel conversion (input) REGCLK2 Serial Parallel conversion output is latched in a standup. SCLK SCLK_N REGCLK REGCLK2 Control / Clock distribution diagram OPERATION (continued) 6. Signal distribution diagram (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
DLA1[1:0]FRA1[1:0]BLA1[1:0] 000000 01 DLA1[1:0]FRA1[1:0]BLA1[1:0] 011110 01 DLA1[1:0]FRA1[1:0]BLA1[1:0] 001110 11 DLA1[1:0]FRA1[1:0]BLA1[1:0] 101110 11 33 mA t Firefly lighting cycle T2 = 2.0268 s FRA1 = [10] DLA1 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms 19 mA t Firefly lighting cycle T = 1.0134 s FRA1 = [01] 33 mA t Firefly lighting cycle T2 = 2.0268 s FRA1 = [10] BLA1 = [1000] BLA1 = [1111] t 33 mA BLA1 = [1111] BLA1 = [1111] Example of initial setting for lighting Current value Serial ON Firefly lighting setup 1 s Current value Serial ON Serial ON Serial ON Current value Current value Change to cycle 1 s to 2 s Change to delay 0 25 % Example of firefly lighting 1 OPERATION (continued) 7. Example of firefly lighting Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
t Firefly lighting cycle T1 = 3.0402 s FRA1 = [11] t1 t3t2 t4 t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms BLA1A1 t Firefly lighting cycle T2 = 2.0268s FRC5 = [10] BLC5C5 t Firefly lighting cycle T3 = 1.0134 s FRF3 = [01] t9 = t10 = t12 = 249.2 ms t11 = 265.8 ms BLF3 DLC5 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms DLF3 = [10] t10 t11 t12 t Firefly lighting cycle T1 = 3.0402 s FRE7 = [11] t1 t3t2 t4 BLE7E7 DLE7 = [11] t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms Luminosity Luminosity Luminosity Luminosity Example of firefly lighting 2 OPERATION (continued) 7. Example of firefly lighting (continued) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
PACKAGE INFORMATION ( Reference Data ) Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
- When using the LSI for new models, verify the safety including the long-term reliability for each product. 2. When the application system is designed by using this LSI, please confirm the notes in this book. Please read the notes to descriptions and the usage notes in the book. 3. This LSI is intended to be used for general electronic equipment. Consult our sales staff in advance for information on the following applications: Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this LSI may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (1) Space appliance (such as artificial satellite, and rocket) (2) Traffic control equipment (such as for automobile, airplane, train, and ship) (3) Medical equipment for life support (4) Submarine transponder (5) Control equipment for power plant (6) Disaster prevention and security device (7) Weapon (8) Others : Applications of which reliability equivalent to (1) to (7) is required Our company shall not be held responsible for any damage incurred as a result of or in connection with the LSI being used for any special application, unless our company agrees to the use of such special application. 4. This LSI is neither designed nor intended for use in automotive applications or environments unless the specific product is designated by our company as compliant with the ISO/TS 16949 requirements. Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in connection with the LSI being used in automotive application, unless our company agrees to such application in this book. 5. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of control led substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage incurred as a result of our LSI being used by our customers, not complying with the applicable laws and regulations. 6. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it migh t emit smoke or ignite. 7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins . In addition, refer to the Pin Description for the pin configuration. 8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as solder-bridge between the pins of the semiconductor device. Also, perform full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 9. Take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short). Safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not w ork during normal operation. Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be damaged before the thermal protection circuit could operate. 11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damaged, which could happen due to negative voltage or exce ssive voltage generated during the ON and OFF timing when the inductive load of a motor coil or actuator coils of op tical pick-up is being driven. 12. Verify the risks which might be caused by the malfunctions of external comp onents. 13. Due to the unshielded structure of this LSI, functions and characteristics of the product cannot be guaranteed under the exposure of light. During normal operation or even under testing condition, please ensure that the LSI is not exposed to light . 14. Please ensure that your design does not have metal shield parts touching the chip surface as the surface potential is GND voltage. 15. Pay attention to the breakdown voltage of this LSI when using. More than + 1500 V or less than – 1500 V electrostatic discharge to all the pins might damage this product. Doc No. TA4-EA-04511 Revision. Established 2006-08-29 Revised 2013-04-01
Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) The products and product specifications described in this book are subject to change without notice for modification and/or im- provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202