AN2546FH-A

DATASHEET SEARCH SITE

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 29

Technical content

Publication date: February 2003 SDB00081BEB AN2546FH-A Automotive LCD TV signal processor IC ■ Overview The AN2546FH-A is a video signal processing IC built-in a 5-volt power-supply source driver for TFT color LCD (normally white type), and it supports the NTSC, PAL and PAL-M/PAL-N systems. The main circuitry of this IC includes video-signal processing circuit, color sig- nal processing circuit, interface circuit, synchronizing cir- cuit and many color quality adjusting circuits. This IC con- verts the composite video signal or separated Y/C signal or RGB signals into RGB signals available for TFT color LCD. ■ Features

• Supply voltage: 3 V/5 V/7.5 V
• Built-in a 5-volt power-supply source driver for TFT type LCD
• Low consumption power (typ. 200 mW)
• Supporting the NTSC, PAL, PAL-M and PAL-N sys- tems
• Supporting composite, component and color differen- tial signal input
• Video signal, analog RGB (2 systems) One is for OSD (analog/digital).
• Each mode setting is possible with I 2C Bus control.
• Electronic volume (D/A converter) built in
• Contrast/Brightness/γ correction circuit built in
• Horizontal and vertical display position adjustment are possible by serial control.
• Improvement of weak electric field characteristics (Compared to AN2526FH/AN2526NFH: −5 dB)
• At reverse stop, built-in output gain down function ■ Applications
• 4 inches to 7 inches middle size TFT LCD equipment of normally white, of such as an in-car TV and an LCD monitor for car navigation system. QFP064-P-1010 Unit: mm 10.00±0.20 48 33 161 12.00±0.20 10.00±0.20 0.10±0.10 (1.25) (1.25) 0.50 0.18 +0 1 0 05 0.15 +0.10 –0.05 Seating plane (1.00) 0.50±0.20 0° to 10° Note) The package of this product will be changed to lead-free type (QFP064-P-1010A). See the new package dimensions section later of this datasheet.

■ Application Circuit Examples 1. Composite signal input 64PAL or PAL-M PAL-N SDATA SCLCK GND2NAVI sync. V CC1 (5.0 V) VSS POL VDD NRGB L-det. Sync. in R-Y out NTSC APC det. ACC det. Y-det. Y-in C-in Kill det. GND3 VCC1 (5.0 V) SC out 5.1 kΩ 2 kΩ 330 kΩ 1 kΩ 15 kΩ 68 kΩ 330 Ω Composite signal 1 µF 15 µF 0.02 µF 0.1 µF 28VCOM VCC1 (5.0 V) VREF PWM LogicLogicLogicLogic Clamp Delay Sharpness APC Tint KillerVXO gene. VXO BPF Sync. cut SW ACC det. ACC amp. YUV SW GCA Bright Reg. R-Y , B-Y DEMOD DAC DAC Reg. I2C Bus VCO 1/nSync. sepa. HHKILL VSYNC drop Vert. count Phase comp. f det. GCA B-Y out B-Y in R-Y in G-Y gene. Matrix Int./Ext. SW Clamp. OSD SW Contrast Gamma Invert Limit 0.1 µF 0.1 µF 4.7 µF NTSC = 39 pF PAL = 27 pF 47 µH PONR COM DC SECAM black level adj. 2.2 µF 33 kΩ 10 µF 4.7 µF 1 500 pF VCC1 VCC3 15 µF 47 µH Be sure to attach a power supply filter to a power supply pin. Power supply pin Recommended crystal oscillator NTSC: VSX0160 (KINSEKI, Limited) PAL: VSX0162 (KINSEKI, Limited) 1 µF YS BLAK B-out B-out det. R-det. 1 µF G-det. 1 µF B-det. 2.2 µF R-in1 G-in1 B-in1 R-in2 G-in2 B-in2 G-out VCOM PWM VD HD SCP R-out G-out det. GND1 2.2 µF R-out det.2.2 µF VCC2 (7.5 V) VCC3 (3.0 V) 0.01 µF 0.02 µF 15 µF 0.022 µF0.47 µF 82 kΩ C-sync.AFC det. 50 kΩ 1 MΩ 3.3 kΩ10 kΩ 100 kΩ 680 pF

• C coupling input in an analog OSD mode.
• Connect to GND in case of no use in a digital OSD mode.

■ Application Circuit Examples (continued) 2. Component signal input 64PAL or PAL-M PAL-N SDATA SCLCK GND2NAVI sync. V CC1 (5.0 V) VSS POL VDD NRGB L-det. Sync. in R-Y out NTSC APC det. ACC det. Y-det. Y-in C-in Kill det. GND3 VCC1 (5.0 V) SC out 5.1 kΩ 330 kΩ 1 kΩ 15 kΩ 68 kΩ 330 Ω Brightness and syncronous signal 1 µF 15 µF 0.02 µF 0.1 µF 28VCOM VCC1 (5.0 V) VREF PWM LogicLogicLogicLogic Clamp Delay Sharpness APC Tint KillerVXO gene. VXO BPF Sync. cut SW ACC det. ACC amp. YUV SW GCA Bright Reg. R-Y , B-Y DEMOD DAC DAC Reg. I2C Bus VCO 1/nSync. sepa. HHKILL VSYNC drop Vert. count Phase comp. f det. GCA B-Y out B-Y in R-Y in G-Y gene. Matrix Int./Ext. SW Clamp. OSD SW Contrast Gamma Invert Limit 0.1 µF 0.1 µF 4.7 µF PONR COM DC SECAM black level adj. 2.2 µF 33 kΩ 10 µF 4.7 µF 1 500 pF VCC1 VCC3 1 µF YS BLAK B-out B-out det. R-det. 1 µF G-det. 1 µF B-det. 2.2 µF R-in1 G-in1 B-in1 R-in2 G-in2 B-in2 G-out VCOM PWM VD HD SCP R-out G-out det. GND1 2.2 µF R-out det.2.2 µF VCC2 (7.5 V) VCC3 (3.0 V) 0.01 µF 0.02 µF 15 µF 0.022 µF0.47 µF 82 kΩ C-sync.AFC det. 50 kΩ 1 MΩ 3.3 kΩ10 kΩ 100 kΩ 680 pF 15 µF 47 µH Power supply pin

• C coupling input in an analog OSD mode.
• Connect to GND in case of no use in a digital OSD mode. Be sure to attach a power supply filter to a power supply pin. Recommended crystal oscillator NTSC: VSX0160 (KINSEKI, Limited) PAL: VSX0162 (KINSEKI, Limited)

■ Application Circuit Examples (continued) 3. Analog RGB signal input 64PAL or PAL-M PAL-N SDATA SCLCK GND2NAVI sync. V CC1 (5.0 V) VSS POL VDD NRGB L-det. Sync. in NTSC GND3 VCC1 (5.0 V) 330 kΩ 1 kΩ 15 kΩ 68 kΩ 330 Ω Synchronous signal 15 µF 28VCOM VCC1 (5.0 V) VREF PWM LogicLogicLogicLogic Clamp Delay Sharpness APC Tint KillerVXO gene. VXO BPF Sync. cut SW ACC det. ACC amp. YUV SW GCA Bright Reg. R-Y , B-Y DEMOD DAC DAC Reg. I2C Bus VCO 1/nSync. sepa. HHKILL VSYNC drop Vert. count Phase comp. f det. GCA G-Y gene. Matrix Int./Ext. SW Clamp. OSD SW Contrast Gamma Invert Limit PONR COM DC SECAM black level adj. 2.2 µF 33 kΩ 10 µF 4.7 µF 1 500 pF VCC1 VCC1 Required only when not using crystal oscillators. VCC3 4.7 µF 4.7 µF 4.7 µF 1 µF YS BLAK B-out B-out det. R-det. 1 µF G-det. 1 µF B-det. 2.2 µF R-in1 G-in1 B-in1 R-in2 G-in2 B-in2 G-out VCOM PWM VD HD SCP R-out G-out det. GND1 2.2 µF R-out det.2.2 µF VCC2 (7.5 V) VCC3 (3.0 V) 0.01 µF 0.02 µF 15 µF 0.022 µF 0.47 µF 82 kΩ C-sync.AFC det. 50 kΩ 1 MΩ 3.3 kΩ 510 kΩ 510 kΩ 10 kΩ 100 kΩ 680 pF Possible to change the synchronous signal input pin according to the channnel 10 value. Possible to input to pin 45 by 3 V[p-p] positive polarity pulse. 15 µF 47 µH Power supply pin Apply a half VCC1 voltage to pin 42 according to resistance division when not connecting crystal oscillators.

• C coupling input in an analog OSD mode.
• Connect to GND in case of no use in a digital OSD mode. Be sure to attach a power supply filter to a power supply pin. Recommended crystal oscillator NTSC: VSX0160 (KINSEKI, Limited) PAL: VSX0162 (KINSEKI, Limited)

■ Pin Descriptions Pin No. Description

1 Crystal oscillator connecting pin 3 (PAL-N)

2 R-Y output pin

3 B-Y output pin

4 R-Y input pin

5 B-Y input pin

6 Signal processing system power supply

(VCC1 = 5.0 V)

7 Internal reference power supply detection

pin (2.0 V) 8 R-ch. analog signal input pin 9 G-ch. analog signal input pin 10 B-ch. analog signal input pin 11 R-ch. clamp detection pin 12 G-ch. clamp detection pin 13 B-ch. clamp detection pin 14 R-ch. OSD input pin 15 G-ch. OSD input pin 16 B-ch. OSD input pin

17 Character picking up pulse input pin

18 Side black control signal input pin

19 B-ch. output pin 20 B-ch. output DC feedback detection pin 21 G-ch. output pin 22 G-ch. output DC feedback detection pin

23 GND 1

24 Drive output reference voltage input pin

25 Drive system power supply (V CC2 = 7.5 V) 26 R-ch. output pin 27 R-ch. output DC feedback detection pin

28 Common reverse signal output pin

29 Pulse output system power supply

(VCC3 = 3.0 V)

30 PWM output pin

31 Vertical synchronous signal output pin

32 Horizontal synchronous signal output pin

Pin No. Description

33 Sand castle pulse output pin

34 Composite synchronous signal output pin

35 Vertical synchronous signal input pin

36 1H reverse signal input pin

37 Clock-system GND (V SS)

38 Analog imposing control signal input pin

39 Horizontal clock detection pin

40 Clock-system power supply (3.0 V)

41 GND 2

42 AFC loop filter connecting pin

43 VCO frequency adjustment pin

44 Synchronous system power supply

(VCC1 = 5.0 V)

45 NAVI signal synchronous signal input pin

46 Synchronous signal input pin

47 Serial data shift clock input pin

48 Serial data input pin

49 Power-on reset detection pin

50 Common DC adjustment voltage output pin

51 DAC output pin

52 Luminance signal input pin

53 Chrominance signal trap filter connection pin 1

54 Chrominance signal trap filter connection pin 2

55 Y-system clamp detection pin

56 ACC detection pin

57 Chrominance signal input pin

58 Chrominance processing system power supply

(VCC1 = 5.0 V)

59 GND 3

60 Chrominance killer detection pin

61 APC detection pin

62 Subcarrier output pin

63 Crystal oscillator connecting pin 1 (NTSC)

64 Crystal oscillator connecting pin 2

(PAL/PAL-M)

■ Recommended Operating Range ■ Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage V CC1 5.5 V VCC2 8.5 VCC3 5.2 Supply current I CC  mA Power dissipation *2 PD 423 mW Operating ambient temperature *1 Topr −30 to +85 °C Storage temperature *1 Tstg −55 to +150 °C Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for T a = 25°C. *2: The power dissipation shown is the value in free air for T opr = 85°C. Parameter Symbol Range Unit Supply voltage V CC1 4.7 to 5.3 V VCC2 7.0 to 8.0 VCC3 2.7 to 3.3 Parameter Symbol Conditions Min Typ Max Unit DC VCC1-system current consumption I TOTAL1 Refer to product standards 32  44 mA VCC2-system current consumption I TOTAL2 Refer to product standards 1.0  9.0 mA VCC3-system current consumption I TOTAL3 Refer to product standards  2.0 mA Chrominance system R-Y standard gain G RY Refer to product standards 9.0  15 dB R-Y/G-Y relative gain G RYGY Refer to product standards −5.0 − 1.0 dB B-Y standard gain G BY Refer to product standards 9.0  15 dB B-Y/G-Y relative gain G BYGY Refer to product standards −15 − 9.0 dB High-level APC pull-in AP H Refer to product standards 500  540 Hz Low-level APC pull-in AP L Refer to product standards −540 − 500 Hz ACC output characteristic 1 G ACC1 Refer to product standards −1.0  1.0 dB ACC output characteristic 2 G ACC2 Refer to product standards −1.0  1.0 dB Chrominance killer characteristic 1 V KILL1 Refer to product standards 400  mV[p-p] Chrominance killer characteristic 2 V KILL2 Refer to product standards  600 mV[p-p] Subcarrier amplitude SCV Refer to product standards 400  mV[p-p] Y-system Sharpness control characteristic G SH Refer to product standards 1.0  dB Sharpness frequency characteristic 1 f SH1 Refer to product standards 4.0  dB R-ch. contrast adjustment range 1 CTR R1 Refer to product standards 1.5  dB ■ Electrical Characteristics at Ta = 25°C

■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) G-ch. contrast adjustment range 1 CTR G1 Refer to product standards 1.5  dB B-ch. contrast adjustment range 1 CTR B1 Refer to product standards 1.5  dB R-ch. contrast adjustment range 2 CTR R2 Refer to product standards  − 2.5 dB G-ch. contrast adjustment range 2 CTR G2 Refer to product standards  − 2.5 dB B-ch. contrast adjustment range 2 CTR B2 Refer to product standards  − 2.5 dB R-ch. pedestal amplitude minimum V PEDRmin Refer to product standards  2.0 V[p-p] G-ch. pedestal amplitude minimum V PEDGmin Refer to product standards  2.0 V[p-p] B-ch. pedestal amplitude minimum V PEDBmin Refer to product standards  2.0 V[p-p] R-ch. pedestal amplitude maximum VPEDRmax Refer to product standards 3.0   V[p-p] G-ch. pedestal amplitude maximum VPEDGmax Refer to product standards 3.0   V[p-p] B-ch. pedestal amplitude maximum VPEDBmax Refer to product standards 3.0   V[p-p] G-ch. output DC voltage V GDC Refer to product standards 2.35  2.85 V[p-p] R-ch. gamma characteristic 1 G GAMR1 Refer to product standards −9.0  −3.0 dB G-ch. gamma characteristic 1 G GAMG1 Refer to product standards −9.0  −3.0 dB B-ch. gamma characteristic 1 G GAMB1 Refer to product standards −9.0  −3.0 dB R-ch. gamma characteristic 2 G GAMR2 Refer to product standards −8.0   dB G-ch. gamma characteristic 2 G GAMG2 Refer to product standards −8.0   dB B-ch. gamma characteristic 2 G GAMB2 Refer to product standards −8.0   dB R-ch. gamma characteristic 3 G GAMR3 Refer to product standards −5.0  0d B G-ch. gamma characteristic 3 G GAMG3 Refer to product standards −5.0  0d B B-ch. gamma characteristic 3 G GAMB3 Refer to product standards −5.0  0d B R-ch. white limiter high-level V WRRH Refer to product standards  3 . 0 V[p-p] G-ch. white limiter high-level V WRGH Refer to product standards  3 . 0 V[p-p] B-ch. white limiter high-level V WRBH Refer to product standards  3 . 0 V[p-p] R-ch. white limiter low-level V WRRL Refer to product standards 3.2  V[p-p] G-ch. white limiter low-level V WRGL Refer to product standards 3.2  V[p-p] B-ch. white limiter low-level V WRBL Refer to product standards 3.2  V[p-p] R-ch. black limiter low-level V BRRL Refer to product standards 3.0  V G-ch. black limiter low-level V BRGL Refer to product standards 3.0  V B-ch. black limiter low-level V BRBL Refer to product standards 3.0  V R-ch. black limiter high-level V BRRH Refer to product standards  2.7 V G-ch. black limiter high-level V BRGH Refer to product standards  2.7 V B-ch. black limiter high-level V BRBH Refer to product standards  2.7 V R-ch. YS threshold 1 V tYSR1 Refer to product standards 0.8  V[p-p] G-ch. YS threshold 1 V tYSG1 Refer to product standards 0.8  V[p-p] B-ch. YS threshold 1 V tYSB1 Refer to product standards 0.8  V[p-p]

■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) R-ch. YS threshold 2 V tYSR2 Refer to product standards  0.5 V[p-p] G-ch. YS threshold 2 V tYSG2 Refer to product standards  0.5 V[p-p] B-ch. YS threshold 2 V tYSB2 Refer to product standards  0.5 V[p-p] R-ch. black level CHR RB Refer to product standards −1.0  1.0 V G-ch. black level CHR GB Refer to product standards −1.0  1.0 V B-ch. black level CHR BB Refer to product standards −1.0  1.0 V R-ch. black level width WCHRRB Refer to product standards 2.0  4.0 µs G-ch. black level width WCHRGB Refer to product standards 2.0  4.0 µs B-ch. black level width WCHRBB Refer to product standards 2.0  4.0 µs R-ch. CHR threshold 1 V tCHR1 Refer to product standards 1.5  V[p-p] G-ch. CHR threshold 1 V tCHG1 Refer to product standards 1.5  V[p-p] B-ch. CHR threshold 1 V tCHB1 Refer to product standards 1.5  V[p-p] R-ch. CHR threshold 2 V tCHR2 Refer to product standards 3.0  V[p-p] G-ch. CHR threshold 2 V tCHG2 Refer to product standards 3.0  V[p-p] B-ch. CHR threshold 2 V tCHB2 Refer to product standards 3.0  V[p-p] R-ch. white level CHR RW Refer to product standards 2.0  V[p-p] G-ch. white level CHR GW Refer to product standards 2.0  V[p-p] B-ch. white level CHR BW Refer to product standards 2.0  V[p-p] R-ch. white level width WCHRRW Refer to product standards 2.0  4.0 µs G-ch. white level width WCHRGW Refer to product standards 2.0  4.0 µs B-ch. white level width WCHRBW Refer to product standards 2.0  4.0 µs R-ch. RGB2 relative amplitude V RGB2R Refer to product standards − 0.45  0.45 V[p-p] B-ch. RGB2 relative amplitude V RGB2B Refer to product standards − 0.45  0.45 V[p-p] Synchronous system Horizontal sync. pulse low-level V HDL Refer to product standards  0.4 V Horizontal sync. pulse amplitude V HD Refer to product standards 2.4  V[p-p] Horizontal sync. pulse width t HD Refer to product standards 3.6  6.0 µs Vertical sync. pulse low-level V VDL Refer to product standards  0.4 V Vertical sync. pulse amplitude V VD Refer to product standards 2.4  V[p-p] Horizontal sync. separation pulse V HSSH SG2 (NTSC) 2.4  V high-level Horizontal sync. separation pulse V HSS SG2 (NTSC) 2.4  V[p-p] amplitude Horizontal sync. separation pulse t HSS SG2 (NTSC) 3.6  6.0 µs width

■ Terminal Equivalent Circuits Pin No. Equivalent circuit Description Voltage · Waveform

1 VXO3: 

PAL-N crystal oscillator con- necting pin Use the capacitor with tem- perature characteristics (N750) to connect to the crystal oscillator.

2 R-Y out: R-Y signal

Output pin of R-Y signal de- modulated from video signal

3 B-Y out: B-Y signal

Output pin of B-Y signal de- modulated from video signal

4 R-Y in: R-Y signal

R-Y signal input pin in a color difference mode and in the standard PAL Pin 58 VCC1 Pin 59 GND 190 Ω 1 kΩ Pin 58 VCC1 Pin 59 GND 2 kΩ Pin 58 VCC1 Pin 59 GND 2 kΩ Pin 58 VCC1 Pin 59 GND Pin 7 V REF 5 kΩ 5 kΩ 5 kΩ 17.5 kΩ 5 kΩ 5 kΩ 2 kΩ

■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage · Waveform

5 B-Y in: B-Y signal

B-Y signal input pin in a color difference mode and in the standard PAL6V CC1:  Drive block 5.0 V-system power supply pin 7V REF:  Reference voltage output pin 2.0 V typ.

8 R-in 1: Analog R signal

9 G-in 1: Analog G signal

V REF 5 kΩ 5 kΩ 5 kΩ 17.5 kΩ 5 kΩ 5 kΩ 2 kΩ 60 Ω Pin 6 VCC1 Pin 23 GND 200 Ω 30 kΩ 26 kΩ 1 kΩ 5 kΩ Pin 6 VCC1 Pin 7 VREF Pin 23 GND

0.7 V[p-p]

typ. 5 kΩ Pin 6 VCC1 Pin 7 VREF Pin 23 GND typ.

Pin No. Equivalent circuit Description Voltage · Waveform

10 B-in 1: Analog B signal

11 R-ch. det.:  R-ch. clamping capacitor coupling pin 12 G-ch. det.:  G-ch. clamping capacitor coupling pin 13 B-ch. det.:  B-ch. clamping capacitor coupling pin ■ Terminal Equivalent Circuits (continued) 5 kΩ Pin 6 VCC1 Pin 7 VREF Pin 23 GND 1 kΩ 1 kΩ Pin 6 VCC1 Pin 23 GND 500 Ω HSS typ. 1 kΩ 1 kΩ Pin 6 VCC1 Pin 23 GND 500 Ω HSS 1 kΩ 1 kΩ Pin 6 VCC1 Pin 23 GND 500 Ω HSS

Pin No. Equivalent circuit Description Voltage · Waveform

14 R-in 2: Analog OSD

Character insertion signal in- put for R-ch., supporting ana- log and digital OSD Digital OSD

15 G-in 2: Analog OSD

Character insertion signal in- put for G-ch., supporting analog and digital OSD Digital OSD

16 B-in 2: Analog OSD

Character insertion signal in- put for B-ch., supporting ana- log and digital OSD Digital OSD

17 Y S:

Character picking up signal input

18 BLAK:

Black level indication con- trol signal input pin ■ Terminal Equivalent Circuits (continued) 5 kΩ Pin 6 VCC1 Pin7 VREF Pin 23 GND Digital OSD circuit 5 kΩ Pin 6 VCC1 Pin7 VREF Pin 23 GND Digital OSD circuit 5 kΩ Pin 6 VCC1 Pin7 VREF Pin 23 GND Digital OSD circuit 15 kΩ 100 kΩ Pin 23 GND 10 kΩ 15 kΩ 100 kΩ Pin 23 GND 10 kΩ typ. VDD GND typ. VDD GND typ. VDD GND VDD GND VDD GND

Pin No. Equivalent circuit Description Voltage · Waveform

19 B-out:

20 B-ch. AVE det.:  B-ch. output DC feedback detection pin

21 G-out:

22 G-ch. AVE det.:  G-ch. output DC feedback detection pin 23  GND 1:  Drive circuits system GND ■ Terminal Equivalent Circuits (continued) 100 Ω Pin 25 VCC2 Pin 6 VCC1 Pin 23 GND16 kΩ 2 kΩ 100 kΩ Pin 6 VCC1 Pin 23 GND 100 Ω Pin 25 VCC2 Pin 6 VCC1 Pin 23 GND16 kΩ 2 kΩ 100 kΩ Pin 6 VCC1 Pin 23 GND

Pin No. Equivalent circuit Description Voltage · Waveform

24 AVE : 

R,G,B output DC reference voltage pin 25  VCC2: 

7.5 V system power supply

26 R-out:

27 R-ch. AVE det.: R-ch. output DC feedback detection pin

28 Common out:

Voltage output pin for common. Output impedance; Approx. 150 Ω ■ Terminal Equivalent Circuits (continued) 100 kΩ Pin 6 VCC1 Pin 23 GND 8 kΩ 2 kΩ 100 kΩ 100 Ω Pin 25 VCC2 Pin 6 VCC1 Pin 23 GND16 kΩ 2 kΩ 100 kΩ Pin 6 VCC1 Pin 23 GND ch.1 ch.1 Pin 25 VCC2 Pin 23 GND 100 kΩ 15 kΩ 200 Ω

Pin No. Equivalent circuit Description Voltage · Waveform 29  VCC3:  Logic output circuits system power supply 3.0 V typ.

30 PWM: Output waveform

31 VD: Output waveform

Vertical synchronous signal output pin

32 HD: Output waveform

Horizontal synchronous sig- nal output pin

33 SCP out:

Sand castle pulse output pin

34 HSS: Output waveform

Composite synchronous sig- nal output pin ■ Terminal Equivalent Circuits (continued) Pin 29 VCC3 Pin 23 GND Pin 37 VSS 0 V VCC3 Pin 29 VCC3 Pin 23 GND Pin 37 VSS 0 V VCC3 Pin 29 VCC3 Pin 23 GND Pin 37 VSS 0 V VCC3 100 Ω 100 Ω 41.3 kΩ Pin 44 VCC1 Pin 41 GND 350 Ω

2.0 V[p-p]

typ.

4.0 V[p-p]

typ. Burst time Vertical/Horizontal blanking time Pin 29 VCC3 Pin 23 GND Pin 37 VSS 0 V VCC3

Pin No. Equivalent circuit Description Voltage · Waveform

35 VDB in: High or Low

Vertical synchronous pulse input pin 36 Ext. pol.: High or Low 1H reverse signal input pin 37  VSS : MOS system GND 

38 PRGB: High or Low

Mode start-up signal input pin Valid only in the analog OSD mode High = Analog OSD start up

39 LDET: 

Capacitor coupling pin for the horizontal unlock detect- ing circuit 40  VDD:  Capacitor connection pin for MOS part power supply 3.0 V typ. 41  GND 2: Pulse system GND  42 AFC det.: AFC filter connecting pin Input impedance; 100 kΩ or more ■ Terminal Equivalent Circuits (continued) Pin 23 GND 15 kΩ 100 kΩ 10 kΩ Pin 23 GND 15 kΩ 100 kΩ 10 kΩ Pin 23 GND 15 kΩ 100 kΩ 10 kΩ Pin 44 VCC1 Pin 41 GND 10 kΩ 12 kΩ 200 Ω 60 Ω 60 Ω Pin 41 GND Pin 44 VCC1 1 kΩ 1 kΩ 2 kΩ 2 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform

43 H f O: 

adjusting resistor connection pin 44  VCC1:  Pulse system power supply 5.0 V

45 NAVI sync-in:

Synchronous signal input pin for the signal of car naviga- tion system Negative polarity input

46 HSS in: Input signal example:

Sync. signal input pin Video signal Separates a sync. signal from luminance signal (video sig- nal)

47 SCLK:

48 DAT:

■ Terminal Equivalent Circuits (continued) Pin 41 GND Pin 44 VCC1 2 kΩ 5 pF 10 kΩ10 kΩ Pin 23 GND 15 kΩ 100 kΩ 10 kΩ 0 V VDD Pin 44 VCC1 Pin 41 GND 50 kΩ850 Ω 85 Ω 21.7 kΩ 32.5 kΩ Pin 23 GND 15 kΩ 100 kΩ 10 kΩ Pin 44 VCC4 Pin 23 GND 15 kΩ 100 kΩ 10 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform

49 RST: 

Capacitor coupling pin for power-on reset 50 Com. DC: DC DC voltage output pin

51 DAC-out: DC

52 Y-in: Input signal example:

Luminance signal input pin Video signal Input luminance signal (video signal)

53 Trap-out: 

Trapping a chrominance sig- nal by connecting external inductor and capacitor. Not necessary in case that an in- put signal is a component. ■ Terminal Equivalent Circuits (continued) Pin 44 VCC1 Pin 37 VSS Pin 41 GND 5 kΩ 500 Ω 100 kΩ 50 kΩ Pin 41 GND Pin 44 VCC11.5 pF 36 kΩ 46 kΩ 40 kΩ Pin 41 GND Pin 44 VCC11.5 pF 36 kΩ 46 kΩ 40 kΩ Pin 58 VCC1 Pin 59 GND 2 kΩ 2 kΩ 50 Ω 50 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform

54 Trap-in: 

55 Y-det.:  Capacitor coupling pin for luminance signal clamping 56 ACC det.:  ACC capacitor connecting pin, adjusting the amplitude of a burst signal automati- cally

57 C-in: Input signal example:

Chrominance signal input pin Video signal Input chrominance signal (video signal) 58  VCC1:  Power supply 5.0 V typ. Chrominance and luminance signal processing system. 59  GND 3:  GND for chrominance and lum- inance signal processing system ■ Terminal Equivalent Circuits (continued) Pin 58 VCC1 Pin 59 GND 2 kΩ Pin 58 VCC1 Pin 59 GND 1 kΩ 1 kΩ 2 kΩ Pin 59 GND Pin 58 VCC1 1 kΩ 5 kΩ 1 kΩ 1 kΩ1 kΩ 2 kΩ 5 kΩ Pin 58 VCC1 Pin 59 GND 50 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform 60 Kill det.:  Killer capacitor coupling pin To prevent degradation of image in a small amplitude of a burst signal, this pin stops a chrominance signal and the mode changes to black and white mode. 61 APC det.:  APC capacitor coupling pin Matching the phase of a crys- tal oscillation to that of burst signal62 SCP out: NTSC 3.58 MHz Subcarrier pulse output pin PAL 4.43 MHz

63 VXO1: 

NTSC crystal oscillator con- necting pin Use the capacitor with tem- perature characteristics (N750) to connect to the crystal oscillator. ■ Terminal Equivalent Circuits (continued) Pin 58 VCC1 Pin 59 GND 1.5 kΩ 72 kΩ 90 kΩ Pin 58 VCC1 Pin 59 GND 2 kΩ 2 kΩ 1 kΩ 50 kΩ 100 kΩ 1 kΩ 1 kΩ 31 kΩ 41 kΩ 45 kΩ 5 kΩ 5 kΩ 50 kΩ Pin 58 VCC1 Pin 59 GND 10 kΩ 10 kΩ Pin 58 VCC1 Pin 59 GND 190 Ω 1 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform

64 VXO2: 

Use the capacitor with tem- perature characteristics (N750) to connect to the crystal oscillator. ■ Terminal Equivalent Circuits (continued) ■ Usage Notes

• The supply voltage applied to pin 6, pin 25, pin 29, pin 44, and pin 58 must be brought up at the same time.
• The crystal oscillator used must be evaluated thoroughly, because chrominance signal processing system characteris- tics change by the crystal oscillator type.
• The conversion of the analog RGB signals and the analog OSD signals with synchronous signals is not supported.
• Input the analog RGB signals and the analog OSD signals after filtering the pedestal parts of these signals.
• Evaluated thoroughly on the application of this device in PAL. ■ Technical Data 1. Serial interface description 1) I 2C bus control mode A serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of signal lines of data and shift clock. When a slave address after setting a start condition matches the address on the IC side, you can receive the data to be transmitted from then. Once the stop condition is set up, the next transmitting data will be ignored until the start condition is set up. There are two kinds of transfer mode: an auto-increment mode which does not transmit subaddress, and data upgrade mode which transmits subaddress + data by 2 bytes. The typical models of communication sequence are shown below: (1) Start condition When the S-data changes from high level to low level at SCLK = high level, a data receiving mode becomes available. (2) Slave address transfer The slave address of the AN2546FH-A is 88h. Pin 58 VCC1 Pin 59 GND 190 Ω 1 kΩ Subaddress transfer Acknowledge bit Pin 48 S-data Pin 47 SCLK 234 5678912 Start condition

■ Technical Data (continued) 1. Serial interface description (continued) 1) I 2C bus control mode (continued) (3) Subaddress transfer When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded as the data block. (5) Stop condition When S-data changes from low level to high level at SCLK = high level, data reception is halted. (6) Pulse timing Timing chart expanded diagram (4) Data transfer Data transferSlave address transfer Acknowledge bit D7 D6 D5 D4 D3 D2 D1 D0Pin 48 S-data Pin 47 SCLK 2345678989 12 Data transfer mode bit "1": Data update mode "0": Auto increment mode Acknowledge bit D7 D6 D5 D4 D3 D2 D1 D0Pin 48 S-data Pin 47 SCLK 2345678989 12 At auto increment mode: Data transfer At data update mode: Stop condition Pin 48 S-data Pin 47 SCLK tf tLOW tBUF tHDSTA tr tHIGH tSUDAT tSUSTO tHDDAT Parameter Symbol Min Typ Max Unit SCLK clock frequency t SCL 0  400 kHz Bus free-time for stop condition and start condition t BUF 1.3  µ s Hold time start condition t HDSTA 0.6  µ s SCLK clock low-state hold time t LOW 1.3  µ s SCLK clock high-state hold time t HIGH 0.6  µ s Data hold time t HDDAT 0  µ s Data setup time t SUDAT 100  ns S-data and SCLK signal rise time t r  300 ns S-data and SCLK signal fall time t f  300 ns Stop condition setup time t SUSTO 0.6  µ s

■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table ch. Sub- Initial value D7 D6 D5 D4 D3 D2 D1 D0 address (HEX) 1 01 80 Common amplitude 2 02 80 Luminance gain 3 03 80 Color gain 4 04 80 Hue 5 05 40 HGA Black limiter 6 06 80 Brightness 7 07 80 DBOSC Aperture 8 08 80 R-ch. sub-brightness 9 09 80 B-ch. sub-brightness 10 0A C0 DCLP White peak limiter 11 0B 80 Gamma 1 12 0C 80 Gamma 2 13 0D 80 Contrast 14 0E 80 R-ch. sub-contrast 15 0F 80 B-ch. sub-contrast 16 10 80 VCO free-run *1 17 11 03 DFVD DFSC DPALM DPALN DSECAM DVMODE DUV DCINT 18 12 00 MACRON PLL stop position adjustment Vertical position adjustment 19 13 80 HOSEI PWMT4 KOTEI Horizontal position adjustment 20 14 80 PWM frequency adjustment BLAK Burst cleaning pulse position adjustment 21 15 80 PWM duty 22 16 7F EXTTEST DHTS EXCHFI POLSW DMOSD DSC DCPS DQPAL 23 17 80 Common DC *2 24 18 80 DC output adjustment Note) *1: VCO free-run adjustment; ch.23 = 02h or more, EXTTEST = High *2: 00h, 01h are prohibition of use because of test mode.

■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (1) ch.5: Black limiter adjustment Sub- D7 D6 D5 D4 D3 D2 D1 D0 address DCLP 0A 0 NAVI sync. mode (Pin 45) 1 Video sync. mode (Pin 46) (4) ch.17: Mode setup 1 Sub- D7 D6 D5 D4 D3 D2 D1 D0 address

11 DFVD DFSC DPALM DPALN DSECAM DVMODE DUV DCINT

DFVD 0 VD cycle: 60 Hz

1 VD cycle: 50 Hz

DFSC 0 Subcarrier: 3.58 MHz 1 Subcarrier: 4.43 MHz DPALM High = PALM mode on DPALN High = PALN mode on DSECAM High = SECAM mode on DVMODE High = Burst swing off DUV 0 Chrominance input

1 Color difference signal input

1 Video signal input

• at NTSC selection DFVD/DFSC/DPALM/DPALN/DSECAM = Low DVMODE = High
• at PAL selection DFVD/DFSC = High DPALM/DPALN/DSECAM/DVMODE = Low
• at PALM selection DPALM/DFVD = High DPALN/DSECAM/DVMODE = Low
• at PALN selection DPALN = High DPALM/DSECAM/DVMODE/DFVD = Low (5) ch.18: PLL stop position and vertical sync. output position adjustment Sub- D7 D6 D5 D4 D3 D2 D1 D0 address MACRON PLL stop position adjustment Vertical position adjustment 12 0 AFC normal operation

1 Copy guard signal correspondence

(3) ch.10: White peak limiter adjustment Sub- D7 D6 D5 D4 D3 D2 D1 D0 address HGA 05 0 Output gain down mode

1 Gain mode

(2) ch.7: Aperture adjustment Sub- D7 D6 D5 D4 D3 D2 D1 D0 address DCLP 07 0 VD free-run: NTSC = 265H, PAL = 315H

1 VD free-run : NTSC = 263H, PAL = 313H

■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (5) ch.18: PLL stop position and vertical sync. position adjustment (continued) <Vertical synchronous output timing adjustment range> Pin 35 input Composite sync. signal odd number field Pin 31 output odd number field FIXHD = "0" Pin 31 output odd number field FIXHD = "1" 2H to 9H (D0 to D2) Composite sync. signal even number field Pin 31 output EXCHF = "1" FIXHD = "0" Pin 31 output EXCHF = "1" FIXHD = "1" Pin 31 output EXCHF = "0" FIXHD = "0" Pin31 output EXCHF = "0" FIXHD = "1" The above timing chart indicates (D2,D1,D0) = "101". For (D2,D1,D0) = "000", the pin 32 output width is 9H. The pin 31 timing is synchronous with the pin 35 input timing. The above timing chart is just for reference 1.5H to 8.5H (D0 to D2) 2.5H to 9.5H (D0 to D2) Pin 35 input Composite sync. signal odd number field Odd number field EXCHF = "1" EXCHF = "0" Composite sync. signal even number field 6H to 9H (D3 to D4) Horizontal PLL onHorizontal PLL off 0-line 1 2 3 5.5H to 8.5H (D3 to D4) Horizontal PLL onHorizontal PLL off 6.5H to 9.5H (D3 to D4) Horizontal PLL onHorizontal PLL off The above timing chart indicates (D4,D3) = "01". PLL stop line number: 254-line (NTSC) 302-line (PAL) <Horizontal PLL start position adjustment range>

■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (6) ch.19: Horizontal sync. output position adjustment Sub- D7 D6 D5 D4 D3 D2 D1 D0 address HOSEI PWMT4 KOTEI 13 0 Sync. output variable mode 1 Sync. output fixation mode  PWM frequency adjustment

0 VCO automatic adjustment off

1 VCO automatic adjustment on

The delay time of pin 34 output to video signal is likely to vary according to an external constant connected to pin 46. For an external constant, the characteristics in weak electric field must be evaluated adequately. Though the horizontal sync. signal output adjustment range is designed by referring to the center of pin 34 output pulse, there would be some error according to VCO free-run frequency. (7) ch.20: PWM frequency and burst cleaning pulse width adjustment Pin 34 Composite sync. signal output Pin 32 Horizontal sync. signal output Composite sync. signal input (video signal) Sync. signal separation delay time (Approximately 1 µs) 27fy Pin 32 Horizontal sync. signal output Pin 32 Horizontal sync. signal output (D5) = "1" 27fy31fy 18fy Delay time (Approximately 400 ns) fh: Horizontal sync. frequency 1fy = (NTSC/PAL)347fh Sub- D7 D6 D5 D4 D3 D2 D1 D0 address PWM frequency adjustment BLAK Burst cleaning pulse adjustment 14 0 Black level variable mode

1 Black level fixation mode

■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (8) ch.22: Mode setup 2 2. Recommended Operating Conditions Sub- D7 D6 D5 D4 D3 D2 D1 D0 address

16 EXTTEST DHTS EXCHFI POLSW DMOSD DSC DCPS D QPAL

1 Test mode

EXCHFI 0 Odd number field: Advance phase

1 Even number field: Advance phase

POLSW 0 Internal POL 1H reverse mode

1 External POL 1H reverse mode

DMOSD 0 Analog OSD signal input

1 Digital OSD signal input

DSC 0 Subcarrier output stop

1 Subcarrier output

DCPS 0 Component input mode

1 Composite input mode

1 Quasi PAL mode

Parameter Symbol Condition Min Typ Max Unit Composite video input signal Y IN Sync. chip - White 0.9 1.0 1.1 V[p-p] Y-input signal voltage Y IN Pedestal - White 0.6 0.7 0.8 V[p-p] C-input signal voltage C IN Burst signal amplitude 200 300 400 mV[p-p] MOS input signal low-level voltage V MOSL 0  0.9 V MOS input signal high-level voltage V MOSH 2.1  *1V Analog RGB signal input RGB IN Pedestal - White 0.6 0.7 0.8 V[p-p] Note) *1: Set it lower than V CC1 (Pin 6 voltage).

■ New Package Dimensions (Unit: mm)

• QFP064-P-1010A (Lead-free package) 12.00±0.20 (1.00) 0.18±0.05 0.50±0.20 0° to 10° (1.25) 12.00±0.20 10.00±0.20 (1.25) 10.00±0.20 48 33 11 6 1764 1.95±0.200.10±0.10 0 15 ±0.05 Seating plane M0.10 0.50 0.10 1.600 1.576 1.400 1.200 1.000 0.800 0.814 0.600 0.400 0.200 0 25 150 Ambient temperature Ta (°C) Power dissipation PD (W) 50 75 100 125 0.000 Mounted on standard board (glass epoxy: 75 × 75 × t0.8 mm3) Rth(j a) = 79.3°C/W Independent IC without a heat sink R th(j a) = 153.5°C/W ■ Technical Data (continued) 3. Power dissipation of package QFP064-P-1010 PD  Ta

Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteris- tics and applied circuits examples of the products. It neither warrants non-infringement of intellec- tual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instru- ments and household appliances). Consult our sales staff in advance for information on the following applications:

• Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body.
• Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maxi- mum rating, the range of operating power supply voltage, and heat radiation characteristics. Other- wise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.

2002 JUL