AN2526NFH

AN2526NFH PANASONIC

Document overview

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Technical content

Publication date: November 2001 SDB00080AEB AN2526NFH Automotive LCD TV signal processor IC I Overview The AN2526NFH is a video signal processing IC with an LCD's 5 V-source driving power supply for TFT color LCD (normally white type), and it supports NTSC and PAL systems. The main circuitry of this IC includes video- signal processing circuit, color signal processing circuit, interface circuit, synchronizing circuit and many color quality adjusting circuits. This IC converts the composite video signal or separated Y/C signal or RGB signals into RGB signals available for TFT color LCD. I Features

• Supply voltage: 5 V/7.5 V
• Built-in LCD's 5 V-source driving power supply
• Low consumption power (typ. 260 mW)
• Supporting NTSC and PAL
• Supporting composite, component and color differen- tial signal input
• Video signalɼanalog RGB (2 systems) One is for OSD (analog/digital).
• Each mode setting is possible with 3-wire or I 2C Bus control.
• Electronic volume (D/A converter) built in
• Contrast/Brightness/γ correction circuit built in
• Horizontal and vertical display position adjustment are possible by serial control.
• Package: QFP-64HP10L (10 × 10 × 1.95 mm)
• Difference from the AN2526FH Compared to the AN2526FH, the sync. system gain is increased in no signal input. This may cause the picture on the screen to be swaying horizontally. So we cannot recommend this IC to be used in the set with no-signal input mode. I Applications
• 4 inches to 7 inches middle size TFT LCD equipment of normally white, of such as in-car TV, an LCD monitor for car navigation system. QFP064-P-1010 Unit: mm 10.00±0.20 48 33 161 12.00±0.20 10.00±0.20 0.10±0.10 (1.25) (1.25) 0.50 0.18 +0.10 −0.05 0.15 +0.10 −0.05 Seating plane (1.00) 0.50±0.20 0° to 10° Note) The package of this product will be changed to lead-free type (QFP064-P-1010A). See the new package dimensions section later of this datasheet.

I Application Circuit Examples 1. Composite signal input LD GND 3 R−Y out B−Y out R−Y in B−Y in B-out R-out G-out VCC2 VCC1 VCOM GND1 TMODE Test CLK Field C-sync. VD HD PWM PONR POL VSS Clamp DAC mon. GND2 NRGB S-data SCLCK BUSCH 1.0 µF 0.1 µF 0.1 µF 1 µF 0.02 µF 0.02 µF 0.1 µF 0.1 µF 47 µH 4.7 µF 1 000 pF 470 Ω 180 kΩ 1 MΩ 5.1 kΩ NTSC

3.58 MHz

4.43 MHz

2.2 µF 2.2 µF 2.2 µF 15 µF 47 µH 0.01 µF 50 kB (7.5 V) 82 kΩ 82 kΩ 100 kΩ 3.3 kΩ 10 kΩ 100 kΩ 200 kΩ 330 pF 330 pF 000 pF VCC1 2.2 µF15 µF 0.022 µF 0.47 µF VCC1 (5.0 V) Dec. R-out Dec. G-out Dec. B-out R-in 1 G-in 1 B-in 1 R-in 2 G-in 2 B-in 2 BLAK YS 47 µH 15 µF 15 µF1 µF1 µF1 µF 1633 BUSCH HPF Logic ACC amp. ACC det. LATCH DAC Shift res. DEC Sync. sepa. HH-KIL V-C/D Logic Logic Logic VCO DAC PWM f-det. 1/n Kill det. APC det. VXO CLMP Delay Trap Tint Tint-ctl. Y AP ctl. Color-ctl. GCA ctl. Line I-det. Int./Ext. SW Int./Ext. SW Contrast Bright Gamma Amp. A VE det. COMON voltage VCOM adj. POL Bright-ctl. Contrast ctl. White peak ctl. Gamma ctl. WB-ctl. CW/SW PAL 1/2 Demod. LPF GCA VREF GCA GCA Matrix CLMP Delay Det. Logic Logic Logic CLP BGP Sync.DRP PH-CMP Reg. φ1 to φ4 Gene. (BGP) Composite signal

• C coupling input in an analog OSD mode.
• Connect to GND in case of no use in a digital OSD mode.

I Application Circuit Examples (continued) 2. Component signal input LD GND 3 R−Y out B−Y out R−Y in B−Y in B-out R-out G-out VCC2 VCC1 VCOM GND1 TMODE Test CLK Field C-sync. VD HD PWM PONR POL VSS Clamp DAC mon. GND2 NRGB S-data SCLCK BUSCH 1.0 µF 0.1 µF 0.1 µF 1 µF 0.02 µF 0.02 µF 0.1 µF 0.1 µF 4.7 µF 1 000 pF 470 Ω 180 kΩ 1 MΩ 5.1 kΩ NTSC 2.2 µF 2.2 µF 2.2 µF 15 µF 47 µH 0.01 µF 50 kB (7.5 V) 82 kΩ 82 kΩ 100 kΩ 3.3 kΩ 10 kΩ 100 kΩ 200 kΩ 330 pF 330 pF 000 pF VCC1 2.2 µF15 µF 0.022 µF 0.47 µF VCC1 (5.0 V) Dec. R-out Dec. G-out Dec. B-out R-in 1 G-in 1 B-in 1 R-in 2 G-in 2 B-in 2 BLAK YS 47 µH 15 µF 15 µF1 µF1 µF1 µF 1633 BUSCH HPF Logic ACC amp. ACC det. LATCH DAC Shift res. DEC Sync. sepa. HH-KIL V-C/D Logic Logic Logic VCO DAC PWM f-det. 1/n Kill det. APC det. VXO CLMP Delay Trap Tint Tint-ctl. Color-ctl. GCA ctl. Line I-det. Int./Ext. SW Int./Ext. SW Contrast Bright Gamma Amp. A VE det. COMON voltage VCOM adj. POL Bright-ctl. Contrast ctl. White peak ctl. Gamma ctl. WB-ctl. CW/SW PAL 1/2 Demod. LPF GCA VREF GCA GCA Matrix CLMP Delay Det. Logic Logic Logic CLP BGP Sync.DRP PH-CMP Reg. φ1 to φ4 Gene. (BGP) Y AP ctl. Lumi. + Sync. signal Chroma signal

• C coupling input in an analog OSD mode.
• Connect to GND in case of no use in a digital OSD mode.

I Application Circuit Examples (continued) 3. Analog RGB signal input LD GND 3 B-out R-out G-out VCC2 VCC1 VCOM GND1 TMODE Test CLK Field C-sync. VD HD PWM PONR POL VSS Clamp DAC mon. GND2 NRGB S-data SCLCK BUSCH 1.0 µF 1 000 pF 470 Ω 180 kΩ 2.2 µF 2.2 µF 2.2 µF 15 µF 47 µH 0.01 µF 50 kB (7.5 V) 82 kΩ 82 kΩ 100 kΩ 3.3 kΩ 10 kΩ 100 kΩ 200 kΩ 330 pF 330 pF 1 000 pF VCC1 2.2 µF15 µF 0.022 µF 0.47 µF VCC1 (5.0 V) R-in 1 G-in 1 B-in 1 R-in 2 G-in 2 B-in 2 BLAK YS 47 µH 15 µF 2.2 MΩ 2.2 MΩ 2.2 MΩ 15 µF 4.7 µF 4.7 µF 4.7 µF 1633 BUSCH HPF Logic ACC amp. ACC det. LATCH DAC Shift res. DEC Sync. sepa. HH-KIL V-C/D Logic Logic Logic VCO DAC PWM f-det. 1/n Kill det. APC det. VXO CLMP Delay Trap Tint Tint-ctl. Color-ctl. GCA ctl. Line I-det. Int./Ext. SW Int./Ext. SW Contrast Bright Gamma Amp. A VE det. COMON voltage VCOM adj. POL Bright-ctl. Contrast ctl. White peak ctl. Gamma ctl. WB-ctl. CW/SW PAL 1/2 Demod. LPF GCA VREF GCA GCA Matrix CLMP Delay Det. Logic Logic Logic CLP BGP Sync.DRP PH-CMP Reg. φ1 to φ4 Gene. (BGP) Y AP ctl. Composite signal

• C coupling input in an analog OSD mode.
• Connect to GND in case of no use in a digital OSD mode.

Pin No. Description 1V CC1 (5.0 V)

2 Reference voltage pin

3 R-ch. clamp detection pin 4 G-ch. clamp detection pin 5 B-ch. clamp detection pin 6 R-ch. decoder output pin 7 G-ch. decoder output pin 8 B-ch. decoder output pin 9 R-ch. analog signal input pin 10 G-ch. analog signal input pin 11 B-ch. analog signal input pin 12 R-ch. analog/character signal input pin 13 G-ch. analog/character signal input pin 14 B-ch. analog/character signal input pin

15 Black level indication control signal input pin

16 Character picking up pulse input pin

17 B-ch. output pin 18 B-ch. output DC feedback detection pin 19 G-ch. output pin 20 V CC2 (7.5 V)

21 Drive output reference potential input pin

22 GND 1

23 G-ch. output DC feedback detection pin 24 R-ch. output pin 25 R-ch. output DC feedback detection pin

26 Common reverse signal output pin

27 Testing pulse input pin

28 Testing clock input pin

29 Field identification signal output pin

30 Composite synchronous signal output pin

31 Vertical synchronous signal output pin

32 Horizontal synchronous signal output pin

Pin No. Description

33 PWM output pin

34 Power-on reset detection pin

35 Vertical synchronous signal input pin

36 1H reverse signal input pin

37 Clock-system GND (V SS)

38 Clamp pulse input pin

39 DAC monitor pin

40 Clock-system power supply (3.0 V)

41 GND 2

42 Analog imposing control signal input pin

43 AFC loop filter connecting pin

44 VCO frequency adjustment pin

45 Synchronous signal input pin

46 Serial/I 2C Bus switching pin

47 Serial data shift clock input pin

48 Serial data input pin

49 Serial data write pulse input pin

50 ACC detection pin

51 ACC input pin

52 Horizontal clock detection pin

53 Chroma killer detection pin

54 APC detection pin

55 VXO input pin

56 VXO output pin

57 Y-system clamp detection pin

58 Chroma trap filter connection pin

59 GND 3

60 Luminance signal input pin

61 R-Y output pin

62 B-Y output pin

63 R-Y input pin

64 B-Y input pin

I Recommended Operating Range I Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage V CC1 5.5 V VCC2 8.5 Supply current I CC  mA Power dissipation *2 PD 423 mW Operating ambient temperature *1 Topr −30 to +85 °C Storage temperature *1 Tstg −55 to +150 °C Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for T a = 25°C. *2: The power dissipation shown is the value in free air for T opr = 85°C. Parameter Symbol Range Unit Supply voltage V CC1 4.7 to 5.3 V VCC2 7.0 to 8.0 Parameter Symbol Conditions Min Typ Max Unit DC VCC1-system current consumption I TOTAL1  29  43 mA VCC2-system current consumption I TOTAL2  6.0  14.0 mA Pin 2 voltage V 2  1.8  2.2 V Pin 40 voltage V 40  2.7  3.3 V Chroma system R-Y standard gain G RY SG3 (Yy = −17 dB, Ys = 0 V[p-p], 9.5  14.5 dB NTSC), ch.1 = "C0" R-Y/G-Y relative gain G RYGY SG3 (Yy = −17 dB, Ys = 0 V[p-p], −8.0 − 4.0 dB NTSC), ch.1 = "C0" B-Y standard gain G BY SG3 (Yy = −17 dB, Ys = 0 V[p-p], 9.5  14.5 dB NTSC), ch.1 = "C0" B-Y/G-Y relative gain G BYGY SG3 (Yy = −17 dB, Ys = 0 V[p-p], −20.5 − 12.5 dB NTSC), ch.1 = "C0" High-level APC pull-in AP H SG5 (4.43 MHz + 520 Hz, PAL) 500  540 Hz Low-level APC pull-in AP L SG5 (4.43 MHz − 520 Hz, PAL) −540 − 500 Hz ACC output characteristic 1 G ACC1 SG5 (0 dB, 6 dB, NTSC), ch.1 = "80" −1.0  1.0 dB ACC output characteristic 2 G ACC2 SG5 (0 dB, 6 dB, NTSC), ch.1 = "80" −1.0  1.0 dB Chroma killer characteristic 1 V KILL1 SG5 (−30 dB, NTSC) 400  mV[p-p] Chroma killer characteristic 2 V KILL2 SG5 (−50 dB, NTSC)  600 mV[p-p] I Electrical Characteristics at Ta = 25°C

I Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system Sharpness control characteristic G SH SG1 (2 MHz, NTSC) 1.0  dB Sharpness frequency characteristic 1 fSH1 SG1 (100 kHz/2 MHz, NTSC) 3.5  dB ch.1 = "80" R-ch. contrast adjustment range 1 CTR R1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 1.5  dB ch.8/10/11 adjustment ch.15 = "C0"/"FF" G-ch. contrast adjustment range 1 CTR G1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 1.5  dB ch.8/10/11 adjustment ch.15 = "C0"/"FF" B-ch. contrast adjustment range 1 CTR B1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 1.5  dB ch.8/10/11 adjustment ch.15 = "C0"/"FF" R-ch. contrast adjustment range 2 CTR R2 SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  − 5.2 dB ch.8/10/11 adjustment ch.15 = "C0"/"80" G-ch. contrast adjustment range 2 CTR G2 SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  − 5.2 dB ch.8/10/11 adjustment ch.15 = "C0"/"80" B-ch. contrast adjustment range 2 CTR B2 SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  − 5.2 dB ch.8/10/11 adjustment ch.15 = "C0"/"80" R-ch. pedestal amplitude minimum V PEDRmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  2.0 V[p-p] ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" G-ch. pedestal amplitude minimum V PEDGmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  2.0 V[p-p] ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" B-ch. pedestal amplitude minimum V PEDBmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  2.0 V[p-p] ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0"

I Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) R-ch. pedestal amplitude maximum VPEDRmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0   V[p-p] ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" G-ch. pedestal amplitude maximum VPEDGmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0   V[p-p] ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" B-ch. pedestal amplitude maximum VPEDBmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0   V[p-p] ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" ch.8/10/11 adjustment, ch.15 = "C0" ch.8/10/11/15 adjustment ch.8/10/11/15 adjustment ch.8/10/11/15 adjustment R-ch. gamma characteristic 2 G GAMR2 SG3 (NTSC), ch.1 = "E0", ch.4 = "40" −8.2   dB ch.8/10/11/15 adjustment ch.13 = "80"/"FF" G-ch. gamma characteristic 2 G GAMG2 SG3 (NTSC), ch.1 = "E0", ch.4 = "40" −8.2   dB ch.8/10/11/15 adjustment ch.13 = "80"/"FF" B-ch. gamma characteristic 2 G GAMB2 SG3 (NTSC), ch.1 = "E0", ch.4 = "40" −8.2   dB ch.8/10/11/15 adjustment ch.13 = "80"/"FF" ch.8/10/11/15 adjustment ch.13 = "80"/"60"

I Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) ch.8/10/11/15 adjustment ch.13 = "80"/"60" ch.8/10/11/15 adjustment ch.13 = "80"/"60" R-ch. white limiter low-level V WRRL SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  3 . 0 V[p-p] ch.8/10/11/15 adjustment ch.15 = "FF" G-ch. white limiter low-level V WRGL SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  3 . 0 V[p-p] ch.8/10/11/15 adjustment ch.15 = "FF" B-ch. white limiter low-level V WRBL SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  3 . 0 V[p-p] ch.8/10/11/15 adjustment ch.15 = "FF" R-ch. white limiter high-level V WRRH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.2  V[p-p] ch.8/10/11/15 adjustment ch.15 = "FF" G-ch. white limiter high-level V WRGH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.2  V[p-p] ch.8/10/11/15 adjustment ch.15 = "FF" B-ch. white limiter high-level V WRBH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.2  V[p-p] ch.8/10/11/15 adjustment ch.15 = "FF" R-ch. black limiter low-level V BRRL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0  V ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" G-ch. black limiter low-level V BRGL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0  V ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00"

I Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) B-ch. black limiter low-level V BRBL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0  V ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" R-ch. black limiter high-level V BRRH SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  1.2 V ch.8/10/11/15 adjustment, ch.7 = "FF" G-ch. black limiter high-level V BRGH SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  1.2 V ch.8/10/11/15 adjustment, ch.7 = "FF" B-ch. black limiter high-level V BRBH SG3 (NTSC), ch.1 = "E0", ch.2 = "40"  1.2 V ch.8/10/11/15 adjustment, ch.7 = "FF" R-ch. YS threshold 1 V tYSR1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 0.8  V[p-p] ch.8/10/11/15 adjustment, Pin 16 = 1 V G-ch. YS threshold 1 V tYSG1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 0.8  V[p-p] ch.8/10/11/15 adjustment, Pin 16 = 1 V B-ch. YS threshold 1 V tYSB1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 0.8  V[p-p] ch.8/10/11/15 adjustment, Pin 16 = 1 V R-ch. YS threshold 2 V tYSR2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40"  0.5 V[p-p] ch.8/10/11/15 adjustment, Pin 16 = 2.2 V G-ch. YS threshold 2 V tYSG2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40"  0.5 V[p-p] ch.8/10/11/15 adjustment, Pin 16 = 2.2 V B-ch. YS threshold 2 V tYSB2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40"  0.5 V[p-p] ch.8/10/11/15 adjustment, Pin 16 = 2.2 V ch.8/10/11/15 adjustment, Pin 16 = SG7 ch.8/10/11/15 adjustment, Pin 16 = SG7 ch.8/10/11/15 adjustment, Pin 16 = SG7

I Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) ch.8/10/11/15 adjustment, Pin 16 = SG7 ch.8/10/11/15 adjustment, Pin 16 = SG7 ch.8/10/11/15 adjustment, Pin 16 = SG7 R-ch. CHR threshold 1 V tCHR1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 1.5  V[p-p] ch.8/10/11/15 adjustment, Pin 12 = 1 V G-ch. CHR threshold 1 V tCHG1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 1.5  V[p-p] ch.8/10/11/15 adjustment, Pin 13 = 1 V B-ch. CHR threshold 1 V tCHB1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 1.5  V[p-p] ch.8/10/11/15 adjustment, Pin 14 = 1 V R-ch. CHR threshold 2 V tCHR2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0  V[p-p] ch.8/10/11/15 adjustment, Pin 12 = 2.2 V G-ch. CHR threshold 2 V tCHG2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0  V[p-p] ch.8/10/11/15 adjustment, Pin 13 = 2.2 V B-ch. CHR threshold 2 V tCHB2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 3.0  V[p-p] ch.8/10/11/15 adjustment, Pin 14 = 2.2 V R-ch. white level CHR RW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.0  V[p-p] ch.8/10/11/15 adjustment, Pin 12 = SG7 G-ch. white level CHR GW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.0  V[p-p] ch.8/10/11/15 adjustment, Pin 13 = SG7 B-ch. white level CHR BW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.0  V[p-p] ch.8/10/11/15 adjustment, Pin 14 = SG7 ch.8/10/11/15 adjustment, Pin 12 = SG7 ch.8/10/11/15 adjustment, Pin 13 = SG7

I Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) ch.8/10/11/15 adjustment, Pin 14 = SG7 R-ch. RGB2 relative amplitude V RGB2R SG2 (NTSC), ch.1 = "A0" − 0.45  0.45 V[p-p] ch.8/10/11/15 adjustment, ch.3 = "40" B-ch. RGB2 relative amplitude V RGB2B SG2 (NTSC), ch.1 = "A0" − 0.45  0.45 V[p-p] ch.8/10/11/15 adjustment, ch.3 = "40" Synchronous system Horizontal sync. pulse low-level V HDL   0.4 V Horizontal sync. pulse amplitude V HD  4.0  V[p-p] Horizontal sync. pulse width t HD  4.86  6.86 µs Vertical sync. pulse low-level V VDL   0.4 V Vertical sync. pulse amplitude V VD  4.0  V[p-p] Horizontal sync. separation pulse V HSSH SG2 (NTSC) 4.0  V high-level Horizontal sync. separation pulse V HSS SG2 (NTSC) 4.0  V[p-p] amplitude Horizontal sync. separation pulse t HSS SG2 (NTSC) 3.8  5.8 µs width Horizontal sync. pulse free-run f HD 15.434  16.034 kHz frequency I Terminal Equivalent Circuits Pin No. Equivalent circuit Description Voltage · Waveform 1  VCC1: 

5.0 V-system power supply pin

Supply current 40 mA typ. 2V REF:  Reference voltage output pin 2.0 V typ. 1 kΩ 60 Ω Pin 1 VCC1 Pin 59 GND200 Ω 30 kΩ 26 kΩ

I Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage · Waveform 3 R-ch. det.:  R-ch. clamping capacitor coupling pin 4 G-ch. det.:  G-ch. clamping capacitor coupling pin 5 B-ch. det.:  B-ch. clamping capacitor coupling pin 6 Dec.R-out: Output pin of R signal de- modulated from video signal 1 kΩ 1 kΩ Pin 1 VCC1 Pin 22 GND 500 Ω HSS 1 kΩ 1 kΩ Pin 1 VCC1 Pin 22 GND 500 Ω HSS 1 kΩ 1 kΩ Pin 1 VCC1 Pin 22 GND 500 Ω HSS Pin 1 VCC1 Pin 22 GND 150 Ω 150 Ω

Pin No. Equivalent circuit Description Voltage · Waveform 7 Dec.G-out: Output pin of G signal de- modulated from video signal 8 Dec.B-out: Output pin of B signal de- modulated from video signal

9 R-in 1: Analog R signal

10 G-in 1: Analog G signal

I Terminal Equivalent Circuits (continued) Pin 1 VCC1 Pin 22 GND 150 Ω 150 Ω Pin 1 VCC1 Pin 22 GND 150 Ω 150 Ω 5 kΩ BGP Pin 1 VCC1 Pin 2 VREF Pin 22 GND

0.7 V[p-p]

typ. 5 kΩ BGP Pin 1 VCC1 Pin 2 VREF Pin 22 GND typ.

Pin No. Equivalent circuit Description Voltage · Waveform

11 B-in 1: Analog B signal

12 R-in 2: Analog OSD

Character insertion signal in- put for R-ch., supporting ana- log and digital OSD. Digital OSD

13 G-in 2: Analog OSD

Character insertion signal in- put for G-ch., supporting ana- log and digital OSD. Digital OSD

14 B-in 2: Analog OSD

Character insertion signal in- put for B-ch., supporting ana- log and digital OSD. Digital OSD I Terminal Equivalent Circuits (continued) 5 kΩ BGP Pin 1 VCC1 Pin 2 VREF Pin 22 GND typ. 5 kΩ BGP Pin 1 VCC1 Pin 2 VREF Pin 22 GND typ. VCC1 GND typ. VCC1 GND 5 kΩ BGP Pin 1 VCC1 Pin 2 VREF Pin 22 GND 5 kΩ BGP Pin 1 VCC1 Pin 2 VREF Pin 22 GND typ. VCC1 GND

Pin No. Equivalent circuit Description Voltage · Waveform

15 BLAK:

Black level indication con- trol signal input pin

16 Y S:

Character picking up signal input

17 B-out:

18 B-ch.AVE det.:  B-ch. output DC feedback detection pin

19 G-out:

20  VCC2: 

7.5 V system power supply

Supply current 12 mA typ. I Terminal Equivalent Circuits (continued) 5 kΩ 49.3 kΩ VSS 5 kΩ 49.3 kΩ VSS VCC1 GND VCC1 GND 100 kΩ 200 Ω 26 kΩ Pin 20 VCC2 Pin 18 Pin 22 GND 2 kΩ 2 kΩ 100 kΩ Pin 17 8 kΩ Pin 20 VCC2 Pin 22 GND 100 kΩ 200 Ω 26 kΩ Pin 20 VCC2 Pin 18 Pin 22 GND 2 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform

21 AVE : 

R,G,B output DC reference voltage pin 22  GND 2:  Drive circuit system GND 23 G-ch.AVE det.:  G-ch. output DC feedback detection pin

24 R-out:

25 R-ch.AVE det.:  R-ch. output DC feedback detection pin I Terminal Equivalent Circuits (continued) 200 kΩ Pin 20 VCC2 Pin 22 GND 8 kΩ 2 kΩ 200 kΩ 2 kΩ 100 kΩ Pin 17 8 kΩ Pin 20 VCC2 Pin 22 GND 100 kΩ 200 Ω 26 kΩ Pin 20 VCC2 Pin 18 Pin 22 GND 2 kΩ 2 kΩ 100 kΩ Pin 17 8 kΩ Pin 20 VCC2 Pin 22 GND

Pin No. Equivalent circuit Description Voltage · Waveform

26 Common out:

Voltage output pin for common. Output impedance; Approx. 150 Ω

27 Test mode: High or Low

Logic test mode start signal input pin; "Open" or "GND" normally

28 Test CLK: High or Low

Logic test pulse input pin; "Open" or "GND" normally

29 Field: Output waveform

Field identifying signal out- put pin

30 HSS: Output waveform

Composite synchronous sig- nal output pin I Terminal Equivalent Circuits (continued) Pin 19 VCC2 Pin 22 GND 100 kΩ 15 kΩ 200 Ω Pin 40 VDD Pin 37 VSS 10 kΩ 39.8 kΩ ch.3 ch.3 Pin 40 VDD Pin 37 VSS 5 kΩ 44.8 kΩ Pin 1 VCC1 Pin 40 VDD Pin 37 VSS Field 0 V VCC1 Pin 1 VCC1 Pin 40 VDD Pin 37 VSS HSS 0 V VCC1

Pin No. Equivalent circuit Description Voltage · Waveform

31 VD: Output waveform

Vertical synchronous signal output pin

32 HD : Output waveform

Horizontal synchronous sig- nal output pin

33 PWM: Output waveform

34 RST: 

Capacitor coupling pin for power-on reset

35 VDB in: High or Low

Vertical synchronous pulse input pin I Terminal Equivalent Circuits (continued) Pin 1 VCC1 Pin 40 VDD Pin 37 VSS VD 0 V VCC1 Pin 1 VCC1 Pin 40 VDD Pin 37 VSS HD 0 V VCC1 Pin 1 VCC1 Pin 40 VDD Pin 37 VSS PWM 0 V VCC1 Pin 1 VCC1 Pin 37 VSS 5 kΩ 500 Ω 100 kΩ 50 kΩ Pin 40 VDD Pin 37 VSS 10 kΩ 45.2 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform 36 Ext. pol.: High or Low 1H reverse signal input pin 37  VSS : MOS system GND 

38 Clamp in: High or Low

Valid only in the external clamp mode. Positive polarity input. 39 DAC mon.: DC DAC DC voltage output pin 40  VDD:  Capacitor connection pin for MOS part power supply. 3.0 V typ. 41  GND 3: Pulse system GND 

42 PRGB: High or Low

Mode start-up signal input pin Valid only in the analog OSD mode High = Analog OSD start up I Terminal Equivalent Circuits (continued) Pin 40 VDD Pin 37 VSS 5 kΩ 50.2 kΩ Pin 40 VDD Pin 37 VSS 5 kΩ 50.2 kΩ Pin 1 VCC1 1.5 pF Pin 59 GND 2 kΩ 200 Ω 25 kΩ 20 kΩ Pin 40 VDD Pin 37 VSS 5 kΩ 53.8 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform 43 AFC det.: AFC filter connection pin Input impedance; 100 kΩ or more

44 H f O: 

adjusting resistor connection pin

45 HSS in: Input signal example:

H-sync. input pin Video signal Separates a sync signal from luminance signal (video sig- nal)

46 Bus-ch: High or Low

Switching pin for serial three- wire control/I2C Bus control High = I2C Bus Open or Low = Serial three- wire control

47 DAC:

I Terminal Equivalent Circuits (continued) Pin 59 GND Pin 1 VCC1 1 kΩ 1 kΩ 2 kΩ 2 kΩ Pin 59 GND Pin 1 VCC1 2 kΩ 5 pF 10 kΩ10 kΩ Pin 59 GND Pin 2 VREF Pin 1 VCC18.4 kΩ 20 kΩ 20 kΩ Pin 40 VDD Pin 37 VSS 4 kΩ 50 kΩ Pin 40 VDD Pin 37 VSS 4 kΩ 50 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform

48 DAT:

49 LEN: High or Low

Load pulse input pin, also works as the slave address conversion pin in the I mode. High = "88" Low = "8A" 50 ACC det.:  ACC capacitor connecting pin, adjusting the amplitude of a burst signal automati- cally51 C in: Input signal example: Chroma signal input pin Video signal Input chroma signal (video signal) 52 L.det.:  Capacitor coupling pin for the horizontal unlock detect- ing circuit I Terminal Equivalent Circuits (continued) Pin 40 VDD Pin 37 VSS Pin 59 GND 4 kΩ 50 Ω 500 Ω ACK Pin 48 VDD Pin 41 VSS 4 kΩ 50 kΩ Pin 1 VCC1 Pin 59 GND 1 kΩ 1 kΩ 1 kΩ 2 kΩ 5 kΩ 5 kΩ 1 kΩ Pin 1 VCC1 Pin 59 GND 50 kΩ Pin 1 VCC1 Pin 59 GND 10 kΩ 12 kΩ 200 Ω 60 Ω 60 Ω

Pin No. Equivalent circuit Description Voltage · Waveform 53 Kill det.:  Killer capacitor coupling pin. To prevent degradation of image in a small amplitude of a burst signal, this pin stops a chroma signal and the mode changes to black and white mode. 54 APC det.:  APC capacitor coupling pin. Matching the phase of a crys- tal oscillation to that of burst signal. 55 VXOI : NTSC 3.58 MHz Xtal connecting pin PAL 4.43 MHz The pair with pin 56 56 VXOO : NTSC 3.58 MHz Xtal connecting pin PAL 4.43 MHz The pair with pin 55 Output impedance; Approximately 100 Ω I Terminal Equivalent Circuits (continued) Pin 1 VCC1 Pin 59 GND 1.5 kΩ 72 kΩ 90 kΩ Pin 1 VCC1 Pin 59 GND 2 kΩ 2 kΩ 1 kΩ 50 kΩ 100 kΩ 1 kΩ 1 kΩ 31 kΩ 41 kΩ 45 kΩ 5 kΩ 5 kΩ 50 kΩ Pin 1 VCC1 Pin 59 GND 15 pF 400 Ω 6 kΩ 26 kΩ 5 kΩ 26 kΩ Pin 1 VCC1 Pin 59 GND 500 Ω 500 Ω

Pin No. Equivalent circuit Description Voltage · Waveform 57 Y-det.:  Capacitor coupling pin for luminance signal clamping

58 Trap: 

Trapping a chroma signal by connecting external inductor and capacitor. Not necessary in case that an input signal is a component. 59  GND 3:  GND for chroma and lumin- ance signal process blocks

60 Y-in: Input signal example:

Luminance signal input pin Video signal Input luminance signal (video signal)

61 R-Y out: R-Y signal

R-Y signal output pin, demo- dulated from a video signal I Terminal Equivalent Circuits (continued) Pin 1 VCC1 Pin 59 GND 1 kΩ 1 kΩ 2 kΩ Pin 59 GND Pin 1 VCC1 2 kΩ 50 Ω 1 kΩ 2 kΩ 2 kΩ Pin 1 VCC1 Pin 59 GND 2 kΩ 2 kΩ 50 Ω 20 kΩ 1 kΩ 2 kΩ Pin 1 VCC1 Pin 59 GND 1 kΩ 1 kΩ

Pin No. Equivalent circuit Description Voltage · Waveform

62 B-Y out : B-Y signal

B-Y signal output pin, de- modulated from a video sig- nal

63 R-Y in: R-Y signal

R-Y signal input pin in a color difference mode and standard PAL.64 B-Y in : B-Y signal B-Y signal input pin in a color difference mode and standard PAL. I Terminal Equivalent Circuits (continued) Pin 1 VCC1 Pin 59 GND 1 kΩ 1 kΩ Pin 1 VCC1 Pin 59 GND Pin 2 VREF 5 kΩ 5 kΩ 5 kΩ 17.5 kΩ 5 kΩ 5 kΩ 2 kΩ Pin 1 VCC1 Pin 59 GND Pin 2 VREF 5 kΩ 5 kΩ 5 kΩ 17.5 kΩ 5 kΩ 5 kΩ 2 kΩ I Usage Notes

• You are required to study adequately before using it in PAL.
• If the duty of PWM output is set to other than 0% to 100%, the jitter of the HD out put increases. So, confirm the horizontal jitter amount on the screen of the set you introduce the PWM function into.

In addition to its serial control by the conventional three-wire method, the AN2526NFH can be controlled by the I2C Bus. The transmission method is selected by the voltage to be applied to Pin 46. Three-wire control mode: Pin 46 = Low-level (connect to GND) I2C Bus mode: Pin 46 = High-level (Pin 41: connect to VDD ) It is recommended that the serial data is transferred during a vertical blanking period. 1. Three-wire control mode A serial data is of three-line system transmitting three kinds of signals of data, shift clock and load pulse independently. The data to be transmitted is made up by 12 bits in total of address (4 bits) and data (8 bits). The DAC is composed of four blocks of serial-parallel conversion, address decoder, data latch and ladder resistors, enabling to control 16 channels in total. Further, the mode setting such as the input signal switching is done by a serial data to reduce the pin count. 1) Serial data format D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address block Data block 2) Serial data input timing chart Timing chart expanded diagram D11 D10 D2 D1 D0Pin 48 S-data Pin 47 SCLK Pin 49 LD Pin 47 SCLK tCKH tCKL tDCH tCHD tCHL tLDH tLDC tcr tcf Pin 48 S-data Pin 49 LD

I Technical Data (continued) 1. Three-wire control mode (continued) 2) Serial data input timing chart (continued) Parameter Symbol Min Max Unit Clock low-level pulse width t CKL 500  ns Clock high-level pulse width t CKH 500  ns Clock rise time t cr  20 ns Clock fall time t cf  20 ns Data setup time t DCH 30  ns Data hold time t CHD 60  ns Load setup time t CHL 200  ns Load hold time t LDC 100  ns Load high-level pulse width t LDH 500  ns 3) Serial-data control contents D11 D10 D9 D8 Selection-ch. EVR control function Number of bit 0 0 0 0 0 Vertical sync. signal output position 3 1 0 0 0 1 Horizontal sync. signal output position 5 0 1 0 0 2 PWM duty 6 1 1 0 0 3 Common pulse amplitude 7 0 0 1 0 4 Y-gain 8 1 0 1 0 5 Color gain 7 0110 6 H u e 7 1 1 1 0 7 Black-limiter level 8 0 0 0 1 8 Bright 8 1 0 0 1 9 Y-aperture gain 8 0 1 0 1 10 R-ch. sub brightness 8 1 1 0 1 11 B-ch. sub brightness 8 0 0 1 1 12 White peak limiter level 8 1 0 1 1 13 Gamma-1 Knee level 8 0 1 1 1 14 Gamma-2 Knee level 8 1 1 1 1 15 RGB contrast 7 A variety of mode-settings for the channel for 8 bits or less is made by using the data stored in the data block. The contents of each mode setting are shown next.

I Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map.

• ch.0: Vertical sync. output position adjustment D11 D10 D9 D8 D7 D6 D5 D4 to D3 D2 D1 D0 EXCHF FIXHD BOSC Hor. PLL start position adjustment  0 Automatic switching  1 263H/313H fixed (NTSC/PAL) 0000  0 HD/VD output timing is serially variable  1 HD/VD output timing fixed

0 Odd number field: Advanced phase

1 Even number field: Advanced phase

• Vertical sync. output timing adjusting range Pin 35 input Composite sync. signal odd number field Pin 31 output odd number field FIXHD = "0" Pin 31 output odd number field FIXHD = "1" 2H to 9H(D0 to D2) Composite sync. signal even number field Pin 31 output EXCHF = "1" FIXHD = "0" Pin 31 output EXCHF = "1" FIXHD = "1" Pin 31 output EXCHF = "0" FIXHD = "1" Pin 31 output EXCHF = "0" FIXHD = "1" The above timing chart indicates (D2,D1,D0) = "101". For (D2,D1,D0) = "000", the pin 31 output width is 9H. The pin 31 timing is synchronous with the pin 35 input timing. The above timing chart is just for your reference. 2.5H to 9.5H (D0 to D2) 1.5H to 8.5H(D0 to D2)

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 V Mode YUV RGB  0 Video signal input display mode  1 Analog RGB input display mode 1000  0 Chroma signal input mode  1 Color-difference signal input mode

0 PAL

1 NTSC

The delay time of pin 30 output to video signal is likely to vary according to an external constant connected to pin 45. For an external constant, you are required to evaluate adequately the characteristics in weak electric field. Though the horizontal sync signal output adjustment range is designed by referring to the center of pin 30 output pulse, there would be some error according to VCO free-run frequency. I Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map. (continued)

• Horizontal PLL start position adjustment range
• ch.1: Horizontal sync. output position adjustment Pin 35 input Composite sync. signal odd number field Odd number field EXCHF = "1" EXCHF = "0" Composite sync. signal even number field 6H to 9H (D3 to D4) Horizontal PLL onHorizontal PLL off 0-line 1 2 3 5.5H to 8.5H (D3 to D4) Horizontal PLL onHorizontal PLL off 6.5H to 9.5H (D3 to D4) Horizontal PLL onHorizontal PLL off The above timing chart indicates (D4,D3) = "01". PLL stop line number: 254-line (NTSC) 302-line (PAL) Composite sync. signal input (video signal) Pin 30 Composite sync. signal output Pin 32 Horizontal sync. signal output Sync. sepa. delay time (Approximately 1 µs) Pin 32 Horizontal sync. signal output Pin 32 Horizontal sync. signal output ch.0 (D6) = "1" f h: Horizontal sync. frequency 347fh 32fy 32fy31fy 18fy Delay time (Approximately 400 ns) 1fy = (NTSC/PAL)

I Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map. (continued)

• ch.2: PWM duty adjustment D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P mode YC mode  0 Composite input mode 0100  1 Component input mode

0 STD ɹPAL mode

1 Quasi ɹPAL/NTSC mode

Note that adjustment characteristics come to discontinuation around max. Duty. = (110110): tw = 56H = (110111): tw = 56H = (111001): tw = 58H

• ch.3: Common pulse amplitude adjustment D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OSD

11000 A n a l o g OSD signal input mode

1 Digital OSD signal input mode

• ch.5: Color gain adjustment D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HTS 10100 1 H reverse inhibit mode 1 1H reverse mode
• ch.6: Hue adjustment D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CP

01100 External clamp pulse input mode

1 Internal clamp (pedestal) mode

: (NTSC/PAL)58 fh

I Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map. (continued)

• ch.9: Y-aperture gain adjustment D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1001 00h, 01h: Test mode
• ch.15: RGB contrast adjustment D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POL mode

11110 Internal POL 1H reverse mode

1 External POL 1H reverse mode

1. I 2C control mode A serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of signal lines of data and shift clock. When a slave address after setting a start condition matches the address on the IC side, you can receive the data to be transmitted from then. Once the stop condition is set up, the next transmitting data will be ignored until the start condition is set up. There are two kinds of transfer mode: an auto-increment mode which does not transmit sub-address, and data upgrade mode which transmits sub-address + data by 2 bites. The typical models of transmitting sequence are shown below: 1) Start condition When the S data changes from high-level to low-level at SCLK = high-level, a data receiving mode becomes available. 2) Slave address transfer The slave address of the AN2526NFH is 88h at pin 49 = high-level and 8Ah at pin 49 = low-level. Sub address transfer Acknowledge bit Pin 48 S-data Pin 47 SCLK 234 5678912 Start condition 3) Sub address transfer When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded as the data block. Data transferSlave address transfer Acknowledge bit D7 D6 D5 D4 D3 D2 D1 D0Pin 48 S-data Pin 47 SCLK 2345678989 12 Data transfer mode bit "1": Data update mode "0": Auto increment mode

I Technical Data (continued) 2. I 2C control mode (continued) 4) Data transfer 5) Stop condition When S-data changes from low-level to high-level at SCLK = high-level, data reception is halted. 6) Pulse timing Timing chart expanded diagram Acknowledge bit D7 D6 D5 D4 D3 D2 D1 D0Pin 48 S-data Pin 47 SCLK 2345678989 12 At auto increment mode: Data transfer At data update mode: Sub address transfer Pin 48 S-data Pin 47 SCLK tf tHDDATtLOW tBUF tHDSTA tr tHIGH tSUDAT tSUSTO Parameter Symbol Min Typ Max Unit SCLK clock frequency t SCL 0  400 kHz Bus free-time for stop condition and start condition t BUF 1.3  µ s Hold time start condition t HDSTA 0.6  µ s SCLK clock low-state hold time t LOW 1.3  µ s SCLK clock high-state hold time t HIGH 0.6  µ s Data hold time t HDDAT 0  µ s Data setup time t SUDAT 100  ns S-data, SCLK signal rise time t r  300 ns S-data, SCLK signal fall time t f  300 ns Stop condition setup time t SUSTO 0.6  µ s

D7 D6 to D4 D3 D2 D1 D0 Selection EVR control function Number channel of bit 0 0 0 0 0 Vertical sync. signal output position 3 0 0 0 1 1 Horizontal sync. signal output position 5 0 0 1 0 2 PWM duty 6 0 0 1 1 3 Common pulse amplitude 7 0 1 0 0 4 Y-gain 8 0 1 0 1 5 Color gain 7 0110 6 H u e 7 Mode Don't Care 0 1 1 1 7 Black-limiter level 8 1 0 0 0 8 Bright 8 1 0 0 1 9 Y-aperture gain 8 1 0 1 0 10 R-ch. sub bright 8 1 0 1 1 11 B-ch. sub bright 8 1 1 0 0 12 White peak limiter 8 1 1 0 1 13 Gamma-1 Knee level 8 1 1 1 0 14 Gamma-2 Knee level 8 1 1 1 1 15 RGB contrast 7 I Technical Data (continued) 2. I 2C control mode (continued) 6) Pulse timing (continued) In case that the ch. has 8 bits or less of data bit number, the data in the data block is used to set various modes. The content of each mode setting is same as three-wire control mode Parameter Symbol Range Min Typ Max Unit Composite video input signal Y IN Sync. chip - white 0.9 1.0 1.1 V[p-p] Y-input signal voltage Y IN Pedestal - white 0.6 0.7 0.8 V[p-p] C-input signal voltage C IN Burst signal amplitude 200 300 400 mV[p-p] MOS input signal low-level voltage V MOSL 0  0.8 V MOS input signal high-level voltage V MOSH 2.3  *1 V Synchronous signal input H SYNC Pedestal - sync. chip 0.2 0.3 0.4 V[p-p] Serial data transfer frequency f SD  1.0 MHz Analog RGB input signal RGB IN Pedestal - white 0.6 0.7 0.8 V[p-p] 3. Recommended Operating Conditions Note) *: Set it lower than V CC1 (Pin 1 voltage).

I New Package Dimensions (Unit: mm)

• QFP064-P-1010A (Lead-free package) 12.00±0.20 (1.00) 0.18±0.05 0.50±0.20 0° to 10° (1.25) 12.00±0.20 10.00±0.20 (1.25) 10.00±0.20 48 33 11 6 1764 1.95±0.200.10±0.10 0.15 ±0.05 Seating plane M0.10 0.50 0.10 1.600 1.576 1.400 1.200 1.000 0.800 0.814 0.600 0.400 0.200 0 25 150 Ambient temperature Ta (°C) Power dissipation PD (W) 50 75 100 125 0.000 Mounted on standard board (glass epoxy: 75 × 75 × t0.8mm3) Rth(j-a) = 79.3°C/W Independent IC without a heat sink R th(j-a) = 153.5°C/W I Technical Data (continued) 4. P D  Ta curves of QFP064-P-1010 PD  Ta

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2001 MAR