AN15865A

AN15865A PANASONIC

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1Publication date: March 2004 SDB00102AEB DATA SHEET SEMICONDUCTOR COMPANY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. AN15865APart No.

G(Y1-6)(CV1-7)/B(U1-6)(SY4-7)/ R(V1-6)(SC4-7)OUT5 H1/V1 G(Y1-6)(CV1-7)/B(U1-6)(SY4-7)/ R(V1-6)(SC4-7)OUT4 CV1-7(SY4-7)/ SC4-7OUT3 CV1-7(SY4-7)/ SC4-7OUT2 CV1-7/SY4-7/ SC4-7OUT1 AN15865A The video switch IC including the synchronous separation function for TV „ Overview The AN15865A has the video switch portion which consists of a five-channel output in a ten-channel input, the synchronous separation function, the AFC function, and the format detection function. It contributes to the rationalization design of a television system. „ Features 1. Support multi scan / Auto format identification 480i, 576i, 480P, 576P, 720P, 1080i, 1152i, 1152i/letter (both 50 Hz & 60 Hz) 2. Field 1 or 2 monitor out is available 3. Auto distinction in the selected input (Sync on CV/Y or Sync on SY or no input signal) 4. Dummy sync output 480i, 576i, 480P, 576P, 720P, 1080i (both 50 Hz & 60 Hz) 5. Sync separation with AFC w/o external x-tal or clock 6. 2 values, 3 values sync identification 7. RGB → YUV converter (CCIR standard, BTA standard, GBR matrix) 8. Each output can be switched between LPF (6 MHz) & through 9. Each output can be switched among 0 dB, 6 dB or mute 10. Macrovision 11. Comparators for Pin detection ×4 (Connected / Open) 12. Comparators for Aspect ratio ×4 (4:3 video / 4:3 letter box / 16:9 video) 13. High frequency (0 dB at 50 MHz) 14. Support the I 2C BUS 15. Various input mode can be selected by using flexible internal switch „ Applications yIC for Color TV „ Package y 80 Pin Plastic High Profile Quad Flat Package (QFP Type) „ Type y Silicon Monolithic BICMOS IC INPUT H1/V1Y1(G1)/U1(B1)/V1(R1)IN10 H2/V2Y2(G2)/U2(B2)/V2(R2)IN9 H3/V3Y3(G3)/U3(B3)/V3(R3)IN8 H4/V4Y4/U4/V4CV7/SY7/SC7IN7 H5/V5Y5/U5/V5CV6/SY6/SC6IN6 H6/V6Y6/U6/V6CV5/SY5/SC5IN5 Y7/U7/V7CV4/SY4/SC4IN4 CV3IN3 CV2IN2 CV1IN1 Note) *1: Independent HV only *2: Independent HV or Sync-separated HV

„ Application Circuit Example Note : VCC1, VCC2 = 9 V ± 0.5 V VCC3, VCC4 = 5 V ± 0.3 V SLVADR : 5 V( 8Chex / 8Dhex ) 0 V( 84hex / 85hex ) Output 2 Output 4 3.3 V Input 4 Input 5 Input 10 Output 5 Input 7 Input 8 Input Input Input 6 Input 9 Input 6 Input 9 0.01 µF Output 3 Output 1 Vin6 V6/SC5 Hin6 U6/SY5 SB5 Y6/CV5 SA5 CV1 GND1 CV2 SA3 SB3 CV3 U7/SY4 SA4 Y7/CV4 SB4 V7/SC4 SA6 Y5/CV6 SB6 U5/SY6 V5/SC6 Hin5 SY1 DCOUT SC1 CV2/SY2 GND SC2 GND2 SLVADR VCC3 G1/Y1 SC3 CV3/SY3 GND VCC2 CV1 Hout1 Vin5 Y4/CV7 Hin4 U4/SY7 Vin4 VCC1 V4/SC7 Hin3 B3/U3 Vin3 R3/V3 VCC4 Hin2 G2/Y2 G3/Y3 B2/U2 Hin1 B1/U1 Vin1 AFC1 R1/V1 Sync-out GND4 G1/Y1 Sync-in R2/V2 SDA SCL Field monitor R2/V2 Vout2 Hout2 B2/U2 GND3 G2/Y2 Vsyncsepa R1/V1 Vout1 B1/U1 Vin264 Input 9 V 5 V 10 kΩ 9 V 5 V 0.47 µF 4.7 µF 4.7 kΩ 75 kΩ 0.022 µF

( AFC-V or independent V ) ( AFC-H or independent H ) HVCO H Counter V Counter Phase detector independent V (selected) independent H (selected) H Sync Separation V Sync Separation Auto sync distinction Sync status Detector ( 2 or 3 ) MACRO VISION System mode control Automatic Polarity control H 2 Automatic Polarity control V 2 AFC filter V Switch 1 LOCK det Field monitor Sync-out V sync sepa H Switch 1 ( independent V ) ( independent H ) Automatic Polarity control V 1 Automatic Polarity control H 1 Vin1 Vin2 Vin6 Hin1 Hin2 Hin6 CV1 CV2 CV3 Y7/CV4 SY4 Y6/CV5 SY5 Y5/CV6 SY6 Y4/CV7 SY7 V Switch 2 System status check clamp Sync-in Vout1 Hout1 Vout2 Hout2 „ Block Diagram (SYNC separation and AFC system)

„ Block Diagram (continued) (Video-Switch) in6 in7 in5 in4 CV1 CV2 CV3 Y7/CV4 U7/SY4 V7/SC4 Y4/CV7 U4/SY7 V4/SC7 Hin4 Vin4 Y5/CV6 U5/SY6 V5/SC6 Hin5 Vin5 Y6/CV5 U6/SY5 V6/SC5 Hin6 Vin6 Sync-SepSync-Sep G3/Y3 B3/U3 R3/V3in8 G2/Y2 Hin3 Vin3 SB6 G1/Y1 B1/U1 R1/V1 Hin1 Vin1 B2/U2 R2/V2 Hin2 Vin2 SA4 SA5 SA6 SA3 SB4 SB5 SB3 Hout1 Vref Sync-Sep Vout1 Switch AFC Hout2 Vout2 in9 in10 out1 CV1 SY1 SC1 out2 out3 Switch Through SC3 6/0 dB 6/0 dB LPF 6/0 dB SC2 6/0 dB 6/0 dB 6/0 dB CV3/SY3 LPF LPF CV2/SY2 LPF 6/0 dB 6/0 dB 6/0 dB LPF LPF LPF G2/Y2 B2/U2 R2/V2 LPF6/0 dB LPF6/0 dB LPF6/0 dB out4 G1/Y1 B1/U1 R1/V1 LPF6/0 dB LPF6/0 dB LPF6/0 dB out5 CCIR BTA GBR Matrix 2 Matrix 3 CCIR BTA GBR Matrix 2 Matrix 3 in1 in2 in3 + + +

„ Pin Descriptions DescriptionTypePin namePin No. Sets the I2C bus slave addressInSLVADR35 CV2/SY2 signal outputOutCV2/SY234 GroundGroundGND231 CV3/SY3 signal outputOutCV3/SY330 GroundGroundGND29 B1/U1 signal outputOutB1/U124 Independent V signal output 1OutVout123 R1/V1 signal outputOutR1/V122 GroundGroundGND321 G2/Y2 signal outputOutG2/Y220 Independent H signal output 2OutHout219 B2/U2 signal outputOutB2/U218 Independent V signal output 2OutVout217 GroundGroundGND33 SC2 signal outputOutSC232 SC3 signal outputOutSC328

5.0 V power supplyPower supplyVCC327

G1/Y1 signal outputOutG1/Y126 Independent H signal output 1OutHout125 R2/V2 signal outputOutR2/V216 Field change signal outputOutField monitor15 V sync separation filterIn / OutV sync sepa14 Sync signal input for sync separationInSync-in13 Sync signal output for sync separationOutSync-out12 GroundGroundGND411 AFC filterIn / OutAFC110 R1/V1 signal inputInR1/V19 Independent V signal input 1InVin18 B1/U1 signal inputInB1/U17 Independent H signal input 1InHin16 G1/Y1 signal inputInG1/Y15 I2C bus clock inputInSCL4 I2C bus data inputIn / OutSDA3 R2/V2 signal inputInR2/V22 Independent V signal input 2InVin21

„ Pin Descriptions (continued) Y4/CV7 signal inputInY4/CV766 Independent V signal input 5InVin565 U4/SY7 signal inputInU4/SY768 Independent H signal input 4InHin467 CV4 signal inputInY7/CV454 Pin status detection for input channel 3InSB353 CV3 signal inputInCV352 Aspect ratio detection for input channel 3InSA351 CV2 signal inputInCV250 GroundGroundGND149 CV1 signal inputInCV148 Aspect ratio detection for input channel 5InSA547 Y6/CV5 signal inputInY6/CV546 Pin status detection for input channel 5InSB545 DescriptionTypePin namePin No. V4/SC7 signal inputInV4/SC770 Independent V signal input 4InVin469 V5/SC6 signal inputInV5/SC664 Independent H signal input 5InHin563 U5/SY6 signal inputInU5/SY662 Pin status detection for input channel 6InSB661 Y5/CV6 signal inputInY5/CV660 Aspect ratio detection for input channel 6InSA659 SC4 signal inputInV7/SC458 Pin status detection for input channel 4InSB457 SY4 signal inputInU7/SY456 Aspect ratio detection for input channel 4InSA455 U6/SY5 signal inputInU6/SY544 Independent H signal input 6InHin643 V6/SC5 signal inputInV6/SC542 Independent V signal input 6InVin641 CV1 signal outputOutCV140

9.0 V power supplyPower supplyVCC239

Output DC voltage corresponding to S2OutDCOUT37 SC1 signal outputOutSC136

„ Pin Descriptions (continued) B2/U2 signal inputInB2/U280 DescriptionTypePin namePin No. Independent H signal input 2InHin279 G2/Y2 signal inputInG2/Y278

5.0 V power supplyPower supplyVCC477

R3/V3 signal inputInR3/V376 Independent V signal input 3InVin375 B3/U3 signal inputInB3/U374 Independent H signal input 3InHin373 G3/Y3 signal inputInG3/Y372

9.0 V power supplyPower supplyVCC171

„ Absolute Maximum Ratings „ Operating supply voltage range 23ICC3, ICC4 NoteUnitRatingSymbolParameterA No. mA 130ICC1, ICC2 Supply current2 5.5VCC3, VCC4 *3°C−55 to +125TstgStorage temperature5 *3°C−20 to +75ToprOperating ambient temperature4 *2mW773PDPower dissipation3 *1V 10.0VCC1, VCC2 Supply voltage1 Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at T a = 75°C for the independent IC package without a heat sink. Refer to the package power dissipation prepared else and use under the condition not exceeding the allowable value. *3: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. NoteUnitRangeSymbolParameter *4.7 to 5.3VCC3, VCC4 V 8.5 to 9.5VCC1, VCC2 Operating supply voltage range Note) *: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.

„ Electrical Characteristics at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) T a = 25°C±2°C unless otherwise specified. Test circuits [Hout items] dB6.25.75.2G kHz15.8415.7515.65mode 480i fHFREE5Hout2 free-run Freq.521 kHz37.7237.5037.28mode 720p/50fHFREE4Hout2 free-run Freq.420 mode 1080i/50 mode 576i mode 1080i, 720p, 1152i, 1152i /letter mode 480i, 576i dB0–3–6

1.0 V[p-p] input at 6 MHz/500

(LPF ON) fLPF1LPF characteristic1 Measure the difference from the Output DC level while in mute mode.

1.0 V[p-p] input at 5 MHz

Between contiguity channels

1.0 V[p-p] input at 30 MHz/500

(during 6 dB output)(LPF OFF) No signal input VCC3, VCC4 Hz–7 0 0——fHPULLLOWH pull in range lower16 kHz15.7215.6215.53fHFREE1Hout2 free-run Freq.117 mode 480p, 576p V—3.3HHIHout1/2 high level 2.8 V0.4—dVDOOutput DC level – 0.4 mA2015ICQ34Quiescent Current 10 V0.5——HLOHout1/2 low level11 µs2.01.61.2HWID1Hout2 pulse width(1) 12 µs1.41.00.6HWID2Hout2 pulse width(2) 13 ns800660520HWID3Hout2 pulse width(3) 14 Hz——700fHPULLUPH pull in range upper15 kHz31.4331.2531.06mode 576p, 1152i, 1152i/letterfHFREE2Hout2 free-run Freq.218 kHz28.3428.1728.00fHFREE3Hout2 free-run Freq.319 mA127118109No signal input VCC1, VCC2ICQ12Quiescent Current1 dB0.3–0 . 2–0 . 7f = 500 kHz, VIN = 1 V[p-p] (except composite pass) GV0 Video Gain3 dB1.0—–1.5fV1 Video Frequency Response 14 dB1.0—–1.5 (during 0 dB output) (composite in) fV2 Video Frequency Response 2 5 dB–50——CTVCrosstalk6 dB–25——

1.0 V[p-p] input at 10 MHz/500

(LPF ON) fLPF2LPF characteristic29 Limits Typ Unit MaxConditions Note Min SymbolParameterB No.

„ Electrical Characteristics (continued) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) T a = 25°C±2°C unless otherwise specified. [DCOUT] V0.5——1VDCL S2 compatible DC level L [00]35 V2.8—1.41VDCM S2 compatible DC level M [01]36 V——4.01VDCH S2 compatible DC level H [11]37 [Address Pins] V1.5——1VADR1 Address setting voltage (84/85hex)33 V——2.51VADR2 Address setting voltage (8C/8Dhex)34 V—3.32.81VHIVout1/2 high level25 V0.5——1VLOVout1/2 low level26 H—6—AFC/free mode 480i, 480p, 1080i/601VWID1Vout2 pulse width(1) 27 H—6—AFC/free mode 576p, 1080i/501VWID2Vout2 pulse width(2) 28 H—6—AFC/free mode 1152i/letter1VWID3Vout2 pulse width(3) 29 H—5—AFC/free mode 720p/601VWID4Vout2 pulse width(4) 30 H—5—AFC/free mode 576i, 720p/501VWID5Vout2 pulse width(5) 31 H—6—AFC/free mode 1152i1VWID6Vout2 pulse width(6) 32 [Vout items] kHz45.3845.1144.84mode 720p/601fHFREE8Hout2 free-run Freq.824 kHz33.9033.7133.51mode 1 080i/601fHFREE7Hout2 free-run Freq.723 Test circuits kHz31.6031.4131.23mode 480p fHFREE6Hout2 free-run Freq.622 Limits Typ Unit MaxConditions Note Min SymbolParameterB No.

„ Electrical Characteristics (continued) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) T a = 25°C±2°C unless otherwise specified. Kbit/s——1001fimax Max. frequency allowable to input41 V0.4——The pin voltage with Pin 3 suction current set to 3 mA during Ack.1VACK Suction current during ACK38 V5.5—3.01VIHI SCL, SDA signal input high level39 V1.5—01VILO SCL, SDA signal input low level40 [I2C Interface] Test circuits Limits Typ Unit MaxConditions Note Min SymbolParameterB No. Note) The above characteristics are reference values on IC designing and not guaranteed by shipping inspection. START CONDITION SLAVE ADDRESS ACK SUB ADDRESS ACK DATA BYTE ACK STOP CONDITION SDA tBUF tSU.STA tHD.STA tSU.DAT tHD.DAT tLO tSU.STO SCL tR tF tHI tLO

„ Electrical Characteristics (Reference values for design) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V Note) T a = 25°C±2°C unless otherwise specified. *1V——2.51VSHVin H57 *1V1.5——1VSLVin L56 *1V——2.51HSHHin H55 *1V1.5——1HSLHin L54 [Others] *1V[p-p]——2.41VDYVInput Dynamic Range42 *1V—3.2—1.0 V[p-p] input 0 dB mode1VSYNCOutput sync level45 *1V—3.5—1VMMute DC level43 *1V—3.5—1.0 V[p-p] input 0 dB mode1VPEDOutput pedestal level44 [SA SB Pins] [Vout items] [Hout items] *1Hz—50—mode (V : 50 Hz) 1fVFREE1Vout2 free-run Freq.147 *1Hz—60—mode (V : 60 Hz) 1fVFREE2Vout2 free-run Freq.248 *1V1.0——1VSALScart ident SA L49 *1V3.0—1.71VSAMScart ident SA M50 *1V——4.01VSAHScart ident SA H51 *1V1.5——1VSBLPin detect SB L52 *1V——2.51VSBHPin detect SB H53 Test circuits *1kHz/ mV—–1.4—Conversion by 6 MHzBHH VCO osc. Chara.46 Reference values Typ Unit MaxConditions Note Min SymbolParameterB No. Note) *1 : The characteristics listed above are logical values derived from the design, and as such, all of these cannot be guarant eed. If, in the unlikely case that problems do occur related to these parameters, Panasonic will negotiate in good faith with the customer on these matters.

„ I2C Bus Conditions R/W 00184/8C 85/8D D6 D5D7Sub Address Note) The change of D3 data is performed by control of a SLVADR terminal Control Register continueASDATA (X + 1) DATA (X + 2)AS DATA (X) ASAS Sub Address (X) Slave Address (84 or 8C)S Note) AS = ACK from Slave 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50 000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60 00 : through 01 : CCIR standard 10 : BTA standard 11 : GBR matrix 00 : through 01 : CCIR standard 10 : BTA standard 11 : GBR matrix 00 : auto distinction 01 : sync on CV/Y use 10 : sync on SY use 11 : free-run OUT4 signal selectOUT3 signal select01 OUT5 signal select OUT5 sync 0 : AFC 1 : independent free-run priority 0 : fixing 1 : auto distinction use OUT5 sync distinction HVout2 polarity 0 : positive 1 : negative Dummy sync mode Control (When 02/D7, D6 = '11') OUT5 matrixOUT4 matrix03 OUT5 GAIN 0 : 0 dB 1 : 6 dB OUT4 GAIN 0 : 0 dB 1 : 6 dB SY3/SC3 GAIN 0 : 0 dB 1 : 6 dB CV3 GAIN 0 : 0 dB 1 : 6 dB SY2/SC2 GAIN 0 : 0 dB 1 : 6 dB CV2 GAIN 0 : 0 dB 1 : 6 dB SY1/SC1 GAIN 0 : 0 dB 1 : 6 dB CV1 GAIN 0 : 0 dB 1 : 6 dB Field monitor sel 0 : F1 / F2 out 1 : clock moni out 00 : 0 V 01 : 1.9 V 10 : indefinite 11 : 4.5 V OUT1 DCOUT OUT5 LPF 0 : through 1 : LPF ON OUT4 LPF 0 : through 1 : LPF ON OUT3 LPF 0 : through 1 : LPF ON OUT2 LPF 0 : through 1 : LPF ON OUT1 LPF 0 : through 1 : LPF ON Australia free-run 0 : except Australia 1 : Australia mode input10 BR/UV sel 0 : BR select 1 : UV select input9 BR/UV sel 0 : BR select 1 : UV select input8 BR/UV sel 0 : BR select 1 : UV select input7 U/SY sel 0 : SY select 1 : U select input6 U/SY sel 0 : SY select 1 : U select input5 U/SY sel 0 : SY select 1 : U select input4 U/SY sel 0 : SY select 1 : U select test70test71test72test73test74test75test76test7707 test80test81test82test83test84test85test86test8708 OUT2 signal selectOUT1signal select 00 D1 D0D4 D3 D2D6 D5D7Sub Address Note) Please send data "00" to sub-address "07" and "08". R/W = 0 y The AN15865A in I2C bus control performs switch mode selection, matrix selection, gain selection, LPF selection, synchronous mode selection and freerun mode selection through a control register and detects the system status, aspect and pin information through a status register. The upper seven address bits are allocated to the slave address while the LSB is allocated to the R/W bit. The R/W bit corresponds to the control register with with the bit set to 0 and corresponds to the status register with the bit set to 1. y The AN15865A selects slave address 84 or 8C(hex) according to the status of the SLVADR pin. Address 84(hex) will be selected with the SLVADR pin grounded the the GND side. Address 8C(hex) will be selected with the pin grounded to the 5-V line.

„ I2C Bus Conditions (continued) OUT1 signal select DCDCDC0111 DCDCDC0011 SC7 IN7 SY7 IN7 SY7 + SC7 IN7 IN70101 SC7 IN7 SY7 IN7 CV7 IN71001 SC6 IN6 SY6 IN6 SY6 + SC6 IN6 IN60001 DCDCDC1101 DCDCDC1011 SC4 IN4 SY4 IN4 CV4 IN41100 DCDCCV3 IN30100 SC5 IN5 SY5 IN5 CV5 IN51010 SC4 IN4 SY4 IN4 SY4 + SC4 IN4 IN40010 DCDCCV1 IN10000 DCDCCV2 IN21000 SC5 IN5 SY5 IN5 SY5 + SC5 IN5 IN50110 SC6 IN6 SY6 IN6 CV6 IN61110 DC *1DCDC1111 CV1 OUT1 SY1 OUT1 SC1 OUT100/D5 00/D400/D600/D7

„ I2C Bus Conditions (continued) OUT2 signal select SC7 IN7 SY7 + SC7 IN7 IN70111 SC7 IN7 CV7 IN70011 SC6 IN6 SY6 IN60101 SC6 IN6 CV6 IN61001 SC5 IN5 SY5 + SC5 IN5 IN50001 SC6 IN6 SY6 + SC6 IN6 IN61101 SC7 IN7 SY7 IN71011 SC4 IN4 CV4 IN41100 DCCV3 IN30100 SC4 IN4 SY4 + SC4 IN4 IN41010 SC4 IN4 SY4 IN40010 DCCV1 IN10000 DCCV2 IN21000 SC5 IN5 CV5 IN50110 SC5 IN5 SY5 IN51110 DC *1DC1111 CV2/SY2 OUT2 SC2 OUT200/D1 00/D000/D200/D3

„ I2C Bus Conditions (continued) OUT3 signal select SC7 IN7 SY7 + SC7 IN7 IN70111 SC7 IN7 CV7 IN70011 SC6 IN6 SY6 IN60101 SC6 IN6 CV6 IN61001 SC5 IN5 SY5 + SC5 IN5 IN50001 SC6 IN6 SY6 + SC6 IN6 IN61101 SC7 IN7 SY7 IN71011 SC4 IN4 CV4 IN41100 DCCV3 IN30100 SC4 IN4 SY4 + SC4 IN4 IN41010 SC4 IN4 SY4 IN40010 DCCV1 IN10000 DCCV2 IN21000 SC5 IN5 CV5 IN50110 SC5 IN5 SY5 IN51110 DC *1DC1111 CV3/SY3 OUT3 SC3 OUT01/D5 01/D401/D601/D7

„ I2C Bus Conditions (continued) OUT4 signal select indefiniteindefiniteDCDCCV1 IN10000 indefiniteindefiniteDCDCCV2 IN21000 indefiniteindefiniteDCDCCV3 IN30100 indefiniteindefiniteV7/SC4 IN4 U7/SY4 IN4 Y7/CV4 IN41100 Vin6 IN5 Hin6 IN5 V6/SC5 IN5 U6/SY5 IN5 Y6/CV5 IN50010 Vin5 IN6 Hin5 IN6 V5/SC6 IN6 U5/SY6 IN6 Y5/CV6 IN61010 Vin4 IN7 Hin4 IN7 V4/SC7 IN7 U4/SY7 IN7 Y4/CV7 IN70110 Vin3 IN8 Hin3 IN8 R3/V3 IN8 B3/U3 IN8 G3/Y3 IN81110 Vin2 IN9 Hin2 IN9 R2/V2 IN9 B2/U2 IN9 G2/Y2 IN90001 Vin1 IN10 Hin1 IN10 R1/V1 IN10 B1/U1 IN10 G1/Y1 IN101001 indefiniteindefiniteDCDCDC0101 indefiniteindefiniteDCDCDC1101 indefiniteindefiniteDCDCDC0011 indefiniteindefiniteDCDCDC1011 indefiniteindefiniteDCDCDC0111 indefiniteindefiniteDC *1DCDC1111 HOUT1 OUT4 VOUT1 OUT4 G1/Y1 OUT4 B1/U1 OUT4 R1/V1 OUT401/D1 01/D001/D201/D3

„ I2C Bus Conditions (continued) OUT5 signal select *2*2DCDCCV1 IN10000 *2*2DCDCCV2 IN21000 *2*2DCDCCV3 IN30100 *2*2V7/SC4 IN4 U7/SY4 IN4 Y7/CV4 IN41100 *2*2V6/SC5 IN5 U6/SY5 IN5 Y6/CV5 IN50010 *2*2V5/SC6 IN6 U5/SY6 IN6 Y5/CV6 IN61010 *2*2V4/SC7 IN7 U4/SY7 IN7 Y4/CV7 IN70110 *2*2R3/V3 IN8 B3/U3 IN8 G3/Y3 IN81110 *2*2R2/V2 IN9 B2/U2 IN9 G2/Y2 IN90001 *2*2R1/V1 IN10 B1/U1 IN10 G1/Y1 IN101001 *2*2DCDCDC0101 *2*2DCDCDC1101 *2*2DCDCDC0011 *2*2DCDCDC1011 *2*2DCDCDC0111 *2*2DC *1DCDC1111 HOUT2 OUT5 VOUT2 OUT5 G2/Y2 OUT5 B2/U2 OUT5 R2/V2 OUT502/D1 012D002/D202/D3 Note) *1 : 3.5 Vdc are outputted at the time of mute mode *2 : It is based on a setup of sync distinction

„ I2C Bus Conditions (continued) Status register continueAMDATA (X + 1) DATA (X + 2)AM DATA (X) AMSlave Address (85 or 8D)S 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : No use 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : No use Aspect ratio SA6 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : No use Aspect ratio SA5 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : No use Aspect ratio SA4 Aspect ratio SA3DATA0 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50 000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60 OUT5 System status AFC-LOCK 0 : unlock 1 : lock Pin detect SB6 0 : Open 1 : connect Pin detect SB5 0 : Open 1 : connect Pin detect SB4 0 : Open 1 : connect Pin detect SB3 0 : Open 1 : connect DATA1 Signal detect 0 : no signal 1 : signal input Australia format 0 : 1 152i 1 : 1 152i(letter) Australia interlace 0 : except Australia 1 : Australia auto distinc. Result sync fix 0 : continue 1 : fix auto distinc. Result CVSYdet 0 : SY 1 : CV MACRO VISION detection (OUT5) 0 : normal signal 1 : macro vision signal Sync status 0 : 2 value 1 : 3 value DATA2 D1 D0D4 D3 D2D6 D5D7 Note) The default data at the time of power-on is 0. Note) AM = Ack from Master R/W = 1 y The AN15865A selects slave address 85 or 8D(hex) according to the status of the SLVADR pin. Address 85(hex) will be selected with the SLVADR pin grounded the the GND side. Address 8D(hex) will be selected with the pin grounded to the 5-V line.

„ I2C Bus Conditions (continued) Description of Registers 1. Control Register Out1 signal select : Selects the Input IN1 to IN7 for OUT1(CV1, SY1, SC1) (Including Mute mode) Out2 signal select : Selects the Input IN1 to IN7 for OUT2(CV2, SY2, SC2) (Including Mute mode) Out3 signal select : Selects the Input IN1 to IN7 for OUT3(CV3, SY3, SC3) (Including Mute mode) Out4 signal select : Selects the Input IN1 to IN10 for OUT4(G1/Y1, B1/U1, R1/V1, Hout1, Vout1) Out5 Sync distinction : Switches the sync identification AFC circuit operating mode 0 = Automatic identification (with priority ranking) (If input signal to both CV and SY, SY signal will be selected) 1 = Uses CV or Y input 2 = Uses SY input 3 = Free-run Free-run priority : The priority of a free-run is changed 0 = Fixed mode 1 = Auto distinction will be started if a signal is inputted into a Sync block While input signal is removed, return to free-run mode. (Free-run priority only enabled when Out5 sync distinction = free-run) Out5 Sync : Selects H, V signal of Hout2, Vout2 whether independent H and V or AFC H and V 0 = AFC H and V 1 = independent H and V Out5 signal select : Selects the Input IN1 to IN10 for OUT5(G2/Y2, B2/U2, R2/V2, Hout2, Vout2) Out4 matrix : Selects the type of matrix conversion of Out4 0 = Through 1 = CCIR protocol 2 = BTA protocol 3 = Convert GBR to YUV Out5 matrix : Selects the type of matrix conversion of Out5 0 = Through 1 = CCIR protocol 2 = BTA protocol 3 = Convert GBR to YUV Dummy sync mode control : Selects the type of output sync format of Out5 0 = 480i / 60 1 = 480p / 60 2 = 1080i / 60 3 = 720p / 60 4 = 576i / 50 5 = 576p / 50 6 = 1 080i / 50 7 = 720p / 50 HVout2 polarity : Select the polarity of HOUT2 and VOUT2 at AFC mode 0 = positive, Sync level is high 1 = Negative, Sync level is low

„ I2C Bus Conditions (continued) CV1 GAIN : Select the gain of OUT1(CV1) 0 = 0 dB 1 = 6 dB SY1/SC1 GAIN : Select the gain of OUT1(SY1, SC1) 0 = 0 dB 1 = 6 dB CV2 GAIN : Select the gain of OUT2(CV2) 0 = 0 dB 1 = 6 dB SY2/SC2 GAIN : Select the gain of OUT2(SY2, SC2) 0 = 0 dB 1 = 6 dB CV3 GAIN : Select the gain of OUT3(CV3) 0 = 0 dB 1 = 6 dB SY3/SC3 GAIN : Select the gain of OUT3(SY3, SC3) 0 = 0 dB 1 = 6 dB OUT4 GAIN : Select the gain of OUT4(G1/Y1, B1/U1, R1/V1) 0 = 0 dB 1 = 6 dB OUT5 GAIN : Select the gain of OUT5(G2/Y2, B2/U2, R2/V2) 0 = 0 dB 1 = 6 dB OUT1 LPF : This switch selects LPF on/off of OUT1 0 = Through 1 = LPF ON OUT2 LPF : This switch selects LPF on/off of OUT2 0 = Through 1 = LPF ON OUT3 LPF : This switch selects LPF on/off of OUT3 0 = Through 1 = LPF ON OUT4 LPF : This switch selects LPF on/off of OUT4 0 = Through 1 = LPF ON OUT5 LPF : This switch selects LPF on/off of OUT5 0 = Through 1 = LPF ON OUT1 DCOUT : Selects the DC level to OUT1(SC1) . This DC level corresponds to S2 standard. 0 = 0 V 1 = 1.9 V 2 = indefinite 3 = 4.5 V Field monitor select : Selects the field distinction signal in interlace mode, or the oscillation clock of built-in VCO 0 = Field1/Field2 out (Field1 : Low Field2 : High) 1 = clock monitor out INPUT4 U/SY select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select

„ I2C Bus Conditions (continued) INPUT5 U/SY select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select INPUT6 U/SY select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select INPUT7 U/SY select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select INPUT8 BR/UV select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select INPUT9 BR/UV select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select INPUT10 BR/UV select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select Australia free-run : Set up, when you oscillate the free-run of the Australia signal 0 = except Australia 1 = Australia mode 2. Status Register Scart Ident SA3 : Return the control voltage of SA3(Pin 51) 0 = less than 1 V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite Scart Ident SA4 : Return the control voltage of SA4(Pin 55) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite Scart Ident SA5 : Return the control voltage of SA5(Pin 47) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite Scart Ident SA6 : Return the control voltage of SA6(Pin 59) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite Pin detect SB3 : Return the control voltage of SB3(Pin 53) 0 = 5 V(Open) 1 = 0 V(Connected) Pin detect SB4 : Return the control voltage of SB4(Pin 57) 0 = 5 V(Open) 1 = 0 V(Connected)

„ I2C Bus Conditions (continued) Pin detect SB5 : Return the control voltage of SB5(Pin 45) 0 = 5 V(Open) 1 = 0 V(Connected) Pin detect SB6 : Return the control voltage of SB6(Pin 61) 0 = 5 V(Open) 1 = 0 V(Connected) AFC-LOCK : Indicate the AFC lock status in the sync separation 0 = unlocked 1 = locked OUT5 System status : Return the input signal format after sync separated 0 = 480i / 60 4 = 576i / 50 1 = 480p / 60 5 = 576p / 50 2 = 1080i / 60 6 = 1080i / 50 3 = 720p / 60 7 = 720p / 50 Sync status : Return of identifying whether the input is ternary sync 0 = Binary sync 1 = Tri-level sync MACRO VISION : Indicate the whether to be a macro vision signal 0 = normal signal 1 = macro vision signal Auto Distinction Result of CV/SY detection : The detection result is indicated on which Sync shall have ridden between "CV" or "SY" 0 = SY 1 = CV Auto Distinction Result of Sync fixing situation : It indicates whether the detection result of Auto distinction fixed 0 = Under the check 1 = fixed Australia interlace : It indicates whether the input signal is Australia format 0 = except Australia 1 = Australia Australia format : It indicates the type of Australia format 0 = 1152i 1 = 1152i(litter) Signal detect : It indicates whether there is input signal 0 = no signal 1 = Signal input

„ Test Circuit Diagram BUS Control Vin6 V6/SC5 Hin6 U6/SY5 SB5 Y6/CV5 SA5 CV1 GND1 CV2 SA3 SB3 CV3 U7/SY4 SA4 Y7/CV4 SB4 V7/SC4 SA6 Y5/CV6 SB6 U5/SY6 V5/SC6 Hin5 SY1 DCOUT SC1 CV2/SY2 GND SC2 GND2 SLVADR VCC3 G1/Y1 SC3 CV3/SY3 GND VCC2 CV1 Hout1 Vin5 Y4/CV7 Hin4 U4/SY7 Vin4 VCC1 V4/SC7 Hin3 B3/U3 Vin3 R3/V3 VCC4 Hin2 G2/Y2 G3/Y3 B2/U2 Hin1 B1/U1 Vin1 AFC1 R1/V1 Sync-out GND4 G1/Y1 Sync-in R2/V2 SDA SCL Field monitor R2/V2 Vout2 Hout2 B2/U2 GND3 G2/Y2 Vsyncsepa R1/V1 Vout1 B1/U1 Vin264 5 V 9 V 0.47 µF 0.47 µF 0.47 µF 0.47 µF 0.47 µF 0.47 µF 0.47 µF 0.47 µF 0.47 µF 75 kΩ 22 nF 0.47 µF 0.47 µF 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ 10 nF 4.7 kΩ4.7 µF 10 µF 10 kΩ 0.47 µF 0.47 µF HV Signal GeneratorSignal Generator 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ Output 2 Output 4 Output 3 Output 1 5 V 9 V 10 µF 10 kΩ 10 µF 10 kΩ 10 µF 10 kΩ Output 5 Input 10 Input 4 Input 5 Input 7 Input 8 Input Input Input 6 Input 9 Input 3.3 V 10 µF 10 kΩ 10 µF 10 kΩ

„ Technical Data 1. Circuit diagrams of the input/output part and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. G/Y, B/U, R/V, U/SY, Y/CV signal input pins. Independent H, V signal input pins. DescriptionInner circuitPin No. VIN Pin 1, 8, 41, 65, 69, 75 HIN Pin 6, 43, 63, 67, 73, 79 G/Y Pin 5, 72, 78 B/U Pin 7, 74, 80 R/Y Pin 2, 9, 76 U/SY Pin 44, 56, 62, 68 Y/CV Pin 46, 48, 50, 52, 54, 60, 66 12k 3.7 V 4 V 90k 9 V 25µ 25µ 25µ 50µ 12k 34k 5 V 85k 60k 40k 75k 200k 2 V

I2C bus clock input pin.4 AFC filter pin.10 I2C bus data input pin.3 DescriptionInner circuitPin No. AFC1 Pin 10 SCL Pin 4 SDA Pin 3 50µ 5 V 12k 50k 1.9 V 30k90k 1.5k ACK 50µ 5 V 12k 50k 1.9 V 30k90k 1.5k 25µ 900µ 5 V 12k 9 V „ Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.

„ Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Sync signal output pin for sync separation.12 Sync signal input pin for sync separation.13 5V system ground pin.11 DescriptionInner circuitPin No. GND4 Pin 11 Sync-out Pin 12 Sync-in Pin 13 100µ 9 V 12k 100µ 12k 1.5V 60µ 80µ 1.3µ 40µ

„ Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Field change signal output pin.15 V sync separation filter pin.14 DescriptionInner circuitPin No. V sync sepa Pin 14 Field monitor Pin 15 12µ10µ 40µ 0.022µ 75k 17k 80k 12k 5 V

3.3 V9 V

„ Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Independent H, V signal output pins 5 V system ground pin.21 AFC or independent H, V signal output pins. G/Y, B/U, R/V, CV/SY, SC signal output pins. DescriptionInner circuitPin No. G/Y Pin 20, 26 B/U Pin 18, 24 R/V Pin 16, 22 CV/SY Pin 30, 34, 38, 40 SC Pin 28, 32, 36 100µ 9 V 12k 100µ Vout Pin 17, 23 Hout Pin 19, 25 GND3 Pin 21

„ Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin to output DC voltage corresponding to S2, which overlaps the SC1 signal on Output 1. The DC voltage varies with the setting in the control register. 9 V system ground pin.31 5 V system power supply pin. x Apply 5 V.27 DescriptionInner circuitPin No. 05/D2 05/D1 DC value 0 V 1.9 V indefinite 4.5 V 5 V 200k 60k 2 V 40k85k 34k 75k 12k SLVADR Pin 35 GND Pin 33 GND2 Pin 31 GND Pin 29 VCC3 Pin 27 DCOUT Pin 37 25µ50µ 35k 12k CIRCUIT 12k 5 V

„ Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. V/SC signal input pins. Pin status detection pins. Pin opened : No signal. Pin shorted : With signal. Status data is transferred to the microcomputer in serial. 9 V system power supply pin. x Apply 9 V.39 DescriptionInner circuitPin No. VCC2 Pin 39 12k 4 V 9 V 25µ 25µ 50µ 90k V/SC Pin 42, 58, 64, 70 SB Pin 45, 53, 57, 61 5 V 200k 60k 2 V 40k85k 34k 75k 12k CIRCUIT 12k 9 V

„ Technical Data (continued) 1. Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 9 V system power supply pin. x Apply 9 V.71 5 V system ground pin.49 5 V system power supply pin. x Apply 5 V.77 Aspect ratio detection pins. DescriptionInner circuitPin No. Pin voltage 5.0 V to 4.0 V 3.0 V to 1.7 V

1.0 V to 0 V

16 : 9 Letter-box 4 : 3 VCC1 Pin 71 VCC4 Pin 77 GND1 Pin 49 12k 34k 5 V 85k 29k 32k 24k 3.5 V 200k 39k 1.6 V 85k 85k SA Pin 47, 51, 55, 59 CIRCUIT 12k 9 V CIRCUIT 12k 5 V

„ Technical Data (continued) 2. Notes on video gain

1 V[p-p] 1 V[p-p]

2 V[p-p]

For 1 V[p-p] input signal, both 0 dB and 6 dB gain can be enabled. However, for 2 V[p-p] input signal, only 0 dB gain is allowed for normal operation. The gain of SY + SC can be controlled by Control Register SY/SC GAIN. SY/SC GAIN = 0 SY + SC = –6 dB SY/SC GAIN = 1 SY + SC = 0 dB please note that the gain of SY + SC is not controlled by Control Resister CV GAIN. 0 dB / 6 dB I2C control SY + SC 0 dB / 6 dB SY SC 3. Other supplementary matters y The remedy of APL change please attach resistance of 1 MΩ -3 MΩ to each pin of CV and SY between opposite GND by carrying out that it is hard to receive APL change. y How to output a synchronous separation output to Hout2 to Vout2 Please choose "1" by test76(07/D6) and out5 sync(02/D4) in a control register, respectively.

„ Usage Notes 1. For use, voltages above 5.5 V should not be applied to the following pins. (Pin No. 15, 17, 19, 23, 25) 2. Pay enough attention to that following items when using the IC, otherwise the IC may break or give off smoke. y Do not insert the IC in the reverse direction. 3. Keep in mind the it may cause a latch-up by the following pins in the examination of the method of pulse current. Pin number Merit level (mA) 46 –100 47 –90 52 –80 53 –70 62 –80 Be careful not to impress the pulse current more than the above. The current level is describing the merit value of the pulse current which a latch-up does not generate. However, in all pins, a latch-up is not caused by the examination of the CV method. (200pF 200V) 4. Purchase of Panasonic I 2C Components conveys a license under the Philips I2C patent right to use these components in an I2C systems, provided that the system conforms to the I2C standard specifications as defined by Philips.

Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteris- tics and applied circuits examples of the products. It neither warrants non-infringement of intellec- tual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instru- ments and household appliances). Consult our sales staff in advance for information on the following applications:

• Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body.
• Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maxi- mum rating, the range of operating power supply voltage, and heat radiation characteristics. Other- wise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.

2002 JUL