AN12975A PANASONIC
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- Manufacturer or author: Provided By digicamel.com
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Technical content
Datasheet sections
1Publication date: October 2008 SDE00029BEB AN12975APart No.
Stereo BTL amplifier IC with built-in AGC (I2C bus-control correspondence) Overview AN12975A is the stereo BTL amplifier which contained the AGC circuit for clip prevention of a speaker output. This IC performs a mode change by the I2C bus control system.(Standby function ON/OFF change etc.) Features ySelection by I2C bus control is possible in the on-level of AGC. (3-bit, 8-step) ySelection by I2C bus control is possible in an attack/recovery time of AGC. (attack: 2-bit , recovery: 3-bit) yThe resistance and the capacitor of a detector circuit which were being used for the conventional AGC are unnecessary. yIn order to realize high efficiency of output power, it adopts CMOS power amplifier circuit . Applications yAudio amplifier for mobile, such as a cellular phone Package y 20 pin plastic non lead package of four directions (LGA Type) Type y Silicon Monolithic Bi-CMOS IC
Application Circuit Example (Block Diagram) Note) This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. VCC_D VCC GND_SPL GND_SPR SPEAKER SPEAKER TEST1 LOUT (Positive) LOUT (Negative) ROUT (Negative) ROUT (Positive) 111213 VCC_SP VREFSP SADSCL 18GND 0.1 μF IN(R) VREF FB-L PREOUT-R IN(L) 10 kΩ +13 dB I2C-BUS Control 1.8 V ±0 dB +4 dB ±0 dB +4 dB AGC AGC DET 3 V 3 V 1 μF +13 dB +13 dB +13 dB TEST2 FB-R PREOUT-L 1 μF 1 μF 0.1 μF 1 μF 1 μF 100 pF 100 pF 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 8 Ω 8 Ω
Pin Descriptions First stage amplifier output L-ch.OutputPREOUT_L20 Negative feedback input stage amplifier L-ch.InputFB_L19 GroundGroundGND18 Negative feedback input stage amplifier R-ch.InputFB_R17 First stage amplifier output R-ch.OutputPREOUT_R16 Terminal of reference voltage InputVREF15 Power supply VCCPower SupplyVCC14 Terminal for testing (please connect to Ground)—TEST113 Terminal of reference voltage for SP output circuitInputVREF_SP12 SP amplifier R-ch. output (+)OutputROUT_POS11 Ground for SP R-ch. amplifier system GroundGND_SPR10 SP amplifier R-ch. output (–)OutputROUT_NEG9 Power supply VCC_SP for SP outputPower SupplyVCC_SP8 SP amplifier L-ch. output (–)OutputLOUT_NEG7 Ground for SP L-ch. amplifier system GroundGND_SPL6 SP amplifier L-ch. output (+)OutputLOUT_POS5 Power supply VCC_D for logic circuitPower SupplyVCC_D4 SDAInput / OutputSAD3 SCLInputSCL2 Terminal for testing (please connect to Ground)—TEST21 DescriptionTypePin namePin No.
Absolute Maximum Ratings Operating Supply Voltage Range *3Storage temperature5 Operating ambient temperature4 Power dissipation3 Supply current2 5.0VCC_SP —A—ICC *2mW222PD °C–55 to +150Tstg *3°C–20 to +70Topr 3.6VCC_D NoteUnitRatingSymbolParameterA No. *1V 3.6VCC Supply voltage1 VCC_SP 1.7 to 2.6 2.7 to 3.3VCC NoteUnitRangeSymbolParameter V 2.7 to 4.5 VCC_DSupply voltage range Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at T a = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the • PD –T a diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the powe r dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C. Note) The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
dBV–90–114⎯Vin = –31.0 dBV , f = 1 kHz RL = 8 Ω, using A curve filter VSSPOL VSSPORoutput level at power save15 mW⎯500300THD = 10% , f = 1 kHz RL = 8 Ω, AGC = OFF VMSPOL VMSPORSP maximum rating output14 dBV–71–78⎯Non-Signal using A curve filter VNSPOL VNSPORSP reference output noise voltage 13 %0.50.07⎯ mA1.00.3⎯ μA1.00.1⎯ mA6.03.91.5 Vin = –31.0 dBV , f = 1 kHz RL = 8 Ω, to THD 5th THSPOL THSPORSP reference output distortion VCC_SP = 3.0 V, Non-signal, STB = OFF, SP = OFF, AGC = ONIVCC2CCircuit current 1C at non-signal (VCC_SP) VCC_SP = 3.0V, Non-signal STB = ON, SP = OFF, AGC = ON IVCC2BCircuit current 2B at non-signal (VCC_SP) VCC = 3.0 V, Non-signal STB = OFF, SP = ON, AGC = ON IVCC1ACircuit current 1A at non-signal (VCC) Circuit Current dBV5.04.03.0 Vin = –12.0 dBV , f = 1 kHz RL = 8 Ω AGC – SELECT = [100] VSPOA2L VSPOA2RSP AGC output level 217 dBV5.04.03.0 Vin = –17.0 dBV , f = 1 kHz RL = 8 Ω AGC－SELECT = [100] VSPOA1L VSPOA1RSP AGC output level 116 Vin = –31.0 dBV , f = 1 kHz RL = 8 Ω VCC_D = 1.8 V, Non-signal STB = OFF, SP = OFF, AGC = ON VCC_D = 1.8 V, Non-signal STB = ON, SP = OFF, AGC = ON VCC_D = 1.8 V, Non-signal STB = OFF, SP = ON, AGC = ON μA1.00.1⎯VCC = 3.0 V, Non-signal STB = ON, SP = OFF, AGC = ONIVCC1BCircuit current 1B at non-signal (VCC)4 μA1.00.1⎯IVCC3BCircuit current 3A at non-signal (VCC_D)6 mA6.03.71.5VCC = 3.0 V, Non-signal STB = OFF, SP = OFF, AGC = ONIVCC1CCircuit current 1C at non-signal (VCC)7 μA100.1⎯IVCC3CCircuit current 1C at non-signal (VCC_D)9 Input/output characteristics mA24131.0VCC_SP = 3.0 V, Non-signal STB = OFF, SP = ON, AGC = ONIVCC2ACircuit current 2A at non-signal (VCC_SP)2 μA100.1⎯IVCC3ACircuit current 3A at non-signal (VCC_D)3 dBV–6.5–8.0–9.5VSPOL VSPORSP reference output level11 Limits Typ Unit Max No teMin ConditionsSymbolParameterB No. Electrical Characteristics at VCC = 3.0 V , VCC_D = 1.8 V , VCC_SP = 3.0 V Note) Ta = 25°C±2°C unless otherwise specified.
Electrical Characteristics at VCC = 3.0 V , VCC_D = 1.8 V , VCC_SP = 3.0 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. V0.2 × VCC_D⎯0Open corrector, Sync current: 3 mAVOL SDA output signal low level VVCC_D + 0.5⎯0.7 × VCC_DVIHSCL, SDA signal input low level44 V0.3 × VCC_D⎯–0 . 5VILSCL, SDA signal input low level43 I2C interface μA10⎯–10Input voltage: 0.1 V to 1.7 VIiSCL, SDA signal input current46 kHz400⎯0fSCL SCL maximum frequency of signal input 47 Limits Typ Unit Max No teMin ConditionsSymbolParameterB No.
*1μs⎯⎯0.6tHigh"H" time of SCL clock70 *1μs⎯⎯1.3tLow"L" time of SCL clock 69 *1μs⎯⎯0.6tHD;STAHold time of a condition for satart68 *1μs⎯⎯0.6tSU;STASetup time of a condition of start67 *1μs⎯⎯1.3tBUF Bass free time between a condition of stop and a condition of start66 *1μs⎯⎯0.6tSU;STORising up time of a condition of stop75 *1μs0.9⎯0tHD;DATData hold time74 *1μs⎯⎯0.1tSU;DATData setup time73 *1μs0.3⎯⎯tFfall time of SDA,SCL signal72 *1μs0.3⎯⎯tRrising time of SDA , SCL signal71 I2C interface Limits Typ Unit Max No teMin ConditionsSymbolParameterB No. Electrical Characteristics (Reference values for design) at VCC = 3.0 V , VCC_D = 1.8 V, VCC_SP = 3.0 V Note) Ta = 25°C±2°C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. tBUF tSU;DAT tHD;DAT tSU;STOtSU;STAtHD;STA tRtF tLow tHigh START CONDITION SAD SCL tR tF tHD;STA STOP CONDITION Repeated START CONDITION START CONDITION VIHmin VILmax (*2) (*3) Note) *1: All values are VIHmin (*2) and VILmax (*3) level standard. *2: VIHmin is the minimum limit of the signal input high level. *3: VILmax is the maximum limit of the signal input low level.
Technical Data yI2C-bus Mode 1. Write Mode Two transmission messages (i.e., the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame. <Start Conditions> When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver will be enabled. <Stop Conditions> When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver will be aborted. <Slave Address> The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be aborted. <Sub Address> The sub address is a specified one unique to each function. <Data> Data is information under control. <Acknowledge Bit> The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level signal returned from the receiver as shown by the dotted lines in Fig. The communication will be aborted if the low signal is not returned. The SDA will not change when the level of the SCL is high except start or stop conditions are enabled. SAD SCL START CONDITION SLAVE ADDRESS ACK SUB ADDRESS ACK DATA ACK STOP CONDITION Example of transmission messages 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 01 8 0 1 0 0 0 0 0 0 0
Technical Data (continued) yI2C-bus Mode (continued) 1. Write Mode (continued) (a) I2C-bus PROTOCOL x Slave address: 10110110 (B6Hex) x Format (normal) S Slave address A Sub address A Data 1 A P Data 2 A Data n AW (b) Auto increment x Sub-address 0*Hex: Auto increment mode (When the data is sent in sequence, the sub address will change one by one and the data will be input.) x Auto increment mode (c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0 (Note.1) will be absolutely 0, when the power is turned ON. (d) Sub-address Byte and Data Byte Format (Note.2) AGC-ATT data bit1 AGC-ATT data bit2 AGC-REC data bit1 AGC-REC data bit2 AGC-REC data bit3 AGC-ON data bit1 AGC-ON data bit2 AGC-ON data bit3*1Hex (Note.2) (Note.2) Standby 0 → ON 1 → OFF (Note.1) SP Save 0 → ON 1 → OFF (Note.2) D1 D0 LSB AGC 0 → OFF 1 → ON (Note.2) (Note.2) (Note.2) Data byte (Note.2)*2Hex ＊*0Hex MSB Sub-address S Slave address A Sub address A Data byte A P Stop condition Acknowledge bitStart condition W Write Mode: 0 Please use these bit only Data = "0", because they are used by our company’s final test and fine-tuning AGC-on level. <00Hex Register> D0, D4, D5, D6, D7: Always set to 0 D1: Standby ON/OFF switch D2: SP Save ON/OFF switch D3: AGC ON/OFF switch <01Hex Register> D0, D1 : AGC-attack-time selection D2, D3, D4: AGC-recovery-time selection D5, D6, D7: AGC-on-level selection <02Hex Register> D0 to D7: Always set to 0 (test&adjust mode) (Note.2)
Technical Data (continued) yI2C-bus Mode (continued) 1. Write Mode (continued) (e) AGC-attack-time selection (f) AGC-recovery-time selection Write 01Hex Register 4 ms11 2 ms01 Attack time 1m s 0.5 ms 4.0 s001 6.0 s101 2.0 s010 8.0 s011 Write 01Hex Register 12.0 s11 3.0 s10 Recovery time 1.5 s 1.0 s (g) AGC-on-level selection (at VCC = 3.0 V, VCC_SP = 3.0V)
4.1 V ≤ *
3.7 V ≤
3.3 V ≤
3.0 V ≤
VCC_SP Recommend) 7d B v 6d B v 5d B v 4d B v 3d B v 2d B v 1 dBv 0 dBv AGC On Level 626 mΩ 498 mΩ 395 mΩ 314 mΩ 249 mΩ 198 mΩ 157 mΩ 125 mΩ Output Po ( Ω ) 001 101 010 011 Write 01Hex Register Note) *: We recommend more than VCC = 2.9 V for 7 dBV output level.
Technical Data (continued) yI2C-bus Mode (continued) 2. Read Mode (a)I2C-bus PROTOCOL x Slave address 10110111(B7Hex) x Format Read Mode: 1 (b) Sub-address Byte and Data Byte Format Sub address *1Hex Latch data [D0] Sub address *1Hex Latch data [D1] Sub address *1Hex Latch data [D2] Sub address *1Hex Latch data [D3] Sub address *1Hex Latch data [D4] Sub address *1Hex Latch data [D5] Sub address *1Hex Latch data [D6] Sub address *1Hex Latch data [D7] Data 1 Sub address *0Hex Latch data [D0] Sub address *0Hex Latch data [D1] Sub address *0Hex Latch data [D2] Sub address *0Hex Latch data [D3] Sub address *0Hex Latch data [D4] Sub address *0Hex Latch data [D5] Sub address *0Hex Latch data [D6] Sub address *0Hex Latch data [D7] Data 0 Data byte Data 2 Sub address *2Hex Latch data [D1] Sub address *2Hex Latch data [D0] LSB Sub address *2Hex Latch data [D2] Sub address *2Hex Latch data [D3] Sub address *2Hex Latch data [D4] Sub address *2Hex Latch data [D5] Sub address *2Hex Latch data [D6] D6D7 Sub address *2Hex Latch data [D7] MSB S Slave address A Data 0 A P Data 1 A Data 2 AR Purchase of Panasonic I2C components conveys a license under the Philips I2C patent right to use these components in an I2C systems, provided that the system conforms to the I2C standard specification as defined by Philips. Note) At the slave address input, it is sequentially output from data 0. There is no necessity for inputting the sub-address. The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25°C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics ,Panasonic will respond in good faith to customer concerns. y Operating temperature guarantee of I2C-bus Control
Technical Data (continued) yI/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. I2C-bus SCL pin SCL Hi-Z I2C-bus SDA pin SAD Hi-Z Power supply pin for I2C-bus－ VCC_D 1.8 V(typ.) TEST mode output pin It is Hi-Z at normal operation. Please connect to GND. Test2 Hi-Z DescriptionInternal circuitWaveform and voltage Pin No. VCC VCC_D VCC_D GND
Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Ground pin for L-ch. speaker output－GND_SPL6 L-ch. negative speaker output pin LOUT_NEG DC 1.45 V Power supply pin for speaker output－ VCC_SP 3.0 V(typ.) L-ch. positive speaker output pinLOUT_POS DC 1.45 V DescriptionInternal circuitWaveform and voltage Pin No. VCC_SP GND_SPL 400k VCC_SP GND_SPL 400k
Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. GND pin for R-ch. speaker output－GND_SPR10 R-ch. negative speaker output pin ROUT_POS DC 1.45 V Reference voltage pin for output stage VREF_SP DC 1.45 V R-ch. positive speaker output pin ROUT_NEG DC 1.45 V DescriptionInternal circuitWaveform and voltage Pin No. VCC_SP GND_SPR 400k VCC_SP GND_SPR 400k VCC_SP 10k 150k 150k
Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Power supply pin－ VCC 3.0 V(typ.) Reference voltage pin VREF DC 1.45 V First stage amplifier L-ch. output pinPREOUT_R DC 1.45 V Test mode pin Please connect to GND. Test1 Hi-Z DescriptionInternal circuitWaveform and voltage Pin No. VCC 10k 150k 150k VCC 10k
Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Ground pin－GND18 Negative feedback pin for input stage amplifier L-ch. FB_L DC 1.45 V First stage amplifier L-ch. output pin PREOUT_L DC 1.45 V Negative feedback pin for input stage amplifier L-ch. FB_R DC 1.45 V DescriptionInternal circuitWaveform and voltage Pin No. 10k 10k VCC 10k
Technical Data (continued) yPower supply and logic sequence Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching. 1. The sequence of the power supply and each logic Power supply Standby SP_Save 1 ms or more 20 ms or more * VCC,VCC_SP, VCC_D Please first bring up the power supply, and then the standby off. Off On Off Off On On On On Off Off On Off The basic procedure at the power-on 1. The power OFF condition Both the standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby Off 4. SP_Save Off The basic procedure at the power-off 2．The sequence of VCC and VCC_SP and VCC_D This IC have not a standup and falling order in VCC and VCC_SP. A standup and falling time of VCC and VCC_SP recommend 1 or more ms. VCC Off On On Off VCC_SP 1 ms or more VCC_D 0 ms or more 1. The power ON condition Both the standby and the SP_Save are in the OFF condition. 2. SP_Save On ( = Standby On) 3. Standby On 4. Power Off After at least 20 ms has passed after the standby off, please off SP_Save. Please control Standby On to simultaneous with SP_Save On, or the back. Note) *: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN_R and IN_L). It is a recommendation value in a constant given in the example of Application Circuit Example (Block Diagram).
Technical Data (continued) yPD ⎯ Ta diagram
Usage Notes 1. Please take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as SP output pin (Pin5, Pin7, Pin9, Pin11) – power supply pin short, SP output pin (Pin5, Pin7, Pin9, Pin11) – GND short, or SP output (Pin5, Pin7, Pin9, Pin11)-to-SP output-pin short (load short). 2. Please absolutely do not mount the IC in the reverse direction on to the printed-circuit-board. It damaged when the electricity is turned on.
Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod- ucts may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or im- provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805